DATA SHEET
MOS INTEGRATED CIRCUIT
µPD16661A
160-OUTPUT LCD COLUMN (SEGMENT) DRIVER WITH RAM
The µPD16661A is a column (segment) driver containing a RAM capable of full-dot LCD drive. With 160 outputs,
this driver has an on-chip display RAM of 160 × 240 × 2 bits. The driver can be combined with the µPD16666A to
display from 1/8 VGA to VGA (640 × 480 dots).
The µPD16661A is upwardly compatible with the µPD16661.
FEATURES
• Display RAM incorporated : 160 × 240 × 2 bits
• Logic voltage : 3.0 to 3.6 V
• Duty : 1/240
• Output count : 160 outputs
• Capable of gray scale display : 4 gray scales (frame thinning-out)
• Memory management : packed pixel system
• 8/16-bit data bus
ORDERING INFORMATION
★
Part Number
Package
µPD16661AN-×××
TCP (TAB)
µPD16661AN-051
Standard TCP (OLB : 0.2 mm-pitch, pliable-output leads)
Remark The TCP package is custom made, so contact an NEC sales representative with your requirements.
The information in this document is subject to change without notice.
Document No. S11498EJ3V0DS00 (3rd edition)
Date Published November 1998 NS CP (K)
Printed in Japan
The mark ★ shows major revised points.
NEC Corporation 1996,1998
µPD16661A
PIN NAMES
Pin Name
Classification
CPU interface
3.3 V
Control signals
Note
I/O
Pad No.
Function
D0 to D15
I/O
A0 to A16
I
Address bus : 17 bits
/CS
I
Chip select
/OE
I
Read signal
/WE
I
Write signal
/UBE
I
Upper byte enable
RDY
O
Ready signal to CPU (Ready state at "H")
Data bus : 16 bits
PL0
I
Specifies the LSI placement positions (No. 0 to 7)
PL1
I
Specifies the LSI placement positions (No. 0 to 7)
PL2
I
Specifies the LSI placement positions (No. 0 to 7)
DIR
I
Specifies the liquid-crystal panel placement direction
MS
I
Master/slave selection pin (Master mode at "H")
BMODE
I
Data bus bit selection pin ("H" = 8 bits, "L" = 16 bits)
GMODE
I
Gray scale data weight reverse switching
3.3 V
(When data = [1,1], "L" = black, "H" = white)
/REFRH
I/O
Self-diagnosis reset pin (wired-OR connection)
TEST
I
Test pin ("H" = test mode, on-chip pull-down resistor)
/RESET
I
Reset signal
/DOFF
I
Display OFF input signal
OSC1
−
Oscillator externally-attached resistor pin
OSC2
−
Oscillator externally-attached resistor pin
STB
I/O
Column drive signal (MS pin "H" = output, MS pin "L" = input)
/FRM
I/O
Frame signal (MS pin "H" = output, MS pin "L" = input)
L1
I/O
Row driver drive level selection signal (1st line)
L2
I/O
Row driver drive level selection signal (2nd line)
/DOUT
O
Display OFF output signal
Liquid-crystal drive
Y1 to Y160
O
Liquid-crystal drive output
Power supplies
GND
−
Ground (two pins for VCC1 system , three pins for VCC2 system)
VCC1
−
5-V power supply
VCC2
−
3.3-V power supply
V0
−
Liquid-crystal drive analog power supply
V1
−
Liquid-crystal drive analog power supply
V2
−
Liquid-crystal drive analog power supply
5.0 V
Note 3.3-V pin : D0 to D15, A0 to A16, /CS, /OE, /WE, /UBE, RDY, BMODE, GMODE, PL0, PL1, PL2, DIR, OSC1,
OSC2, /RESET, /DOFF, TEST, MS
5-V pin : STB, /FRM, L1, L2, /DOUT
★ Remark /xxx indicates active low signal.
2
µPD16661A
BLOCK DIAGRAM
DIR
PL0,1,2
TEST
A0 to A16
Address
input
control
Address
management
circuit
RAM
160x240x2 bits
Arbiter
Control
/CS,/OE,
/WE,/UBE
RDY
BMODE
D0 to D15
Data bus
control
GMODE
/REFRH
Data latch(1)
/RESET
MS
STOP
Frame
thinning-out
FRC control
OSC1
CR
oscillator
Internal timing
generation
OSC2
/DOFF
Data latch(2)
Liquid-crystal
timing generation
3.3 V operation
/FRM STB
Self-diagnosis
circuit
3.3 V operation
Level shifter
5.0V operation
5.0 V operation
DEC
V0
V1
V2
Liquid-crystal drive
circuit
160 outputs
/FRM
STB /DOUT L1
L2
Y1 Y2 Y3
Y160
3
µPD16661A
1. BLOCK FUNCTIONS
(1) Address management circuit
The address management circuit converts the addresses transferred from the system via A0 to A16 into
addresses compatible with the memory map of the on-chip RAM.
This function can be used to address up to VGA size (480 × 640 dots) with 8 of these LSIs, thus making it
possible to configure a liquid-crystal display system without difficulty.
(2) Arbiter
The arbiter adjusts the contention between the RAM access from the system and the RAM read on the liquidcrystal drive side.
(3) RAM
Static RAM (single port) of 160 × 240 × 2 bits
(4) Data bus control
The data bus controls the data transfer directions by means of Read/Write from the system.
The mode can be switched from 8 bits to 16 bits by the BMODE pin, and the relation between the display data
and the gray scale can be switched by the GMODE pin.
(5) Frame thinning-out control
The frame thinning-out control indicates the four gray scales with three thinning-out frames. The thinning-out
method can be changed in units of 9 pixels (3 columns × 3 lines).
(6) Internal timing generation
The internal timing to each block is generated from the /FRM and STB signals.
(7) CR oscillator
In master mode, this oscillator generates the clock that is the reference for the frame frequency. The frame
frequency is one 484th (1/484) of this oscillation. For example, if the frame frequency is 80 Hz, an oscillation
frequency of 38.72 kHz is necessary. As the CR has a built-in capacitance, adjust the required oscillation
frequency with an externally attached resistor.
In slave mode, oscillation is stopped.
(8) Liquid-crystal timing generation
In master mode, /FRM (the frame signal) and STB (the column drive signal strobe) are generated.
(9) FRC control
This circuit realizes the four gray-scale displays.
4
µPD16661A
(10) Data latch (1)
This data latch reads and latches 160-pixel data from the RAM.
(11) Data latch (2)
This data latch synchronizes with the STB signal and latches 160-pixel data.
(12) Level shifter
The level shifter converts the voltage from the operating voltage of the internal circuit (3.3 V) to the voltage of the
liquid-crystal drive circuit and row driver interface (5.0 V).
(13) DEC
The DEC decodes the gray scale display data to make it compatible with the liquid-crystal drive voltages V0, V1,
and V2.
(14) Liquid-crystal drive circuit
This circuit selects one of the display OFF signal (/DOFF)-compatible liquid-crystal drive power supplies V0, V1,
or V2, and generates the liquid-crystal applied voltage.
(15) Self-diagnosis circuit
This circuit automatically detects any occurrence of an operation timing lag between the master chip and the
slave chip that has been caused by outside noise, and sends a refresh signal to all the column drivers.
2. MEMORY MAP
Address
Description
A16
0
A0
0
0
0
0
H
Display data of Nos. 0, 2, 4, and 6
0
0
H
Display data of Nos. 1, 3, 5, and 7
A
0
H
F
F
H
:
:
0
F
0
:
:
1
D
F
Unused
:
1
F
F
5
µPD16661A
Address map image diagram (Example of VGA-size configuration)
Column direction specified with A7 to A0
Y1
Y1
Y1
Y160
Line direction specified
Y1
Y160
Y160
Y160
L1
Address setting direction
with A16 to A8
L240
No.0
No.2
No.4
No.6
L1
Address setting direction
L240
No.1
No.3
Y1
Y160
6
No.5
Y1
Y160
No.7
Y1
Y160
Y1
Y160
µPD16661A
3. DATA BUSES
The method for lining up byte data on the data bus line is essentially the Little Endian system adopted by NEC
and Intel Corp.
3.1 16-bit data bus (BMODE = L)
Byte unit access
D0 to D7
D8 to D15
The address setting direction →
00000H
00001H
is as shown on the right.
00002H
00003H
00004H
00005H
:
:
:
:
D0 to D7
D8 to D15
Word unit access
The address setting direction →
00000H
is as shown on the right.
00002H
00004H
:
:
For access from the system to be performed in word units (16 bits), or byte units (8 bits), /UBE (upper-byte
enable) and A0 are used to show whether valid data is in the bytes of either (or both) D0 to D7 or D8 to D15.
I/O
/CS
/OE
/WE
/UBE
A0
MODE
D0 to D7
D8 to D15
H
X
X
X
X
Not selected
Hi-z
Hi-z
L
L
H
L
L
H
L
H
L
Read
Dout
Hi-z
Dout
Dout
Dout
Hi-z
L
H
L
L
L
H
L
H
L
Write
Din
X
Din
Din
Din
X
L
L
H
X
H
X
X
H
X
H
Output
disable
Hi-z
Hi-z
Hi-z
Hi-z
Remark X : Don’t care, Hi-z : High impedance
7
µPD16661A
3.2 8-bit data bus (BMODE = H)
D0 to D7
The address setting direction →
00000H
is as shown on the right.
00001H
00002H
:
:
I/O
/CS
/OE
/WE
MODE
D0 to D7
D8 to D15
H
X
X
Not selected
Hi-z
Note
L
L
H
Read
Dout
Note
L
H
L
Write
Din
Note
L
H
H
Output disable
Hi-z
Note
Note When BMODE = H, D8 to D15 and /UBE are pulled down internally, so either leave them open, or
connect them to the GND.
Remark X : Don’t care, Hi-z : High impedance
8
µPD16661A
4. RELATIONSHIP BETWEEN DATA BITS AND PIXELS
Because the display is in four gray scales, each pixel consists of two bits.
The RAM is configured with four pixels (8 pixels per word) using the packed pixel system.
(1) BMODE = L
In byte unit access (8 bits)
D0
D1
Pixel 1
D2
D3
D4
Pixel 2
D5
Pixel 3
D6
D7
D8
Pixel 4
D9
D10 D11 D12 D13 D14 D15
Pixel 5
Pixel 6
Pixel 7
Pixel 8
00000H
Liquid-Crystal
Panel
00001H
Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
00000H
00001H
00002H
00003H
In word unit access (16 bits)
D0
D1
Pixel 1
D2
D3
Pixel 2
D4
D5
Pixel 3
D6
D7
D8
Pixel 4
D9
Pixel 5
D10 D11 D12 D13 D14 D15
Pixel 6
Pixel 7
Pixel 8
00000H
Liquid-Crystal
Panel
Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
00000H
00002H
(2) BMODE = H
D0 D1
D2 D3
D4 D5
Pixel 1
Pixel 2
Pixel 3
D6
D7
Pixel 4
D0
D1
D2 D3
D4 D5
Pixel 5
Pixel 6
Pixel 7
D6
D7
Pixel 8
00000H
Liquid-Crystal
Panel
00001H
Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
00000H
00001H
00002H
00003H
9
µPD16661A
5. RELATIONSHIP BETWEEN DISPLAY DATA AND GRAY-SCALE LEVEL
(1) GMODE = L
Gray Scale
Dn
Display State
Dn+1
Liquid-Crystal State
Level
0
0
0
1
0
1
0
1
2
1
1
3
OFF
Display
OFF State
ON
(2) GMODE = H
Gray Scale
Dn
Display State
Dn+1
Liquid-Crystal State
Level
10
1
1
3
0
1
2
1
0
1
0
0
0
OFF
Display
OFF State
ON
µPD16661A
6. LSI PLACEMENT AND ADDRESS MANAGEMENT
Addresses can be managed to allow the use of a maximum of eight µPD16661A devices for configuring a liquidcrystal display of up to VGA size (480 × 640 dots).
Up to eight of these LSIs can be connected to the same data bus and to the /CS, /WE, and /OE pins, which are
shared.
One screen of the liquid-crystal display can be treated as one memory area in the system, so it is not necessary
to decode more than one µPD16661A device.
The PL0, PL1, and PL2 pins are used to specify the LSI No. and determine the LSI placement. The DIR pin is
used to determine the direction (perpendicular, lateral) of the liquid-crystal display.
PL2
PL1
PL0
LSI No.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No. 0
No. 1
No. 2
No. 3
No. 4
No. 5
No. 6
No. 7
11
µPD16661A
Landscape VGA size address
DIR = “0”
Specified with A7 to A0
Y8
Y160
Y8
Y153
Y1
Y153
L1
00000
00026
00028
L2
00100
00126
00128
No.0
Specified with
A16 to A8
Y8
Y160
Y1
Y8
Y160
Y153
Y1
Y153
0004E 00050
00076
00078
0009E
0014E 00150
00176
00178
0019E
No.2
No.4
No.6
L239 0EE00
0EE26 0EE28
0EE4E 0EE50
0EE76 0EE78
0EE9E
L240
0EF00
0EF26 0EF28
0EF4E 0EF50
0EF76 0EF78
0EF9E
L1
0F000
0F026
0F028
0F04E 0F050
0F076
0F078
0F09E
L2
0F100
0F126
0F128
0F14E 0F150
0F176
0F178
0F19E
No.1
No.3
No.5
No.7
L239 1DE00
1DE26 1DE28
1DE4E 1DE50
1DE76 1DE78
1DE9E
L240 1DF00
1DF26 1DF28
1DF4E 1DF50
1DF76 1DF78
1DF9E
Y153
Y160
12
Y160
Y1
Y1
Y8
Y153
Y160
Y1
Y8
Y153
Y160
Y1
Y8
Y153
Y160
Y1
Y8
No.6
Y160
Y8
Y153
Y160
Y1
1DF78 1DF76
1DF9E
Y153
1DE78 1DE76
0F178 0F176
0F19E
1DE9E
0F078 0F076
0F09E
No.7
0EF78 0EF76
0EF9E
No.5
No.4
Y8
Y153
Y160
Y1
1DF50 1DF4E
1DE50 1DE4E
0F150 0F14E
0F050 0F04E
0EF50 0EF4E
0EE50 0EE4E
00150 0014E
No.3
No.2
00126
00026
Y8
Y8
Y153
Y160
Y1
1DF28 1DF26
1DE28 1DE26
0F128 0F126
0F028 0F026
0EF28 0EF26
0EE28 0EF26
00128
00028
Y1
Y160
Y153
No.1
No.0
Specified with
A7 to A0
0EE78 0EE76
00176
Y8
00050 0004E
Y1
Y160
Y153
Y160
Y8
Y1
1DF00
1DE00
0F100
0F000
0EF00
0EE00
00100
00000
Y153
L240
L239
L2
L1
L240
L239
L2
L1
Portrait VGA size address
0EE9E
00178
0019E
Y8
00076
Y1
Y160
Y153
00078
Y8
0009E
Y1
µPD16661A
DIR = “1”
Specified with A16 to A8
13
µPD16661A
7. CPU INTERFACE
7.1 Function of the RDY (Ready) pin
The on-chip RAM uses a single-port RAM. In order to avoid conflict between accessing from the CPU side
and reading on the liquid-crystal drive side, the RDY pin performs a wait operation on the CPU.
(1) Timing
★
A0 to A16,/UBE
/CS
/OE,/WE
Hi-z
Hi-z
RDY
Wait
Ready
Wait
(2) Connection of the RDY pin
The RDY pin uses a 3-state buffer. Externally attach a pull-up resistor to the RDY pin.
When more than one µPD16661A is used, wired-OR connect each LSI RDY pin.
VCC2
CPU
Pull-up resistor
Ready input
14
RDY
Column driver
RDY
Column driver
µPD16661A
★
7.2 Access timing
(1) Display data read timing
A16 to A0
/UBE
/CS
/OE
Hi-z
Hi-z
RDY
Hi-z
D15 to D0
Hi-z
Dout
(2) Display data write timing
A16 to A0
/UBE
/CS
/WE
Hi-z
Hi-z
RDY
D15 to D0
Din
15
µPD16661A
8. GRAY SCALE CONTROL
The four gray scales are expressed in terms of 3 thinning-out frames.
The thinning-out method is changed by 9 pixels: pixel numbers 1, 2, and 3, and line numbers 1, 2, and 3 of the
liquid-crystal panel.
Frame thinning-out method
1
Gray Scale 0
2
3
1
Gray Scale 1
2
3
1
Gray Scale 2
2
3
1
Gray Scale 3
2
3
Line
16
Frame 1
Frame 2
Frame 3
1
1
1
2
3
2
3
2
3
Column
µPD16661A
9. LIQUID-CRYSTAL TIMING GENERATION
9.1 Reset state
In the reset state, the internal counter is zero-cleared.
After the reset is released, the display OFF function operates during the 4-frame cycle, even if the /DOFF pin is
at H.
/RESET
1
2
3
4
5
6
/FRM
/DOUT
Internal state
Display OFF
Display ON
9.2 Liquid-crystal timing generation circuit
When the master mode is set with MS = H, this circuit generates the signals /FRM and STB at a duty ratio timing
of 1/240. It also generates L1 and L2, which are the drive voltage selection signals for the row driver.
The /FRM signal is generated twice per frame. The STB signal is generated 121 times per half frame, or 242
times per frame.
Generation of /FRM & STB signals
OSC1
/FRM
STB
121
1
2
121
1
2
121
1
2
Frame
Generation of L1 and L2 signals
STB
1 2 3 4 ⋅⋅⋅
1 2 3 4 ⋅⋅⋅
1 2 3 4 ⋅⋅⋅
1 2 3 4 ⋅⋅⋅
L1
1 1 1 1 ⋅⋅⋅
1 1 1 1 ⋅⋅⋅
0 0 0 0 ⋅⋅⋅
0 0 0 0 ⋅⋅⋅
L2
1 0 1 0 ⋅⋅⋅
0 1 0 1 ⋅⋅⋅
0 1 0 1 ⋅⋅⋅
1 0 1 0 ⋅⋅⋅
17
µPD16661A
10. SELF-DIAGNOSIS FUNCTION
This is a function to check whether or not there has been a delay in the operation timing of each column driver
caused by external noise, etc. The slave chip compares the L1 and L2 signals of the master chip with the L1 and
L2 signals generated internally, and if a mismatch is discovered, the slave chip sends a refresh signal to all the
column drivers. When the refresh signal is received, the internal reset is activated, and the timing is initialized. At
this time, the display turns OFF while /REFRH = L and during the four frame cycle.
The L1 and L2 signals are checked for mismatch at the rising edge of /FRM once every half frame.
L1(Master)
Mismatch
L2 (Master)
L1 (Slave)
Mismatch
L2 (Slave)
/REFRH
Initialized
Initialized
Block configuration diagram (Slave side)
/RESET
Internal reset
/REFRH
Self-diagnosis circuit
18
L1
Internal L1 signal
L2
Internal L2 signal
µPD16661A
11. SYSTEM CONFIGURATION EXAMPLE
This is an example of the configuration of a liquid-crystal panel of half VGA size (480 × 320, perpendicular) using
four µPD16661A devices and two row drivers.
• Each column driver sets the LSI No. with the PL0, PL1, and PL2 pins.
• The DIR pin of each column driver is set to low.
• One of the column drivers only is set to master; all the others are set to slave. Signals are supplied from the
master column driver to the slave column drivers and the row drivers.
• The OSC1 and OSC2 pins have an oscillator resistor attached on the master, and are left open on the slaves.
• All the signals from the system side (D0 to D15, A0 to A16, /CS, /OE, /WE, /UBE, RDY, /RESET, /DOFF) are
connected in parallel to the column driver. A pull-up resistor is attached to the RDY signal.
• The TEST pin is used to test the LSI, and is left open or connected to the GND when the system is configured.
VCC2
RDY
/DOFF
/RESET
D0 to D15
A0 to A16
Control
( /CS, /OE,
/WE, /UBE)
STB
/FRM
/DOUT,/DOFF'
L1
L2
OSC1
Master
No.0
Slave
No.2
OSC2
/REFRH
Y1
Y160 Y1
Y160
Scan direction
Row
driver
240
Scan direction
Row
driver
240
Y160
Y1 Y160
Slave
No.1
Y1
Slave
No.3
Remark /DOFF’ is an input pin of row driver.
19
µPD16661A
★ 12. CHIP SET POWER SUPPLY INPUT SEQUENCE
It is recommended that the power supply be input in the following way.
VCC2 → VCC1 → input → VDD, VEE → V1, V2
Make sure that the LCD drive voltages are input last.
ON
VCC2
VCC1
OFF
OFF
Note1
CPU Interface
(A0 to A16, /CS, /OE,
/WE, /UBE,D0 to D15,
/DOFF)
/RESET
At least 0 s
ON
4.5 V
3.3 V
0V
3.3 V
0V
0.3 VCC2
At least 0 s
At least 100 ns
ON
Note2
VDD
OFF
OFF
Note2
ON
VEE
V1
At least 0 s
ON
OFF
ON
V2
OFF
Notes 1. Inputting the selection pins (PL0, PL1, PL2, DIR, MS, BMODE) at the same time as the VCC2 pin
is unproblematic.
2. It is not necessary to turn ON VDD and VEE at the same time.
VDD and VEE are the liquid-crystal power supplies of the row driver.
Caution Disconnection of the chip set power supply is done in the reverse order of the input
sequence.
20
µPD16661A
13. EXAMPLE OF THE CONFIGURATION OF THE MODULE − INTERNAL SCHOTTKY BARRIER
DIODE FOR POWER SUPPLY PROTECTION REINFORCEMENT
Note
VDD
VCC1
V2
V1
V0
VSS
Note
VEE
Configure the diodes that are enclosed in the dotted lines when V0 is not 0 V (GND).
★
Note VDD and VEE are the liquid-crystal power supplies of the row driver.
Remark Use the Schottky Barrier Diode at Vf = 0.5 V or less.
21
µPD16661A
14. ELECTRICAL CHARACTERISTICS
Absolute maximum ratings (TA = +25 °C)
Parameter
Symbol
Ratings
Unit
Remark
Supply voltage (1)
VCC1
−0.5 to +6.5
V
Note1
Supply voltage (2)
VCC2
−0.5 to +4.5
V
Note2
Input /Output voltage (1)
VI/O1
−0.5 to VCC1 + 0.5
V
Note1
Input /Output voltage (2)
VI/O2
−0.5 to VCC2 + 0.5
V
Note2
Input/ Output voltage (3)
VI/O3
−0.5 to VCC1 + 0.5
V
Note3,
Note4
Operating ambient temperature
TA
−20 to +70
°C
Storage temperature
Tstg
−40 to +125
°C
Notes1. 5-V signals (/FRM, STB, /DOUT, L1, L2)
2. 3.3-V signals (MS, DIR, PL0 to PL2, A0 to A16, /CS, /OE, /WE, /UBE, RDY, D0 to D15, /RESET, OSC1,
OSC2, /DOFF, TEST, GMODE, BMODE, /REFRH)
3. Liquid-crystal drive power supplies (V0, V1, V2, Y1 to Y160)
4. Set V0 < V1 < V2
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Recommended operating range (TA = −20 to +70 °C, V0 = 0 V)
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
Supply voltage (1)
VCC1
4.5
5.0
5.5
V
Supply voltage (2)
VCC2
3.0
3.3
3.6
V
Input voltage (1)
VI1
0
VCC1
V
Note1
Input voltage (2)
VI2
0
VCC2
V
Note2
V1 input voltage
V1
V0
V2
V
V2 input voltage
V2
V1
VCC1
V
ROSC
300
700
kΩ
OSC external resistor
Remark
Notes1. 5-V signals (/FRM, STB)
2. 3.3-V signals (MS, DIR, PL0 to PL2, A0 to A16, /CS, /OE, /WE, /UBE, RDY, D0 toD15, /RESET, OSC1,
OSC2, /DOFF, TEST, GMODE, BMODE, /REFRH)
22
µPD16661A
DC Characteristics
(Unless otherwise specified, VCC1 = 4.5 to 5.5 V, VCC2 = 3.0 to 3.6 V, V0 = 0 V, V1 = 1.4 to 2.0 V,
V2 = 2.8 to 4.0 V, TA = −20 to +70 °C)
Parameter
High-level input voltage (1) VCC1
Symbol
MIN.
VIH1
0.7 VCC1
Low-level input voltage (1) VCC1
VIL1
High-level input voltage (2) VCC2
VIH2
Low-level input voltage (2) VCC2
VIL2
High-level input voltage (2) VCC2
VIH3
Low-level input voltage (2) VCC2
VIL3
High-level output voltage (1) VCC1
VOH1
Low-level output voltage (1) VCC1
VOL1
TYP.
MAX.
0.3 VCC1
0.7 VCC2
0.3 VCC2
0.8 VCC2
0.2 VCC2
VCC1 −
0.4
0.4
Unit
Remark
V
Note1
V
Note1
V
Note2
V
Note2
V
Note4
V
Note4
V
IOH = −1 mA,
Note3
V
IOL = 2 mA,
Note3
High-level output voltage (2) VCC1
VOH2
Low-level output voltage (2) VCC1
VOL2
High-level output voltage (3) VCC2
VOH3
Low-level output voltage (3) VCC2
VOL3
VCC1 −
0.4
0.4
VCC2 −
0.4
0.4
V
IOH = −2 mA,
Note1
V
IOL = 4 mA,
Note1
V
IOH = −1 mA,
Note4
V
IOL = 2 mA,
Note4
Input leakage current (1)
II1
Input leakage current (2)
II2
10
40
±10
µA
Other than
TEST pin,
VI = VCC2 or
GND
100
µA
Pull-down
(TEST pin),
VI = VCC2
Current consumption for display operation (1)
IMAS1
40
µA
Master,
VCC1, Note5
Current consumption for display operation (2)
IMAS2
150
µA
Master,
VCC2, Note5
Current consumption for display operation (3)
ISLV1
30
µA
Slave,
VCC1, Note5
Current consumption for display operation (4)
ISLV2
Liquid-crystal driving output ON resistance
RON
100
µA
2
kΩ
Slave,
VCC2, Note5
1
Note6
Notes 1. 5-V signals (/FRM, STB,L1,L2)
2. 3.3-V signals (MS, DIR, PL0 to PL2, A0 to A16, /CS, /OE, /WE, /UBE, RDY, D0 to D15, /RESET, /DOFF,
TEST, GMODE, BMODE)
3. /DOUT pin
4. D0 to D15, RDY, and OSC2 pins
5. When the frame frequency is 70 Hz, and the output and CPU are without load and access respectively.
(D0 to D15, A0 to A16, and /UBE = GND, and /CS, /OE, and /WE = VCC2)
6. This is the resistance value between a Y pin and a V pin (V0, V1, or V2) when the load current
(ION = 100 µA) is passed to a pin of Y1 to Y160.
23
µPD16661A
AC Characteristics 1 Display data transfer timing
Master mode
(Unless otherwise specified, VCC1 = 4.5 to 5.5 V, VCC2 = 3.0 to 3.6 V, V0 = 0 V, V1 = 1.4 to 2.0 V,
V2 = 2.8 to 4.0 V, TA = −20 to +70 °C, Frame frequency : 70 Hz (fOSC = 33.88 kHz), Output load : 100 pF)
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
STB Clock cycle time
tCYC
58
2/fOSC
µs
STB High-level width
tCWH
28
1/fOSC
µs
STB Low-level width
tCWL
28
1/fOSC
µs
STB Rise time
tR
100
ns
STB Fall time
tF
100
ns
STB - /FRM Delay time
tPSF
12
µs
/FRM - STB Delay time
tPFS
12
µs
tCYC
tCWL
tCWH
tR
tF
0.9 VCC1
STB (Output)
0.1 VCC1
tPSF
tPFS
tPSF
tPFS
0.9 VCC1
/FRM (Output)
24
0.1 VCC1
Remark
µPD16661A
Slave mode
(Unless otherwise specified, VCC1 = 4.5 to 5.5 V, VCC2 = 3.0 to 3.6 V, V0 = 0 V, V1 = 1.4 to 2.0 V,
V2 = 2.8 to 4.0 V, TA = −20 to +70 °C)
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
STB Clock cycle time
tCYC
10
µs
STB High-level width
tCWH
4
µs
STB Low-level width
tCWL
4
µs
STB Rise time
tR
150
ns
STB Fall time
tF
150
ns
/FRM Setup time
tSFR
1
µs
/FRM Hold time
tHFR
1
µs
Remark
tCYC
tCWL
tCWH
tF
tR
0.7 VCC1
STB (Input)
0.3 VCC1
tSFR
tHFR
tSFR
tHFR
0.7 VCC1
/FRM (Input)
0.3 VCC1
25
µPD16661A
Master/Slave common items
(Unless otherwise specified, VCC1 = 4.5 to 5.5 V, VCC2 = 3.0 to 3.6 V, V0 = 0 V, V1 = 1.4 to 2.0 V,
V2 = 2.8 to 4.0 V, TA = −20 to +70 °C)
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
Remark
Output delay time (L1, L2, /DOUT)
tDOUT1
50
100
ns
Output without load
Output delay time (Y1 to Y160)
tDOUT2
90
150
ns
Output without load
STB (Output)
0.9 VCC1
tDOUT1
tDOUT1
L1, L2,
/DOUT
0.9 VCC1
tDOUT2
tDOUT2
0.9 V2
0.1 V2
Y1 to Y160
0.9 V2
0.1 V2
26
µPD16661A
AC Characteristics 2 Graphic access timing
(Unless otherwise specified, VCC1 = 4.5 to 5.5 V, VCC2 = 3.0 to 3.6 V, V0 = 0 V, V1 = 1.4 to 2.0 V,
V2 = 2.8 to 4.0 V, TA = −20 to +70 °C, tr = tf = 5 ns, frame frequency : 70 Hz (fOSC = 33.88 kHz))
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
Remark
/OE,/WE Recovery time
tRY
30
ns
Address setup time
tAS
10
ns
Address hold time
tAH
20
ns
RDY Output delay time
tRYR
30
ns
CL = 15 pF
★
RDY Float time
tRYZ
30
ns
Note3
★
Wait state time
tRYW
35
ns
Note1
Ready state time (Without Contention)
tRYF1
60
100
ns
Note1
Ready state time (With Contention)
tRYF2
650
1200
ns
Note1
Data access time (Read cycle)
tACS
100
ns
Note2
Data float time (Read cycle)
tHZ
40
ns
Note3
/CS-/OE Time (Read cycle)
tCSOE
10
ns
/OE-/CS Time (Read cycle)
tOECS
20
ns
Write pulse width (Write cycle)
tWP
50
ns
Data setup time (Write cycle)
tDW
20
ns
Data hold time (Write cycle)
tDH
20
ns
/CS-/WE Time (Write cycle)
tCSWE
10
ns
/WE-/CS Time (Write cycle)
tWECS
20
ns
Reset pulse width
tWRES
100
ns
RDY-/OE Time
tRDOE
Note4
—
RDY-/WE Time
tRDWE
Note4
—
Note1
Notes 1. Load circuit
VCC2
1.8 kΩ
1.0 kΩ
2.
60 pF
Load circuit
VCC2
1.8 kΩ
1.0 kΩ
100 pF
27
µPD16661A
★
3. Load circuit
VCC2
1.8 kΩ
1.0 kΩ
5 pF
4. The display may be affected if there is a long time from the rise of RDY to the /OE or /WE signals.
It is recommended that tRDOE and tRDWE are 1000 ns or less.
28
µPD16661A
/OE,/WE Recovery time
tRY
0.7 VCC2
/OE,/WE
★
0.3 VCC2
Read cycle
0.7 VCC2
A16 to A0
/UBE
0.3 VCC2
tAS
/CS
tAH
0.3 VCC2
tCSOE
tRDOE
tOECS
0.7 VCC2
/OE
0.3 VCC2
tRYR
RDY
tRYW
tRYZ
0.1 VCC2
Hi-z
D15 to D0
tRYF
tACS
tHZ
Output
0.1 VCC2
0.9 VCC2
0.1 VCC2
29
µPD16661A
★ Write cycle
0.7 VCC2
A16 to A0
/UBE
0.3 VCC2
tAH
tAS
/CS
0.3 VCC2
tCSWE
tRDWE
tWECS
0.7 VCC2
/WE
0.3 VCC2
tRYF
tRYR
tRYW
tRYZ
0.1 VCC2
RDY
0.1 VCC2
tWP
Hi-z
0.7 VCC2
Input
D15 to D0
0.3 VCC2
tDW
★ Reset pulse width
/RESET
0.3 VCC2
tWRES
30
tDH
µPD16661A
AC Characteristics 3 CR Oscillator
(VCC2 = 3.0 to 3.6 V, TA = −20 to +70 °C)
Parameter
Oscillation Frequency
Frame Frequency
Symbol
MIN.
TYP.
MAX.
Unit
Remark
fOSC
32
36
40
kHz
External resistor 350 kΩ
66.1
74.4
82.6
Hz
External resistor 350 kΩ
15. RELATIONSHIP BETWEEN THE OSCILLATION , FRAME , AND STB FREQUENCIES
This relationship is as follows:
Frame frequency =
STB frequency =
1
× Oscillation frequency
242 × 2
1
× Oscillation frequency
2
31
D16661AN-051
1
JAPAN
P0.0815
φ1
Cu
Polyimide
MAX. 0.9
Flex resin
1.42±0.03
Copper
SR
2±0.01
0.12
(1)
(1)
44.86±0.08
18.5
18.5
(36) (Cut Line)
17.5±0.3 (SR)
17.5±0.3 (SR)
35 (Slit)
17 (Mark)
P0.2±0.01x165 = 33±0.05 W0.1±0.015
17 (Mark)
P0.1021
(6.3) (Cut Line)
6.8
Specification
Basefilm : UPILEX-S
75 µm
Adhesive : EPOXY
12 µm
COPPER FOIL : ELECTROLYSIS Cu
25 µm
Plating : Sn
MIN. 0.25 µm
Solder Resist : EPOXY
25 µm
FLEX RESIN : POLYIMIDE
COATING RESIN : EPOXY
2
0.2±0.2
0.2±0.2
4.75±0.03
2.375
1.2 (1.5)
4.2±0.2(SR)
1.075
5.625
0.8
10.2
(2.3)
(12.5) (Cut Line)
13
13.8
14.5
2.6±0.2
4
(0.4)
2.2
(0.5)
P0.0808
P0.1034
20.2
16.57
10±0.3 (SR)
10±0.3 (SR)
13 (Hole)
13 (Hole)
P0.45±0.01x73 = 32.85±0.045 W0.225±0.02
17±0.3 (SR)
17±0.3 (SR)
35
(coating area)
0
21.2 –4.6
1
D16661AN
-051
This product is face up type.
This product is singleflex resin type.
This flgure is shown by Copper side
over Polyimide.
Detail see another sheet.
5 Sprocket holes (23.75 mm) for 1 Pattern.
Corner radius is 0.30 mm Max.
All tolerances unless otherwise
specified 0.05 mm.
32
JAPAN
µPD16661A
★ 16. PACKAGE DRAWING
Standard TCP package drawing (µPD16661AN-051)
(coating area)
6.8 –4.6
0
13.8
10.2
Flex resin
µPD16661A
Test pad and alignment mark details (x20)
From P.C.
18.5
From P.C.
17
0.4±0.015
0.6±0.015
2±0.01
P0.2
R0.5
Cu Hole
0.4
φ 1.2
PI Hole
0.4±0.015
0.6±0.015
R0.8
Cu
0.3
0.2
0.3
0.2
0.3
0.2
(0.5)
φ1
Cu Hole
φ 1.6
Cu
10.2
13.8
(12.5)
0.2
R0.6
PI Hole
0.3
0.4
0.06
14.5
Alignment hole details (x20)
0.1±0.015
From P.C.
TCP tape winding direction
Output lead
Tape pull-out
direction
Wind-up direction
The Cu pattern side is
the underside of the tape.
33
µPD16661A
Standard TCP package drawing (µPD16661AN-051)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
34
NC
V0
V1
V2
VCC1
GND
VCC2
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
VCC2
OSC1
OSC2
GND
DIR
PL0
PL1
PL2
/REFRH
/RESET
/UBE
/CS
/OE
/WE
RDY
/DOFF
TEST
BMODE
GMODE
MS
VCC2
GND
/FRM
STB
/DOUT
L2
L1
VCC1
GND
V2
V1
V0
NC
DIE FACE UP
Pin connection diagram
NC
NC
NC
Y160
Y159
Y158
Y157
Y156
Y155
.
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Y5
Y4
Y3
Y2
Y1
NC
NC
NC
1
2
3
4
5
6
7
8
9
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159
160
161
162
163
164
165
166
µPD16661A
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material.
All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry.
Each unused pin should be connected to V DD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
35
µPD16661A
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC’s Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96. 5