DATA SHEET MOS INTEGRATED CIRCUIT µPD16667 160-OUTPUT LCD ROW DRIVER The µPD16667 is a row (common) driver which contains a RAM capable of full-dot LCD display. With 160 outputs, this driver can be combined with a column (segment) driver, µPD16662, which contains a RAM to display 240 × 160 pixels to 480 × 320 pixels. With a built-in display RAM, the column driver can reduce the current consumption, thus making it most suitable for the display block of a PDA or portable terminal. FEATURES • LCD-driven voltage: 20 to 36 V • Duty: 1/160 • Driving type: 2 lines selected simultaneously • Output count: 160 outputs • Capable of gray scale display: 4 gray scales ORDERING INFORMATION Part No. Package µPD16667N-XXX TCP (TAB) µPD16667N-051 Standard TCP (OLB: 0.2 mm pitch, folding) The external shape of the TCP is custom-made, so please contact an NEC sales representative with your shape requirements. Document No. S12838EJ4V0DS00 (4th edition) Date Published January 1999 N CP(K) Printed in Japan The mark shows major revised points. µPD16667 BLOCK DIAGRAM X1 to X160 VDD V1 Liquid-crystal drive circuit VEE Selection control circuit Q1 to Q80 Bidirectional shift register DIR VCC1 Level shifter L1 L2 /DOFF’ STB VSS /FRM Column driver interface Remark /xxx indicates active low signal. BLOCK FUNCTION 1. Liquid-crystal drive circuit This circuit selects and outputs the level for liquid-crystal driving. One of VDD, VEE, and V1 is selected by the output of the selection control circuit. 2. Selection control circuit This circuit creates the signal which will select the level of the output signal, based on the output of the shift register circuit and the driving level power selection signals L1 and L2 3. Bidirectional shift register circuit This refers to the 80-bit bidirectional shift register circuit. The DIR signal can be used to switch over the shift direction. The data that has been entered from the /FRM pin is shifted by the low drive signal strobe (STB). 4. Level shifter circuit This circuit transforms the 5-V signals to the high-voltage signals for liquid-crystal driving. 2 µPD16667 PIN FUNCTIONS Classification Pin Name Input/Output Pad No. Function Power suuply VCC1 VSS VDD VEE V1 5 V power for level shifter GND for level shifter Power for logic, liquid-crystal drive level power Power for logic, liquid-crystal drive level power (GND) Liquid-crystal drive level power Liquid-crystal display timing STB /FRM /DOFF’ L1 L2 DIR I I I I I I Row drive signal strobe Frame signal Display OFF signal Drive level power selection symbol (1st line) Drive level power selection symbol (2nd line) Shift direction selection symbol:when L (DIR = VEE), X1 → X160 when H (DIR = VDD), X160 → X1 Liquid-crystal drive output X1 to X160 O Liquid-crystal drive output Selects and outputs one of VDD, VEE, and V1. DETAILS OF PIN FUNCTIONS • STB (input) Input pin of the row drive strobe signal The bidirectional shift register is shifted at STB’s rising edge. • /FRM (input) Input pin of the frame signal The shift register data is read at STB’s rising edge. • DIR (input) Input pin of the drive output’s shift direction selection signal When the shift direction selection signal (DIR) is “L”, the shift data (selection signal) is shifted from the drive output X1 to the X160 direction. When “H”, it is shifted from the X160 to the X1 direction. • /DOFF’ (input) Input pin of the display OFF signal It is placed in the display OFF status (all outputs at V1) at the “L” level. In the mean time, it reads the frame signal and returns to the normal display status at the “H” level. • L1 and L2 (input) Input pins of the drive level power selection signal In the case of the liquid-crystal drive output, the two lines are selected simultaneously by the shift register. L1 selects the first line, and L2 selects the second line. Both lines select VDD at “H”, and VEE at “L”. 3 µPD16667 SYSTEM CONFIGURATION EXAMPLE This example shows configuration of a liquid-crystal panel of half-VGA size (480 x 320 oblong) using four column drivers and two row drivers. • • • • • • Each column driver sets the LSI No. with PL0 and PL1 pins. The DIR pins of each column driver are all set to low level. Only one of the column drivers is set to the master, all the others are set to the slave. Signals are supplied from the master column driver to the slave column driver and the row driver. Connect an oscillator resistor to the OSC1 and OSC2 pins of the master, and leave the slave open. Inputs signals from the system (D0 to D15, A0 to A16, /CS, /OE, /WE, /UBE, RDY, /RESET, /DOFF’) in parallel to all of the column driver. Connect a pull-up resistor to the RDY signal. The TEST pin is used to test the LSI, and is open or GND when the system is configured. VCC2 RDY /DOFF /RESET D0 to D15 A0 to A16 Control (/CS, /OE, /WE, /UBE) PULSE STB /FRM /DOUT, /DOFF’ L1 L2 OSC1 Slave No. 2 Master No. 0 /REFRH OSC2 Y240 Scan direction 160 Y240 Y1 Scan direction Row driver 160 Row driver Y1 Y240 Slave No. 1 Y1 Y240 Y1 Slave No. 3 Remark The /DOUT pin is an output pin for the column driver. 4 µPD16667 POWER SUPPLY SEQUENCE OF CHIP SET It is recommended to apply power in the following sequence. VCC2 → VCC1 → input → VDD, VEE → V1, V2 Be sure to apply LCD drive voltages V1 and V2 last. ON VCC2 Note 1 OFF ON VCC1 CPU I/F 0 s or more Note 1 (A0 to A16, /CS, /OE, /WE, /UBE, D0 to D15, /DOFF) 4.5 V OFF 3.3 V 0V 3.3 V /RESET Note 1 0V 0.3 VCC2 100 ns or more VDDNote 2 0 s or more ON OFF OFF VEENote 2 V1 ON OFF 0 ns or more ON ON V2 Note 1 OFF Notes 1. VCC2, CPU I/F, /RESET, and V2 are column driver power supply pins or input pins. 2. VDD and VEE do not need to be turned ON at the same time. Caution Turn off the power to the chip set in the reverse order of the power application sequence. 5 µPD16667 EXAMPLE OF CONNECTING INTERNAL SCHOTTKY BARRIER DIODE OF MODULE TO REINFORCE POWER SUPPLY PROTECTION (Use a schottky barrier diode with Vf = 0.5 V or less.) VDD VCC1 V2 Note V1 V0 Note VSS VEE Connect the diodes enclosed in the dotted line ( ) when V0 is not 0 V (GND) Note V0 and V2 are column driver liquid-crystal power supplies. 6 µPD16667 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25 °C, VSS = 0 V) Parameter Supply voltage Symbol Condition VCC1 VDD – VEE Unit V VCC1 ≤ VDD, VEE ≤ VSS 40 V1 Input voltage Ratings –0.5 to +6.5 VEE – 0.5 to VDD + 0.5 VI1 Other than the DIR pin VI2 DIR pin –0.5 to VCC1 + 0.5 VEE – 0.5 to VDD + 0.5 Output voltage VO VEE – 0.5 to VDD + 0.5 Operating temperature TA –20 to +70 Storage temperature Tstg –40 to +125 °C Recommended Operating Range (TA = −20 to +70 °C, VSS = 0 V) Parameter Supply voltage Symbol Condition MIN. MAX. Unit V VCC1 4.75 5.25 VDD – V1 10 18 V1 – VEE 10 18 V1 Input voltage TYP. VI1 Other than DIR pin VI2 DIR pin 0 3 0 VCC1 VEE VDD DC Characteristics (unless otherwise specified, VCC1 = 4.75 to 5.25 V, VDD − (VEE) = 20 to 31 V, VCC1 ≤ VDD, VEE ≤ VSS, V1 = 0 to 3 V, VSS = 0 V, TA = − 20 to +70 °C) Parameter High-level input voltage Symbol Condition MIN. TYP. MAX. VIH1 Other than the DIR pin VIH2 DIR pin VIL1 Other than the DIR pin VIL2 DIR pin Driver ON resistance RON Load current = 100 µA 2.0 kΩ Input leakage current IIH1 VIN = VCC, other than the DIR pin 1.0 µA IIH2 VIN = VDD, DIR pin 25 IIL1 VIN = 0 V, other than the DIR pin IIL2 VIN = VEE, DIR pin ICC1 Operating frame frequency at 70 Hz Low-level input voltage Current consumption IDD 0.8 VCC1 Unit V VDD − 0.3 (VDD – VEE) 0.2 VCC1 VEE + 0.3 (VDD – VEE) 1.0 –1.0 –25 200 320 40 100 µA 7 µPD16667 AC Characteristics Parameter Symbol MIN. TYP. MAX. twsh 500 STB low-level width twsl 500 /FRM setup time tsf 100 /FRM hold time thf 100 STB rising time tr 150 STB falling time tf 150 tpdsx tpdout Output no-load Unit ns STB high-level width Output delay time 8 Condition 300 200 µPD16667 AC CHARACTERISTICS WAVEFORM DIAGRAMS tr tf VCC1 0.9 VCC1 0.5 VCC1 STB VSS 0.1 VCC1 twsh twsl tsf thf VCC1 0.5 VCC1 /FRM VSS VCC1 0.5 VCC1 /DOFF’ VSS tpdsx tpdsx VDD VDD to V1 50 % Xn V1 VEE to V1 50 % tpdout VEE tpdsx tpdsx VDD VDD to V1 50 % Xn + 2 V1 VEE to V1 50 % VEE tpdout 9 µPD16667 LEVEL SELECTION TIMING OF LIQUID-CRYSTAL DRIVE OUTPUT The /FRM is input twice in one frame. The STB is input 81 times in half a frame, and 162 times in one frame. VDD DIR VEE VCC1 /FRM VSS VCC1 STB VSS 81 1 2 80 81 1 2 80 81 1 2 80 81 1 2 80 81 1 frame T1 T2 T3 T4 VCC1 L1 VSS VCC1 L2 VSS VDD X1 V1 VEE X2 X3 X4 X160 (When DIR is “H”) VDD DIR VEE VDD X160 V1 VEE X159 X158 X157 X1 10 Remark When /DOFF’ is “L”, the X output becomes V1 level. Afterward, if /DOFF’ becomes “H”, the level of the X output is output with the above timing. Caution When the time difference between the STB, L1, and L2 signals is large, hazards may occur in output. STANDARD TCP PACKAGE (µPD16667N-051) 11 µPD16667 µPD16667 Detail of cross mark 0.6±0.05 0.05±0.02 0.3±0.05 0.05±0.02 TCP tape winding direction Output leads Winding direction Unwinding direction CU pattern is on the backside of the tape 12 µPD16667 PIN CONFIGURATION NC NC NC NC Y1 Y2 Y3 VEE Y4 Y5 • • • V1 VDD VEE • • • VSS • • • • VCC1 VDD /FRM /DOUT L1 L2 STB DIR µ PD16667N -051 • • • • • • • • • • • • VEE • • VDD Y156 Y157 Y158 V1 VEE NC Y159 Y160 NC NC NC 13 µPD16667 [MEMO] 14 µPD16667 [MEMO] 15 µPD16667 No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96. 5