PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD4483362 8M-BIT CMOS SYNCHRONOUS FAST STATIC RAM 256K-WORD BY 36-BIT HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE Description The µPD4483362 is a 262,144 words by 36 bits synchronous static RAM fabricated with advanced CMOS technology using Full-CMOS six-transistor memory cell. The µPD4483362 is suitable for applications which require synchronous operation, high-speed, low voltage, highdensity memory and wide bit configuration, such as cache and buffer memory. The µPD4483362 is packaged in 100-pin PLASTIC LQFP with a 1.4 mm package thickness for high density and low capacitive loading. Features • Fully synchronous operation • HSTL Input / Output levels • Fast clock access time : 3.8 ns (133 MHz) • Asynchronous output enable control : /G • Byte write control : /SBa (DQa1-9), /SBb (DQb1-9), /SBc (DQc1-9), /SBd (DQd1-9) • Common I/O using three-state outputs • Internally self-timed write cycle • Late write with 1 dead cycle between Read-Write • 3.3 V (Chip) / 1.5 V (I/O) supply • 100-pin PLASTIC LQFP package, 14 mm x 20 mm • Sleep Mode : ZZ (Enables sleep mode, active high) Ordering Information Part number µPD4483362GF-A75 Access time Clock frequency Package 3.8 ns 133 MHz 100-pin PLASTIC LQFP (14 x 20) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M14440EJ1V0DS00 (1st edition) Date Published April 2001 NS CP(K) Printed in Japan © 2001 µPD4483362 Pin Configuration (Marking Side) /xxx indicates active low signal. 100-pin PLASTIC LQFP (14 x 20) SA9 SA8 SA17 NC /SW /G VREF /K K VSS VDD NC /SBa NC /SBb /SBc /SBd /SS SA7 SA6 [ µPD4483362GF ] 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 DQc9 1 80 DQb9 DQc8 2 79 DQb8 DQc7 3 78 DQb7 VDDQ 4 77 VDDQ VSSQ 5 76 VSSQ DQc6 6 75 DQb6 DQc5 7 74 DQb5 DQc4 8 73 DQb4 DQc3 9 72 DQb3 VSSQ 10 71 VSSQ VDDQ 11 70 VDDQ DQc2 12 69 DQb2 DQc1 13 68 DQb1 NC 14 67 VSS VDD 15 66 NC NC 16 65 VDD VSS 17 64 ZZ DQd1 18 63 DQa1 DQd2 19 62 DQa2 VDDQ 20 61 VDDQ VSSQ 21 60 VSSQ DQd3 22 59 DQa3 DQd4 23 58 DQa4 DQd5 24 57 DQa5 DQd6 25 56 DQa6 VSSQ 26 55 VSSQ VDDQ 27 54 VDDQ DQd7 28 53 DQa7 DQd8 29 52 DQa8 DQd9 30 51 DQa9 Remark Refer to Package Drawing for 1-pin index mark. 2 Preliminary Data Sheet M14440EJ1V0DS SA16 SA15 SA14 SA13 SA12 SA11 VREF SA10 NC VDD VSS NC VREF SA0 SA1 SA2 SA3 SA4 NC SA5 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 µPD4483362 Pin Name and Functions Pin name SA0 to SA17 Pin No. Description 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, Synchronous Address Input 45, 46, 47, 48, 49, 50, 83 DQa1 to DQa9 63, 62, 59, 58, 57, 56, 53, 52, 51 DQb1 to DQb9 68, 69, 72, 73, 74, 75, 78, 79, 80 DQc1 to DQc9 13, 12, 9, 8, 7, 6, 3, 2, 1 DQd1 to DQd9 18, 19, 22, 23, 24, 25, 28, 29, 30 /SS 98 Synchronous Chip Select /SW 85 Synchronous Byte Write Enable /SBa Note1 93 Synchronous Byte "a" Write Enable /SBb Note1 95 Synchronous Byte "b" Write Enable /SBc Note1 96 Synchronous Byte "c" Write Enable /SBd Note1 97 Synchronous Byte "d" Write Enable 86 Asynchronous Output Enable 64 Asynchronous Sleep Mode K, /K 89, 88 Main Clock Input VDD 15, 41, 65, 91 Core Power Supply VSS 17, 40, 67, 90 Ground VDDQ 4, 11, 20, 27, 54, 61, 70, 77 Output Buffer Power Supply VSSQ 5, 10, 21, 26, 55, 60, 71, 76 Output Buffer Ground VREF 38, 43, 87 Input Reference NC 14, 16, 31, 39, 42, 66, 84, 92, 94 No Connection /G ZZ Note2 Synchronous Data Input / Output Notes 1. If Byte Write Operation is not used, Byte Write Pins (/SBa, /SBb, /SBc, /SBd) are to be tied to VSS. 2. If Sleep Mode is not used, ZZ Pin is to be tied to VSS. Remark This device only supports Single Differential Clock, R / R Mode. (R / R stands for Registered Input / Registered Output.) Preliminary Data Sheet M14440EJ1V0DS 3 µPD4483362 Late Write Block Diagram 18 SA0 to SA17 K Address register K /K Mux Write address register /K /SS /SS Write clock generator /SW /SW /SBa /SBa Write control logic /SBb /SBb /SBc /SBc /SBd /SBd DQa1 to DQa9 DQb1 to DQb9 DQc1 to DQc9 DQd1 to DQd9 4 Memory cell array 9,437,184 bits Read comp. Data Data in out Mux 36 Data in register /G /G ZZ ZZ Output Register Preliminary Data Sheet M14440EJ1V0DS µPD4483362 Synchronous Truth Table DQa1–9 DQb1–9 DQc1–9 DQd1–9 ZZ /SS /SW /SBa /SBb /SBc /SBd Mode Power L H × × × × × Not selected Hi-Z Hi-Z Hi-Z Hi-Z Active L L H × × × × Read Dout Dout Dout Dout Active L L L L L L L Write Din Din Din Din Active L L L L H H H Write Din Hi-Z Hi-Z Hi-Z Active L L L H L L L Write Hi-Z Din Din Din Active L L L H H H H Abort Write Hi-Z Hi-Z Hi-Z Hi-Z Active H × × × × × × Sleep Mode Hi-Z Hi-Z Hi-Z Hi-Z Standby Remark × : Don’t care Output Enable Truth Table Mode /G DQ Read L Dout Read H Hi-Z Sleep (ZZ=H) × Hi-Z Write (/SW=L) × Hi-Z, Din Deselect (/SS=H) × Hi-Z Remark × : Don’t care Preliminary Data Sheet M14440EJ1V0DS 5 µPD4483362 Electrical Specifications Absolute Maximum Ratings Parameter Symbol Supply voltage Condition MIN. TYP. MAX. Unit Note VDD –0.5 +4.0 V 1 VDDQ –0.5 +4.0 V 1 Input voltage VIN –0.5 VDD+0.3 V 1 Input / Output voltage VI/O –0.5 VDDQ+0.3 V 1 Operating temperature TA 0 50 °C Storage temperature Tstg –55 +125 °C Output supply voltage Note 1. –2.0 V MIN. (Pulse width : 2 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (TA = 0 to 50 °C) Parameter MIN. TYP. MAX. Unit VDD 3.135 3.3 3.465 V Output buffer supply voltage VDDQ 1.4 1.5 1.6 V Input reference voltage VREF 0.7 0.75 Core supply voltage Symbol Conditions 0.8 V Note VREF–0.1 V VDDQ+0.3 V MAX. Unit Low level input voltage VIL –0.3 High level input voltage VIH VREF+0.1 Note –0.8 V MIN. (Pulse width : 2 ns) Recommended AC Operating Conditions (TA = 0 to 50 °C) Parameter Symbol Conditions MIN. TYP. Input reference voltage VREF (RMS) –5% +5% V Low level input voltage VIL –0.3 VREF–0.2 V High level input voltage VIH VREF+0.2 VDDQ+0.3 V MAX. Unit Capacitance (TA = 25 °C, f = 1 MHz) Parameter Note Symbol Test conditions Input capacitance CIN VIN = 0 V 5.5 pF Input / Output capacitance CI/O VI/O = 0 V 7.0 pF Clock Input Capacitance Cclk Vclk = 0 V 6.0 pF Note These parameters are not 100% tested. 6 Preliminary Data Sheet M14440EJ1V0DS µPD4483362 DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input leakage current ILI VIN = 0 to VDD –5 +5 µA DQ leakage current ILO VI/O = 0 to VDDQ –5 +5 µA Operating supply current IDD VIN = VIH or VIL, /SS = VIL, ZZ = VIL, 350 mA 20 mA MAX. Unit Cycle = MAX., IDQ = 0 mA Sleep mode power supply current ISBZZ ZZ = VIH, All other inputs = VIH or VIL, Cycle = DC, IDQ = 0 mA Output Voltage on Push-Pull Output Buffer Mode Parameter Symbol Conditions MIN. TYP. Low level output voltage VOL IOL = +2 mA – 0.3 V High level output voltage VOH IOH = –2 mA VDDQ–0.3 – V Preliminary Data Sheet M14440EJ1V0DS 7 µPD4483362 AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Characteristics Test Conditions Input waveform (rise and fall time = 0.5 ns (20 to 80%)) 1.25 V VDDQ / 2 Test Points VDDQ / 2 VDDQ / 2 Test Points VDDQ / 2 0.25 V Output waveform 8 Preliminary Data Sheet M14440EJ1V0DS µPD4483362 Single Differential Clock, Registered Input / Registered Output Mode Parameter Symbol –A75 (133 MHz) MIN. MAX. Unit Clock cycle time tKHKH 7.5 – ns Clock phase time tKHKL / 2.0 – ns 1.5 – ns 0.5 – ns Notes tKLKH Setup times Hold times Address tAVKH Write data tDVKH Write enable tWVKH Chip select tSVKH Address tKHAX Write data tKHDX Write enable tKHWX Chip select tKHSX Clock access time tKHQV – 3.8 ns 1 K high to Q change tKHQX 1.5 – ns 2 /G low to Q valid tGLQV – 3.8 ns 1 /G low to Q change tGLQX 0 – ns 2 /G high to Q Hi-Z tGHQZ 0 3.8 ns 2 K high to Q Hi-Z (/SW) tKHQZ 1.5 3.8 ns 2 K high to Q Hi-Z (/SS) tKHQZ2 1.5 3.8 ns 2 K high to Q Lo-Z tKHQX2 1.5 – ns 2 Sleep Mode Recovery tZZR – 7.5 ns Sleep Mode Enable tZZE – 7.5 ns Notes 1. See figure. (VTT = 0.75 V) VTT 50 Ω ZO = 50 Ω DQ (Output) 20 pF 2. See figure. (VTT = 0.75 V) VTT 50 Ω DQ (Output) 5 pF Preliminary Data Sheet M14440EJ1V0DS 9 10 Preliminary Data Sheet M14440EJ1V0DS DQ /G /SW /SS Address K /K Read Operation a tWVKH tSVKH tAVKH tKHWX tKHSX b tKHAX Qa tKHQV tKHQX c tKHKH Qb d Qc e tGHQZ tKHKL f Qe tGLQV tGLQX tKLKH g Qf h Qg tKHQZ2 i tKHQX2 j Qi k µPD4483362 Preliminary Data Sheet M14440EJ1V0DS DQ /G /SBx /SW /SS Address K /K Write Operation l tWVKH tSVKH tAVKH tKHWX tKHSX m tKHAX Ql tWVKH tGHQZ tKHWX n tDVKH tKHKH Dn o tKHDX p tGLQV tGLQX tKHKL Qo q Qp tKLKH r Qq tKHQZ s Ds t u tKHQX2 Qt v µPD4483362 11 12 Preliminary Data Sheet M14440EJ1V0DS DQ /ZZ /SW /SS Address K /K Sleep Mode a b Qa c Qb d Qc tZZE e f g h i tZZR j k Qj l µPD4483362 µPD4483362 Package Drawing 100-PIN PLASTIC LQFP (14x20) A B 80 81 51 50 detail of lead end S C D R Q 31 30 100 1 F G H I J M K P S N S L M NOTE ITEM Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 22.0±0.2 B 20.0±0.2 C 14.0±0.2 D 16.0±0.2 F 0.825 G 0.575 H 0.32 +0.08 −0.07 I J 0.13 0.65 (T.P.) K 1.0±0.2 L 0.5±0.2 M 0.17 +0.06 −0.05 N 0.10 P 1.4 Q 0.125±0.075 R 3° +7° −3° S 1.7 MAX. S100GF-65-8ET-1 Preliminary Data Sheet M14440EJ1V0DS 13 µPD4483362 Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µPD4483362. Type of Surface Mount Device µPD4483362GF: 100-pin PLASTIC LQFP (14 x 20) 14 Preliminary Data Sheet M14440EJ1V0DS µPD4483362 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Preliminary Data Sheet M14440EJ1V0DS 15 µPD4483362 • The information in this document is current as of April, 2001. The information is subject to change without notice. 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