ETC UPD434001ALG5-A20-7JD

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD434001AL
4M-BIT CMOS FAST SRAM
4M-WORD BY 1-BIT
Description
The µPD434001AL is a high speed, low power, 4,194,304 bits (4,194,304 words by 1 bit) CMOS static RAM.
Operating supply voltage is 3.3 V ± 0.3 V.
The µPD434001AL is packaged in 32-pin plastic SOJ and 32-pin plastic TSOP (II).
Features
• 4,194,304 words by 1 bit organization
• Fast access time : 15, 17, 20 ns (MAX.)
• Output Enable input for easy application
• Single +3.3 V power supply
Ordering Information
Part number
Package
Access time
Supply current mA (MAX.)
ns (MAX.)
At operating
At standby
5
µPD434001ALLE-A15
32-pin plastic SOJ
15
130
µPD434001ALLE-A17
(10.16 mm (400))
17
120
20
110
µPD434001ALLE-A20
µPD434001ALG5-A15-7JD
32-pin plastic TSOP (II)
15
130
µPD434001ALG5-A17-7JD
(10.16 mm (400))
17
120
µPD434001ALG5-A20-7JD
(Normal bent)
20
110
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M12223EJ5V0DS00 (5th edition)
Date Published May 2000 NS CP(K)
Printed in Japan
The mark • shows major revised points.
©
1996
µPD434001AL
•
Pin Configuration (Marking Side)
/xxx indicates active low signal.
32-pin plastic SOJ (10.16 mm (400))
[ µPD434001ALLE ]
32-pin plastic TSOP (II) (10.16 mm (400)) (Normal bent)
[ µPD434001ALG5-7JD ]
A0
1
32
A21
A1
2
31
A20
A2
3
30
A19
A3
4
29
A18
A4
5
28
A17
A5
6
27
A16
/CS
7
26
/OE
VCC
8
25
GND
GND
9
24
VCC
DIN
10
23
DOUT
/WE
11
22
A15
A6
12
21
A14
A7
13
20
A13
A8
14
19
A12
A9
15
18
A11
A10
16
17
NC
A0 - A21 : Address Inputs
DIN
: Data Input
DOUT
: Data Output
/CS
: Chip Select
/WE
: Write Enable
/OE
: Output Enable
VCC
: Power supply
GND
: Ground
NC
: No connection
Remark Refer to Package Drawings for the 1-pin index mark.
2
Data Sheet M12223EJ5V0DS00
µPD434001AL
A0
|
A21
DIN
Row decoder
Address buffer
Block Diagram
Memory cell array
4,194,304 bits
Input data
controller
Sense amplifier /
Switching circuit
Output data
controller
Column decoder
DOUT
Address buffer
/CS
/OE
/WE
VCC
GND
Truth Table
/CS
/OE
/WE
Mode
I/O
Supply current
H
×
×
Not selected
High impedance
ISB
L
L
H
Read
DOUT
ICC
L
×
L
Write
DIN
L
H
H
Output disable
High impedance
Remark × : Don’t care
Data Sheet M12223EJ5V0DS00
3
µPD434001AL
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
Supply voltage
Condition
Rating
VCC
Unit
–0.5
Note
to +4.6
V
–0.5
Note
to +4.6
V
Input / Output voltage
VT
Operating ambient temperature
TA
0 to 70
°C
Storage temperature
Tstg
–55 to +125
°C
Note –2.0 V (MIN.) (pulse width : 2 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
3.3
3.6
V
Supply voltage
VCC
3.0
High level input voltage
VIH
2.2
VCC+0.3
V
Low level input voltage
VIL
–0.3 Note
+0.8
V
Operating ambient temperature
TA
0
70
°C
Note –2.0 V (MIN.) (pulse width : 2 ns)
4
Data Sheet M12223EJ5V0DS00
µPD434001AL
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Input leakage current
ILI
VIN = 0 V to VCC
–2
+2
µA
Output leakage current
ILO
VOUT = 0 V to VCC,
–2
+2
µA
mA
/CS = VIH or /OE = VIH or /WE = VIL
Operating supply current
Standby supply current
ICC
/CS = VIL,
Cycle time : 15 ns
130
IOUT = 0 mA,
Cycle time : 17 ns
120
Minimum cycle time
Cycle time : 20 ns
110
ISB
/CS = VIH, VIN = VIH or VIL
50
ISB1
/CS ≥ VCC – 0.2 V,
5
mA
VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V
High level output voltage
VOH
IOH = –4.0 mA
Low level output voltage
VOL
IOL = +8.0 mA
2.4
V
0.4
V
MAX.
Unit
VIN = 0 V
6
pF
VOUT = 0 V
10
pF
Remarks 1. VIN : Input voltage
VOUT : Output voltage
2. These DC characteristics are in common regardless of package types.
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Input capacitance
Output capacitance
Symbol
CIN
COUT
Test condition
MIN.
TYP.
Remarks 1. VIN : Input voltage
VOUT : Output voltage
2. These parameters are periodically sampled and not 100% tested.
Data Sheet M12223EJ5V0DS00
5
µPD434001AL
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
Input Waveform (Rise and Fall Time ≤ 3 ns)
3.0 V
1.5 V
Test Points
1.5 V
1.5 V
Test Points
1.5 V
GND
Output Waveform
Output Load
AC characteristics directed with the note should be measured with the output load shown in Figure 1 or
Figure 2.
Figure 1
Figure 2
(for tAA, tACS, tOE, tOH)
(for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, tOW )
VTT = +1.5 V
+3.3 V
50 Ω
317 Ω
ZO = 50 Ω
DOUT (Output)
DOUT (Output)
30 pF
CL
Remark
6
351 Ω
CL includes capacitances of the probe and jig, and stray capacitances.
Data Sheet M12223EJ5V0DS00
5 pF
CL
µPD434001AL
Read Cycle
Parameter
µPD434001AL-A15 µPD434001AL-A17 µPD434001AL-A20
Symbol
MIN.
MAX.
15
MIN.
MAX.
17
MIN.
Unit
Notes
MAX.
Read cycle time
tRC
20
ns
Address access time
tAA
15
17
20
ns
/CS access time
tACS
15
17
20
ns
/OE access time
tOE
7
8
10
ns
Output hold from address change
tOH
3
3
3
ns
/CS to output in low impedance
tCLZ
3
3
3
ns
/OE to output in low impedance
tOLZ
0
0
0
ns
/CS to output in high impedance
tCHZ
7
8
8
ns
/OE to output hold in high impedance
tOHZ
7
8
8
ns
1
2, 3
Notes 1. See the output load shown in Figure 1.
2. Transition is measured at ± 200 mV from steady-state voltage with the output load shown in Figure 2.
3. These parameters are periodically sampled and not 100% tested.
Remark
These AC characteristics are in common regardless of package types.
Read Cycle Timing Chart 1 (Address Access)
tRC
Address (Input)
tAA
tOH
DOUT (Output)
Previous data out
Data out
Remarks 1. In read cycle, /WE should be fixed to high level.
2. /CS = /OE = VIL
Data Sheet M12223EJ5V0DS00
7
µPD434001AL
Read Cycle Timing Chart 2 (/CS Access)
tRC
Address (Input)
tAA
tACS
/CS (Input)
tCLZ
tCHZ
/OE (Input)
tOHZ
tOE
tOLZ
DOUT (Output)
High impedance
Data out
Caution
Address valid prior to or coincident with /CS low level input.
Remark
In read cycle, /WE should be fixed to high level.
8
Data Sheet M12223EJ5V0DS00
High impedance
µPD434001AL
Write Cycle
Parameter
Symbol
µPD434001AL-A15 µPD434001AL-A17 µPD434001AL-A20
MIN.
MAX.
MIN.
MAX.
MIN.
Unit
MAX.
Write cycle time
tWC
15
17
20
ns
/CS to end of write
tCW
10
11
12
ns
Address valid to end of write
tAW
10
11
12
ns
Write pulse width
tWP
10
11
12
ns
Data valid to end of write
tDW
7
8
9
ns
Data hold time
tDH
0
0
0
ns
Address setup time
tAS
0
0
0
ns
Write recovery time
tWR
1
1
1
ns
/WE to output in high impedance
tWHZ
Output active from end of write
tOW
7
8
3
8
3
Notes
3
ns
1, 2
ns
Notes 1. Transition is measured at ± 200 mV from steady-state voltage with the output load shown in Figure 2.
2. These parameters are periodically sampled and not 100% tested.
Remark
These AC characteristics are in common regardless of package types.
Write Cycle Timing Chart 1 (/WE Controlled)
tWC
Address (Input)
tCW
/CS (Input)
tAW
tAS
/WE (Input)
tWR
tWP
tACS
tCLZ
tDW
DIN (Input)
tDH
Data in
tOH
tWHZ
tOW
High impedance
DOUT (Output)
tAA
Caution
/CS or /WE should be fixed to high level during address transition.
Remarks 1. Write operation is done during the overlap time of a low level /CS and a low level /WE.
•
2. During tWHZ, DOUT pin is in the output state, therefore the input signals must not be applied to the
output.
3. When /WE is at low level, the DOUT pin is always high impedance. When /WE is at high level, read
operation is executed. Therefore /OE should be at high level to make the DOUT pin high impedance.
Data Sheet M12223EJ5V0DS00
9
µPD434001AL
Write Cycle Timing Chart 2 (/CS Controlled)
tWC
Address (Input)
tAS
tCW
/CS (Input)
tAW
tWP
tWR
/WE (Input)
tDW
tDH
Data in
DIN (Input)
High impedance
•
DOUT (Output)
Caution
/CS or /WE should be fixed to high level during address transition.
Remark
Write operation is done during the overlap time of a low level /CS and a low level /WE.
10
Data Sheet M12223EJ5V0DS00
µPD434001AL
Package Drawings
•
32-PIN PLASTIC SOJ (10.16mm (400))
B
32
17
C
1
D
16
G
J
E
F
U
M
N
S
M
Q
T
P
S
K
I
H
NOTE
Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
B
21.26±0.2
C
10.16
D
11.18±0.2
E
1.005±0.1
F
0.74
G
3.5±0.2
H
2.545±0.2
I
0.8 MIN.
J
2.6
K
M
1.27(T.P.)
0.40±0.10
N
0.12
P
9.4±0.20
Q
T
0.1
R0.85
U
0.20 +0.10
−0.05
P32LE-400A-1
Data Sheet M12223EJ5V0DS00
11
µPD434001AL
•
32-PIN PLASTIC TSOP (II) (10.16mm (400))
32
17
detail of lead end
F
P
E
1
16
A
H
G
C
D
M
N
M
J
I
S
L
S
B
NOTE
Each lead centerline is located within 0.21 mm of
its true position (T.P.) at maximum material condition.
K
ITEM
MILLIMETERS
A
21.17 MAX.
B
1.075 MAX.
C
1.27 (T.P.)
D
0.42 +0.08
−0.07
E
0.1±0.05
F
1.2 MAX.
G
H
0.97
11.76±0.2
I
J
10.16±0.1
0.8±0.2
K
0.145 +0.025
−0.015
L
0.5±0.1
M
0.21
N
0.10
P
+7°
3° −3°
S32G5-50-7JD2-1
12
Data Sheet M12223EJ5V0DS00
µPD434001AL
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the µPD434001AL.
Types of Surface Mount Device
µPD434001ALLE
: 32-pin plastic SOJ (10.16 mm (400))
µPD434001ALG5-7JD : 32-pin plastic TSOP (II) (10.16 mm (400)) (Normal bent)
Data Sheet M12223EJ5V0DS00
13
µPD434001AL
[ MEMO ]
14
Data Sheet M12223EJ5V0DS00
µPD434001AL
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet M12223EJ5V0DS00
15
µPD434001AL
• The information in this document is current as of May, 2000. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
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patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
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responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
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agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
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The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
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to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4