FEDL6665C-02
¡ Semiconductor
MSM6665C-xx
¡ Semiconductor
FEDL6665C-02
This version:
Aug. 2000
MSM6665C-xx
Previous version: Nov. 1997
DOT MATRIX LCD CONTROLLER WITH 17-DOT COMMON DRIVER AND 80-DOT SEGMENT
DRIVER
GENERAL DESCRIPTION
The MSM6665C-xx is a dot-matrix LCD control driver which has functions of displaying
characters, cursor and arbitrators.
The MSM6665C-xx is provided with a 17-dot common driver, 80-dot segment driver, display
RAM and character ROM, and is controlled with the commands from the serial interface.
The character ROM can change the font data by mask option.
The MSM6665C-02 has standard ROM with 256 different character fonts.
The MSM6665C-xx can drive a variety of LCD panels because the bias voltage, which determines
the LCD driving voltage, can be optionally supplied from the external source.
FEATURES
•
•
•
•
•
•
•
•
•
•
Serial interface
Contains a 17-dot common driver and an 80-dot segment driver.
Contains ROM with character fonts of (5 x 7 dots) x 256.
A built-in RC oscillator circuit.
Provided with 80-dot arbitrators.
Switchable between 1/9 duty (1 line; characters + cursor + arbitrator) and 1/17 duty (2 lines;
characters + cursor, 1 line; arbitrator).
Character blink operation can be switched between all-characters lighting-on mode and allcharacters lighting-off mode.
SiG C-MOS process
Arbitrator blink operation can be switched between 5-dot unit mode and 1-dot unit mode.
Package options :
128-pin plastic QFP (QFP128-P-1420-0.50-K) (Product name: MSM6665C-xxGS-K)
Aluminum pad chip
(Product name: MSM6665C-xx)
xx indicates code number.
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FEDL6665C-02
¡ Semiconductor
MSM6665C-xx
BLOCK DIAGRAM
C1 - C17
S1 - S80
17
80
VDD
COMMON
SEGMENT
VSS
DRIVER
DRIVER
VSS1
LATCH
VSS2
VSS3
SHIFT REGISTER
VSS4
VSS5
TEST1
CHARACTER
GENERATOR
ROM
(256x5x7dots)
RAM
TEST2
TEST3
F/F
GATE
(512bits)
9D/ 17D
RST
FREQUENCY
DIVIDER
OSC1
OSC2
OSC3
OSC
8
&
TIMING
GENERATION
SERIAL/PARALLEL INTERFACE
CS
C /D
SHT
SO
SI
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FEDL6665C-02
¡ Semiconductor
MSM6665C-xx
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
S58
S59
S60
S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
S74
S75
S76
S77
S78
S79
S80
NC
TEST3
TEST2
PIN CONFIGURATION (TOP VIEW)
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
TEST1
OSC3
OSC2
NC
OSC1
VDD
SO
RST
9D/17D
SHT
SI
C/D
NC
CS
VSS1
NC
VSS2
VSS3
VSS4
VSS5
VSS (GND)
C1
NC
C2
C3
NC
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
C17
C16
NC
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
NC
S45
S44
NC
S43
S42
S41
S40
S39
S38
NC
S37
S36
NC
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
NC : No connection
128-Pin Plastic QFP
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FEDL6665C-02
¡ Semiconductor
MSM6665C-xx
ABSOLUTE MAXIMUM RATINGS
Symbol
Condition
Rating
Unit
Applicable pin
Supply Voltage
V DD
Ta=25°C, VDD–VSS
–0.3 to +7
V
VDD, VSS
Bias Voltage
VBI
Ta=25°C, VDD–VSS5
–0.3 to +10
V
VDD, VSS5
Input Voltage
VI
Ta=25°C
–0.3 to VDD+0.3
V
All inputs
Power Dissipation
PD
1210
mW
–55 to +150
°C
Parameter
Storage Temperature
*1:
Ta=25°C
*1
QFP128-1420
TSTG
The power dissipation depends on the heat sink characteristic of the package.
Set a junction temperature at 150°C or lower.
RECOMMENDED OPERATING CONDITIONS
Parameter
*1:
Symbol
Condition
Range
Unit
Applicable pin
Supply Voltage
VDD
VDD–VSS
2.5 to 5.5
V
VDD, VSS
Bias Voltage
VBI
VDD–VSS5
3 to 8
V
VDD, VSS5
OSC1
Operating Frequency
fop
*1
65 to 115
kHz
Operating Temperature
Top
—
–40 to +85
°C
RC oscillation, external input clock frequency
(Note) Bias voltage list
(VBI=VDD–VSS5)
Symbol
1/5 bias
1/4 bias
Remarks
Highest voltage
VDD
VDD
VDD
VSS1
VDD–1/5VBI
VDD–1/4VBI
VSS2
VDD–2/5VBI
VSS3
VDD–3/5VBI
VSS4
VDD–4/5VBI
VDD–3/4VBI
VSS5
VSS5
VSS5
VDD–2/4VBI
Lowest voltage
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FEDL6665C-02
¡ Semiconductor
MSM6665C-xx
ELECTRICAL CHARACTERISTICS
DC Characteristics (1)
(VDD=2.5 to 3.5V, VBI=3 to 8V, Ta=–40 to +85°C)
Parameter
Condition
Symbol
VIH1
External clock input
"L" Input Voltage 1
VIL1
External clock input
"H" Input Voltage 2
VIH2
"L" Input Voltage 2
VIL2
"H" Input Current 1
IIH1
VI=VDD
"L" Input Current
IIL
VI=0V
"H" Input Current 2
IIH2
Pull-down resistance, VI=VDD
"H" Output Voltage
VOH
IOH=–1.5mA
"L" Output Voltage
VOL
OFF Leakage
"H" Input Voltage 1
—
—
Min. Typ. Max. Unit
0.8VDD —
0
VDD
— 0.2VDD
0.8VDD —
VDD
Applicable pin
V
OSC1
V
OSC1
V
Input pins except OSC1
0
— 0.2VDD
V
Input pins except OSC1
—
—
mA
Input pins except TEST
Input pins
1
—
—
–1
mA
0.01
—
0.4
mA TEST 1 - 3
VDD–0.5
—
—
V
SO
IOL=1.5mA
—
—
0.5
V
SO
IOFF
VI=VDD/0V
—
—
±1
mA
SO
OSC "H" Output Current
IOH
VI=VDD–0.5V
OSC "L" Output Current
IOL
VI=0.5V
COM Output Resistance
RC
SEG Output Resistance
RS
Supply Current 1
IDD1
Supply Current 2
IDD2
—
—
–0.15
mA OSC2, OSC3
0.15
—
—
mA OSC2, OSC3
I0=±50mA
—
—
6
kW
C1 - C17
I0=±10mA
—
—
18
kW
S1 - S80
—
—
0.5
mA
—
—
—
70
mA
—
RC oscillation, f=80kHz
C=56pF, RS=10kW
R=66kW, No load
External clock, f=80kHz
DC Characteristics (2)
(VDD=4.5 to 5.5V, VBI=3 to 8V, Ta=–40 to +85°C)
Parameter
Condition
Symbol
Min. Typ. Max. Unit
VIH1
External clock input
"L" Input Voltage 1
VIL1
External clock input
"H" Input Voltage 2
VIH2
—
"L" Input Voltage 2
VIL2
—
"H" Input Current 1
IIH1
"L" Input Current
IIL
"H" Input Current 2
IIH2
Pull-down resistance, VI=VDD
"H" Output Voltage
VOH
IOH=–1.5mA
"L" Output Voltage
VOL
IOL=1.5mA
OFF Leakage
IOFF
VI=VDD/0V
OSC "H" Output Current
IOH
VI=VDD–0.5V
OSC "L" Output Current
IOL
VI=0.5V
COM Output Resistance
RC
I0=±50mA
—
SEG Output Resistance
RS
I0=±10mA
—
Supply Current 1
IDD1
Supply Current 2
IDD2
"H" Input Voltage 1
0.8VDD —
0
VDD
— 0.2VDD
0.8VDD —
VDD
Applicable pin
V
OSC1
V
OSC1
V
Input pins except OSC1
0
— 0.2VDD
V
Input pins except OSC1
VI=VDD
—
—
1
mA
Input pins except TEST
VI=0V
—
—
–1
mA
Input pins
0.05
—
0.7
mA TEST 1 - 3
VDD–0.5
—
—
—
—
0.5
V
SO
—
—
±1
mA
SO
—
—
–0.5
mA OSC2, OSC3
0.5
—
—
mA OSC2, OSC3
—
6
kW
C1 - C17
—
18
kW
S1 - S80
—
—
1.3
mA
—
—
—
100
mA
—
V
SO
RC oscillation, f=80kHz
C=56pF, RS=10kW
R=66kW, No load
External clock, f=80kHz
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FEDL6665C-02
¡ Semiconductor
MSM6665C-xx
AC Characteristics
(VDD=2.5 to 5.5V, Ta=–40 to +85°C)
Parameter
Symbol
Condition
Min.
Max.
CS Setup Time
tCS
—
300
—
CS Hold Time
tCH
—
200
—
SO ON Delay Time
tON
—
—
200
SO OFF Delay Time
tOFF
—
—
200
SO Output Delay Time
tDLY
0
CL=45pF
Input Setup Time
tIS
—
200
200
—
Input Hold Time
tIH
—
200
—
—
100
—
Input Waveform Rise Time, Fall Time
tr, tf
Reset Pulse Input Pulse Width
tRT
All inputs
—
5
ns
µs
VIH2
VIL2
CS
t CH
SI
VIH2
VIL2
C/ D
VIH2
VIL2
t IH
t IS
VIH2
VIL2
SHT
t CS
SO
Unit
"Z"
VOH
VOL
"Z"
t OFF
t DLY
t ON
RST
* VIH2=0.8VDD
VIL2=0.2VDD
VOH=VDD–0.5V
VOL=0.5V
VIL2
t RT
Oscillation circuit
RS
OSC1
R
OSC2
C
OSC3
6/31
FEDL6665C-02
¡ Semiconductor
MSM6665C-xx
Oscillation characteristics 1 (RS=10kW, C=56pF, R variable characteristics)
1/17 duty
40
VDD=3.0V
VDD=5.0V
30
Frame Cycle¥2 (ms)
f=80kHz
Frame cycle¥2=27.2ms
20
10
0
55
65
75
85
95
R Resistance (kW)
Oscillation characteristics 2 (RS=10kW, R=66kW, C variable characteristics)
1/17 duty
40
VDD=3.0V
VDD=5.0V
30
Frame Cycle¥2 (ms)
f=80kHz
Frame cycle¥2=27.2ms
20
10
0
35
45
55
65
75
C Capacitance (pF)
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FEDL6665C-02
¡ Semiconductor
MSM6665C-xx
FUNCTIONAL DESCRIPTION
Pin Functional Description
• SI (Serial Input)
Input pin for inputting serially commands and display data in an 8-bit unit.
"H"=1 and "L"=0.
When CS pin is at “H” level, read-in is executed by the leading edge of SHT.
Whether input data is a command or data is determined by selecting a C/D level at the
8th leading edge of SHT.
The input data is a command if C/D="H", and display data if C/D="L".
• C/D (Command/Data)
Input pin for determining whether input data for SI pin is a command or display data.
Read-in is executed by the 8th leading edge of SHT. The input data is a command if C/
D="H", and display data if C/D="L".
• SHT (Shift Clock)
Clock input pin for reading-in SI input and C/D input.
Read-in is executed by the clock leading edge. Read-in operation is complete with 8
clocks. Maintain this SHT pin at "H" when there is no command and data input from the
SI pin. Inputting data during BUSY may cause malfunction.
Valid if CS pin is at "H" level.
• SO (Serial Out)
Serial output pin for reading-out BUSY/NON-BUSY and display data. "H"="1" and
"L"="0". If CS pin is at "H" level and Serial out Enable is set with the command, output
is executed.
Otherwise, this pin becomes high impedance. BUSY/NON-BUSY is output when CS
pin is at "H" level. BUSY if "L" and NON-BUSY if "H". It goes BUSY after the 8th leading
edge of SHT, then goes NON-BUSY automatically after a certain time.
Display data is output synchronously with the leading edge of SHT.
Input instruction SOE/D to set this output to Serial Out Enable or a high impedance state
since the pin status is undefined after the power is applied.
• CS (Chip Select)
Chip Select input pin.
"Chip Select ON" if CS pin is at "H" level, and "Chip Select OFF" at "L" level. When "L"
level is input, SO pin becomes open and SHT pin becomes equivalent to "H" level inside
of the IC. Moreover, it prevents the input rows of SI, C/D and SHT pins from current
flowing.
Note: For SI, C/D, SHT, SO, and CS, refer to "I/O Procedure".
• RST
Direct input reset input pin.
By inputting "L" level pulse into RST pin, SOE/D, DISP, ABBC1/5, and ABB commands
are set as D0="0". Before turning on the power, be sure to set RST pin at "L" level once.
Setting this pin at "L" level during command execution may cause malfunction.
• 9D/17D (1/9Duty/1/17Duty)
Duty setting input pin.
1/9duty is set if this pin is at "H" level, and 1/17duty at "L" level. Choice depends on the
type of panel to be used.
If 1/9duty is selected, common outputs C10 to C17 should be set open.
8/31
FEDL6665C-02
¡ Semiconductor
MSM6665C-xx
• TEST1, TEST2, TEST3
Test signal input pins.
The manufacturer uses these pins for testing.
The user should make these pins short-circuited to GND or open.
• OSC1, OSC2, OSC3
Pins used for 80kHz RC oscillation circuit formation and as external master clock input
pin. OSC2 and OSC3 are open during input of external master clock. See diagram below.
OSC1
10k W
OSC2
62±5kW
OSC1
OSC2
OPEN
56pF
OSC3
[RC oscillation circuit formation]
80kHz
OSC3
OPEN
[External master clock input]
< Oscillation circuit wiring diagram >
• C1 to C17, S1 to S80 (Common 1 - 17, Segment 1 - 80)
LCD output pins to be connected with the LCD panel. Turning into AC is made by frame
inversion. During use at 1/9duty, C1 to C9 pins are used, and C10 to C17 pins are set
open. See figure below.
Arbitrator
C1
C2
C8
C9
Cursor
C10
C16
C17
Cursor
S1
S80
<Relationship between panel and LCD output>
• VDD, VSS
Supply voltage pins. VDD should be set at "H" level.
VSS is a GND pin. If the battery is used, VDD is connected to the + pin, and VSS to the
– pin.
9/31
FEDL6665C-02
¡ Semiconductor
MSM6665C-xx
• VSS1, VSS2, VSS3, VSS4, VSS5
LCD bias voltages input pins.
The voltages that are input via VDD and VSS1 to VSS5 are output for driving LCD.
The LCD bias voltages are shown below.
[Case of 1/5 bias] (VBI=VDD–VSS5)
Highest voltage :
VDD
VSS1
VSS2
VSS3
VSS4
Lowest voltage :
VSS5
[Case of 1/4 bias] (VBI=VDD–VSS5)
Highest voltage :
VDD
VSS1
VSS2, VSS3
VSS4
Lowest voltage :
VSS5
(VDD–1/5 VBI)
(VDD–2/5 VBI)
(VDD–3/5 VBI)
(VDD–4/5 VBI)
(VDD–1/4 VBI)
(VDD–2/4 VBI)
(VDD–3/4 VBI)
10/31
FEDL6665C-02
¡ Semiconductor
MSM6665C-xx
List of Commands
X : Don't care
No. Mnemonics
Operation
1
LPA
Load Pointer
Address
2
LOT
Load Option
3
BKCG 1/0
Bank Change 1/0
4
SOE/D
5
DISP
6
ABBC 1/5
Arbitrator Blink
Control 1/5 dot
7
ABB
Arbitrator Blink
Serial Out
Enable/Disable
Display on/off
8
AINC
Address Increment
9
CHB
Character Blink on/off
10
CSC
Cursor Control
on/off
11
CSB
Cursor Blink
on/off
D
5
4
3
2
1
Comments
7
6
0
1
1
A5 A4 A3 A2 A1 A0 Serial addresses 0 to 47
1
0
1
1
X
X
I1
I0
1
0
0
X
0
0
0
1/0 Switching between display addresses
1
0
0
X
0
1
1
1/0 of SO
1
0
0
X
1
0
0
1/0 Display OFF if D0="0"
1
0
0
1
1
1
0
1/0 a 5dot unit. 1dot if D0="1", 5 dot if
Meanings for I1 and I0 are set as in
the table below.
Valid only when 1/9duty.
1
0
0
0
1
1
0
1
0
0
X
1
X
1
0 and 15, and between 16 and 31.
Switching output and high impedance
Display ON if D0="1"
Sets arbitrator blink in a 1dot unit or
D0="0"
Data that is input via SI after setting
D0="1", is set as data for arbitrator
1/0
blink (1-dot unit). This is cancelled by
D0="0"
X
Pointer address is incremented by 1.
0
X
X
X
0
0
1/0 X
Controls blinking of characters and
arbitrators (5-dot). Though arbitrator
blink that is set as all-blank dispalyed
is acceptable, blinking does not occur.
0
X
X
X
0
1
1/0 X
Turns cursor on or off.
0
X
X
X
1
0
1/0 X
Controls blinking of cursor.
But, though blinking setting with
no cursor-on setting is acceptable,
blinking does not occur.
1/0 X
CHB + CSB
12
CCB
Character & Cursor
Blink on/off
0
X
X
X
1
1
13
BPC
Blink Pattern
Control
1
0
0
X
0
0
Sets blink patterns of characters.
1
1/0 ( q :chara.) if D0="1" ( n :chara.)
if D0="0"
Notes :
1. Commands number 1 to 7 and command number 13 do not affect pointer address.
2. By entering commands number 8 to 12 or display code data, pointer address is
automatically incremented by 1.
3. When Reset is entered, commands numbers 5 to 7 or number 13 are set to D0="0".
I1
I0
0
0
Operation is canceled. (No operation)
0
1
Hereafter, equivalent to writing blank code at each AINC execution.
1
0
Hereafter, cursor-off and blink-cancellation are executed at each AINC execution.
1
1
Both of above two operations are made.
Operation
11/31
FEDL6665C-02
¡ Semiconductor
MSM6665C-xx
Command Description
[D7, D6, D5, D4, D3, D2, D1, D0], X=don’t care
• LPA (Load Pointer Address)
[1,1,A5,A4,A3,A2,A1,A0]
The command sets "address" data into the address pointer to specify an address on
which command execution affects and an address where display data is stored. The
"address" is a number between 0 and 2FH, given by A0 through A5 in hexadecimal.
When addresses 30H through 3FH are specified, display data and CHB, CSC, CSB, CCB
commands become invalid through an address pointer is set up. Normally, the address
pointer is a loop of 0H through 2FH.
• LOT (Load Option)
[1,0,1,1,X,X,I1,I0]
This command indicates some specific operation of display at the current address which
is performed each time of AINC command execution.
Operation is specified by bit I1 and I0 of the command.
I1
I0
0
0
Operation is cancelled. (No operation)
0
1
Hereafter, equivalent to writing blank code at each AINC execution.
1
0
Hereafter, Cursor-off and blink-cancellation are executed at each AINC execution.
1
1
Both of above two operations are made.
Operation
Note: When blink-cancellation is executed, all RAM data, which controls blinks for each bit
of the arbitrator, go zeros.
• BKCG 1/0 (Bank Change 1/0)
[1,0,0,X,0,0,0,1/0]
Command used to do switching between display address groups (switching between
BANKs), which is valid only when 1/9duty display is selected.
When D0 is "0", display address range becomes 0 through 15, and 32 through 47.
When D0 is "1", display address range becomes 16 through 31, and 32 through 47.
Command execution and display data setting are not affected by Bank setting.
The D0 status is not changed by Reset inputting. The D0 status is unknown when the
system is powered on. So D0 must be set to "0" or "1" with the command.
• SOE/D (Serial Out Enable/Disable)
[1,0,0,X,0,1,1,1/0]
Command used to control the impedance of SO output pin.
When D0 is "1", display data is output via SO pin. When D0 is "0", SO pin goes to high
impedance.
The D0 status is not changed by Reset inputting. The D0 status is unknown when the
system is powered on. So D0 must be set to "0" or "1" with the command.
12/31
FEDL6665C-02
¡ Semiconductor
MSM6665C-xx
• DISP (Display on/off)
[1,0,0,X,1,0,0,1/0]
Command used to control display-on and display-off of the LCD panel.
When D0 is "1", the display of the LCD panel goes on, and When D0 is "0", it goes off.
When the display is off, the VDD level voltage is output on all of pins of both the segment
drivers and the common drivers.
D0 is set to "0" after inputting Reset.
• ABBC 1/5 (Arbitrator Blink Control 1/5 dot)
[1,0,0,1,1,1,0,1/0]
Command used to do switching between arbitrator’s blinking in a 1-dot unit and or in
a 5-dot unit.
When D0 is "1", arbitrator’s blinking comes in the 1 dot unit mode.
When D0 is "0", it comes in the 5-dot unit mode.
D0="0" is set after inputting Reset.
Note:
1-dot unit blink setting Æ See ABB.
5-dot unit blink setting Æ See CHB.
• ABB (Arbitrator Blink)
[1,0,0,0,1,1,0,1/0]
Command used to control on/off of blinking, which is valid only when arbitrator’s
blinking is set in the 1-dot unit mode.
Data , which are entered via SI pin after setting D0="1", are taken as arbitrator blink data
(1-dot unit).
Input blink data correspond to each of arbitrator’s dots. When "1", blinking is on, and
when "0", blinking is off.
Note that the arbitrator, which arbitrator-on is not specified, is not able to blink, though
blink-setting is available. Dummy data must be entered into the arbitrator blink data D5
thru D7.
It is impossible to write data in addresses 00 through 31.
D0="0" is set after inputting Reset.
Note:
If blink is set in the 5-dot unit mode, ABB command setting (D0="1" or "0") is
available, but blink-on/off setting via input of display data is impossible.
• AINC (Address Increment)
[1,0,0,X,1,X,1,X]
Command used to increment the value of the address pointer by 1.
The pointer is increment by 1 each time this command is executed. The operation set by
LOT command is given to the address before being increased by 1 each time this
command is execution.
13/31
FEDL6665C-02
¡ Semiconductor
MSM6665C-xx
• CHB (Character Blink on/off)
[0,X,X,X,0,0,1/0,X]
Command used to control blinking of characters and arbitrator (5-dot unit).
This command is executed to the address indicated by the address pointer. Blinking is
on by setting D1="1", and off by setting D1="0".
For blinking of characters, all lighting-on or all lighting-off, and characters-displaying
are repeated.
Choosing between all lighting-on and all lighting-off is controlled by BPC command.
For arbitrator, only lighting bits repeat lighting-off and lighting-on. The blink control or
arbitrator is valid only when ABBC1/5="0" and in the 5-dot unit mode.
Refer to BPC.
• CSC (Cursor Control on/off)
[0,X,X,X,0,1,1/0,X]
Command used to control lighting-on and lighting-off of cursor.
This command is executed to the address indicated by the address pointer.The cursor
is lighting on by setting D1="1", and lighting off by setting D1="0".
• CSB (Cursor Blink on/off)
[0,X,X,X,1,0,1/0,X]
Command used to control blinking of cursor.
This command is executed to the address indicated by the address pointer. Blinking is
on by setting D1="1", and off by setting D1="0".
The blinking in the address, where cursor-lighting-on is not specified, does not occur,
though the command of blinking is acceptable. Blinking starts by specifying cursorlighting-on.
• CCB (Character & Cursor Blink on/off)
[0,X,X,X,1,1,1/0,X]
Command used to execute both CHB command and CSB command.
• BPC (Blink Pattern Control)
[1,0,0,X,0,0,1,1/0]
Command used to control blink patterns of characters.
When D0="1" is set, all lighting-off (35 dots) and characters-displaying are repeated.
When D0="0" is set, all lighting-on (35 dots) and characters-displaying are repeated.
When D0="1" is set, if characters are blanks, their blinkings do not occur in appearance.
When D0="0" is set, if characters are in all lighting-on, their blinkings do not occur in
appearance.
D0 is set to "0" after inputting Reset.
[D0 = "1"]
[D0 = "0"]
• Increment (+1) in address pointer
When display data or arbitrator data (1-dot unit) is entered or when the following
commands are executed, the address pointer is incremented by 1.
AINC, CHB, CSC, CSB and CCB.
14/31
FEDL6665C-02
¡ Semiconductor
MSM6665C-xx
I/O Procedure
• Input timing (command input, display data input)
8-bit input synchronization is taken by this leading edge.
If input in an 8-bit unit is kept, the following leading edges of CS is not needed.
CS
don't care
C/ D
C/D
MSB
SI
LSB
SHT
SO
LSB
"Z"
BUSY
MSB
NON-BUSY/ BUSY
17D : Max=[Master clock cycle] x 10
9D : Max=[Master clock cycle] x 20
• Output timing (display code data output)
Code data or arbitrator data indicated by the address pointer is always output, provided
that the SOE command has already been input.
Synchronization in an 8-bit unit.
CS
don't care
C/ D
SHT
SO
"Z"
LSB
MSB
BUSY
NON-BUSY
NON-BUSY/ BUSY
17D : Max=[Master clock cycle] x 10
9D : Max=[Master clock cycle] x 20
Note: If CS is set at "L" level when 8-bit read-out is not complete, and CS is set at "H" level
again, then read-out operation is executed, uncomplete data will be output continually
and the remaining read-out data will be zero.
15/31
FEDL6665C-02
¡ Semiconductor
MSM6665C-xx
Various Frequency Calculation Method
• Original Clock Frequency and Blink Frequency
Blink cycle calculation
([Original clock cycle] x 5) x 214 = Blink cycle ............................................. Formula 1
From formula 1, the blink frequency can be calculated.
Example)
When the original clock frequency is 80kHz.
Clock cycle Ts=12.5[µs]
From formula 1,
Blink cycle Tb=(12.5 x 10-6 x 5) x 214 = 1.024 [s]
Thus,
Blink frequency = 1 [Hz]
• Original Clock Frequency and Frame Frequency
Frame cycle calculation
1/9 DUTY: (Original clock cycle) x 1152 = Frame cycle ............................. Formula 2
1/17 DUTY: (Original clock cycle) x 1088 = Frame cycle ........................... Formula 3
From Formula 2,3 the blink frequency can be calculated.
Example)
In the original clock 80kHz and 1/17 DUTY specifications
Clock cycle Ts=12.5 [µs]
From formula 3,
Clock cycle Tf=12.5 x 10-6 x 1088 = 13.6 [ms]
Thus,
Frame frequency = 73.5 [Hz]
16/31
FEDL6665C-02
¡ Semiconductor
MSM6665C-xx
Display and Memory Address
Arbitrator
Character 1
Cursor 1
Display
Character 2
Cursor 2
RAM map
32
33
47
Arbitrator
0
1
15
Character 1
0
1
15
Cursor 1
16
17
31
Character 2
16
17
31
Cursor 2
Note: Characters are entered with codes.
Arbitrator is displayed with no CG ROM. The relationship between input data and
display is shown below.
S5n+1
S5n+5
n : 0 - 15
D4
D0
Dummy input is required for serial data D7 through D5. Either "1" or "0" is available
for data to be input into D7 through D5.
17/31
FEDL6665C-02
¡ Semiconductor
MSM6665C-xx
Flowchart for Power-On Timing
Turn on power
Reset input
Wait for 20 clocks
CS="H"
SOE/D, D0="1"
Wait for 20 clocks
BPC and BKCG
5ms required; external reset input or power-on reset input
Clock input for initial busy clear.
at 1/17 duty
)
( 1020 clocks
clocks at 1/9 duty
The device is enabled.
Make the SO output enable, to perform busy detection.
Input a wait for the SOE/D command processing. (For the processing
of each command after this, perform busy detection. *1)
Set the blink pattern and bank change mode.
command set
LOT, I1="1", I0="1"
AINC executed 48 times
LOT, I1="1", I0="1"
Set the Load Option. (Blank-code writing and blink-cancellation
are executed each time the AINC command is executed.)
Input the AINC command to clear the RAM data.
Release the Load Option.
Input display data for initial screen
NO
Is Input of display data for
initial screen completed?
YES
DISP, D0="1"
Display is turned on and the initial screen is displayed.
Normal operation
*1
After the required commands and display data are intered, perform busy detection
based on the SO pin status. When it is confirmed that the status has been changed
from BUSY (SO="L") to NON-BUSY (SO="H"), enter the next data.
If busy detection is not performed, wait for 10 master oscillation clocks when used at
1/17 duty or for 20 master oscillation clocks when at 1/9 duty, then enter the next
data.
18/31
FEDL6665C-02
¡ Semiconductor
MSM6665C-xx
Waveforms Applied to LCD
1/17 duty (1/5 bias)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
C1
VDD
VSS1
VSS2
VSS3
VSS4
VSS5
C2
VDD
VSS1
VSS2
VSS3
VSS4
VSS5
C17
VDD
VSS1
VSS2
VSS3
VSS4
VSS5
Sn
VDD
VSS1
VSS2
VSS3
VSS4
VSS5
= lighting on
= lighting off
19/31
FEDL6665C-02
¡ Semiconductor
MSM6665C-xx
1/9duty (1/4 bias)
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
C1
VDD
VSS1
VSS2, 3
VSS4
VSS5
C2
VDD
VSS1
VSS2, 3
VSS4
VSS5
C9
VDD
VSS1
VSS2, 3
VSS4
VSS5
Sn
VDD
VSS1
VSS2, 3
VSS4
VSS5
= lighting on
= lighting off
20/31
FEDL6665C-02
¡ Semiconductor
MSM6665C-xx
1/17 duty (1/4 bias)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
C1
VDD
VSS1
VSS2, 3
VSS4
VSS5
C2
VDD
VSS1
VSS2, 3
VSS4
VSS5
C17
VDD
VSS1
VSS2, 3
VSS4
VSS5
Sn
VDD
VSS1
VSS2, 3
VSS4
VSS5
= lighting on
= lighting off
21/31
FEDL6665C-02
¡ Semiconductor
MSM6665C-xx
Character Codes and Fonts of MSM6665C-02
00H :
08H :
10H :
18H :
20H : SP
28H : (
30H : 0
38H : 8
01H :
09H :
11H :
19H :
21H : !
29H : )
31H : 1
39H : 9
02H :
0AH :
12H :
1AH :
22H : "
2AH : *
32H : 2
3AH : :
03H :
0BH :
13H :
1BH :
23H : #
2BH : +
33H : 3
3BH : ;
04H :
0CH :
14H :
1CH :
24H : $
2CH : ,
34H : 4
3CH : <
05H :
0DH :
15H :
1DH :
25H : %
2DH : -
35H : 5
3DH : =
06H :
0EH :
16H :
1EH :
26H : &
2EH : .
36H : 6
3EH : >
07H :
0FH :
17H :
1FH :
27H : '
2FH : /
37H : 7
3FH : ?
22/31
FEDL6665C-02
¡ Semiconductor
MSM6665C-xx
40H : @
48H : H
50H : P
58H : X
60H : `
68H : h
70H : p
78H : x
41H : A
49H : I
51H : Q
59H : Y
61H : a
69H : i
71H : q
79H : y
42H : B
4AH : J
52H : R
5AH : Z
62H : b
6AH : j
72H : r
7AH : z
43H : C
4BH : K
53H : S
5BH : [
63H : c
6BH : k
73H : s
7BH : {
44H : D
4CH : L
54H : T
5CH : \
64H : d
6CH : l
74H : t
7CH : |
45H : E
4DH : M
55H : U
5DH : ]
65H : e
6DH : m
75H : u
7DH : }
46H : F
4EH : N
56H : V
5EH : ^
66H : f
6EH : n
76H : v
7EH : ~
47H : G
4FH : O
57H : W
5FH : _
67H : g
6FH : o
77H : w
7FH :
23/31
FEDL6665C-02
¡ Semiconductor
MSM6665C-xx
24/31
FEDL6665C-02
¡ Semiconductor
MSM6665C-xx
25/31
FEDL6665C-02
¡ Semiconductor
MSM6665C-xx
APPLICATION CIRCUITS
Example :
1/17 duty, 1/5 bias
Cursor-contained (5 x 7 dots)16-character x 2-line LCD panel
17 dots
COM
C1 - C17
80 dots
SEG
S1
-
S80
OSC1
Bias Generation circuit
VDD
MSM6665C-xx
VSS1
OSC2
OSC3
VSS2
10kW
62kW
56pF
OSC1
or
OSC2
80kHz
OPEN
OSC3
OPEN
LCD bias
VSS3
VSS4
VSS5
9D/ 17D
RST
Vss
TEST 1~3
CS
C/ D SHT
SO
SI
PORT
26/31
FEDL6665C-02
¡ Semiconductor
MSM6665C-xx
PAD CONFIGURATION
Pad Layout
Chip size : 6.09 ¥ 4.97mm
Passivation film etched hole : 110 ¥ 110mm
Y
92
59
93
58
X
117
34
1
33
Pad Coordinates
Pad No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pad Name
C15
C14
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
VSS
VSS5
VSS4
VSS3
VSS2
X (µm)
Y (µm)
–2486
–2336
–2186
–2036
–1886
–1736
–1586
–1436
–1286
–1136
–986
–836
–686
–536
–386
–227
–67
83
233
383
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
Pad No.
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Pad Name
VSS1
CS
C/D
SI
SHT
9D/17D
RST
SO
VDD
OSC1
OSC2
OSC3
TEST1
TEST2
TEST3
S80
S79
S78
S77
S76
X (µm)
533
683
833
983
1133
1283
1433
1583
1733
1891
2308
2489
2639
2870
2870
2870
2870
2870
2870
2870
Y (µm)
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–2332
–1797
–1647
–1347
–1197
–1047
–897
–747
27/31
FEDL6665C-02
¡ Semiconductor
Pad No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Pad Name
S75
S74
S73
S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
MSM6665C-xx
X (µm)
Y (µm)
2870
2870
2870
2870
2870
2870
2870
2870
2870
2870
2870
2870
2870
2870
2870
2870
2870
2870
2482
2332
2182
2032
1882
1732
1582
1432
1282
1132
982
832
682
532
382
232
82
–68
–218
–368
–518
–668
–597
–447
–297
–147
3
153
303
453
603
753
903
1053
1203
1353
1503
1653
1803
1953
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
Pad No.
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
Pad Name
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
C17
C16
X (µm)
Y (µm)
–818
–968
–1118
–1268
–1418
–1568
–1718
–1868
–2018
–2168
–2318
–2468
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
–2870
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
2332
1803
1653
1503
1353
1203
1053
903
753
603
453
303
153
3
–147
–297
–447
–597
–747
–897
–1047
–1197
–1347
–1497
–1647
–1797
28/31
FEDL6665C-02
¡ Semiconductor
MSM6665C-xx
Pin and Pad Correspondence
The symbol for each chip pad and package pin is equal, but the numbers for each pad and pin
are not equal.
If both chips and packaged devices are used, the number for each chip pad should be
corresponded to the number for each package pin according to each symbol listed in the table
below.
Symbol
Chip Package
Symbol
Chip Package
Pad
Pin
Symbol
Chip Package
Pad
Pin
Symbol
Chip Package
Pad
Pin
Pad
Pin
C15
1
65
OSC2
31
100
S55
61
3
S25
91
37
C14
2
66
OSC3
32
101
S54
62
4
S24
92
38
C13
3
67
TEST1
33
102
S53
63
5
S23
93
39
C12
4
68
TEST2
34
103
S52
64
6
S22
94
40
C11
5
69
TEST3
35
104
S51
65
7
S21
95
41
C10
6
70
S80
36
106
S50
66
8
S20
96
42
C9
7
71
S79
37
107
S49
67
9
S19
97
43
C8
8
72
S78
38
108
S48
68
10
S18
98
44
C7
9
73
S77
39
109
S47
69
11
S17
99
45
C6
10
74
S76
40
110
S46
70
12
S16
100
46
C5
11
75
S75
41
111
S45
71
14
S15
101
47
C4
12
76
S74
42
112
S44
72
15
S14
102
48
C3
13
78
S73
43
113
S43
73
17
S13
103
49
C2
14
79
S72
44
114
S42
74
18
S12
104
50
C1
15
81
S71
45
115
S41
75
19
S11
105
51
VSS(GND)
16
82
S70
46
116
S40
76
20
S10
106
52
VSS5
17
83
S69
47
117
S39
77
21
S9
107
53
VSS4
18
84
S68
48
118
S38
78
22
S8
108
54
VSS3
19
85
S67
49
119
S37
79
24
S7
109
55
VSS2
20
86
S66
50
120
S36
80
25
S6
110
56
VSS1
21
88
S65
51
121
S35
81
27
S5
111
57
CS
22
89
S64
52
122
S34
82
28
S4
112
58
C/D
23
91
S63
53
123
S33
83
29
S3
113
59
SI
24
92
S62
54
124
S32
84
30
S2
114
60
SHT
25
93
S61
55
125
S31
85
31
S1
115
61
9D/17D
26
94
S60
56
126
S30
86
32
C17
116
62
RST
27
95
S59
57
127
S29
87
33
C16
117
63
SO
28
96
S58
58
128
S28
88
34
–
–
–
VDD
29
97
S57
59
1
S27
89
35
–
–
–
OSC1
30
98
S56
60
2
S26
90
36
–
–
–
29/31
FEDL6665C-02
¡ Semiconductor
MSM6665C-xx
PACKAGE DIMENSIONS
(Unit : mm)
QFP128-P-1420-0.50-K
.
Mirror finish
Oki Electric Industry Co., Ltd.
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5 mm)
1.19 TYP.
4/Nov. 28, 1996
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
30/31
FEDL6665C-02
¡ Semiconductor
MSM6665C-xx
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
6.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
9.
MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 2000 Oki Electric Industry Co., Ltd.
Printed in Japan
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