DATA SHEET MOS INTEGRATED CIRCUIT µPD75004, 75006, 75008 4-BIT SINGLE-CHIP MICROCOMPUTER DESCRIPTION The µPD75008 is one of the 75X Series 4-bit single-chip microcomputer. In addition to high-speed operation with 0.95 µ s minimum instruction execution time for the CPU, the µ PD75008 employs a serial bus interface with standard NEC format, the µPD75004 is a powerful product with a high cost/performance ratio. The µ PD75P008 with PROM, which is provided with µPD75008, is applicable for evaluating systems under development, or for small-scale production of developed systems. Detailed functions are described in the following user’s manual. Be sure to read it for designing. µPD7500X Series User’s Manual: IEM-5033 FEATURES • Capable of high-speed operation and variable instruction execution time to power save • 0.95 µs, 1.91 µs, 15.3 µs (Main system clock: operating at 4.19 MHz) • 122 µs (Subsystem clock: operating at 32.768 kHz) • 75X architecture comparable to that for an 8-bit microcomputer is employed • Built-in NEC standard serial bus interface (SBI) • Clock operation at reduced power dissipation (5 µA TYP. : operating at 3 V) • Enhanced timer function (3 channels) • Interrupt functions especially enhanced for applications, such as remote control receiver APPLICATIONS VCRs, CD players, telephones, cameras, blood pressure gauges, etc. Unless otherwise specified, µ PD75008 is treated as the representative model throughout this manual. The information in this document is subject to change without notice. Document No. IC-2633C (O. D. No. IC-7673E) Date Published November 1993 P Printed in Japan The mark ★ shows major revised points. NEC Corporation 1990 µPD75004, 75006, 75008 ORDERING INFORMATION Part Number Package Quality Grade µPD75004CU-xxx 42-pin plastic shrink DIP (600 mil) Standard µPD75004GB-xxx-3B4 44-pin plastic QFP (■ ■ 10 mm) Standard µPD75006CU-xxx 42-pin plastic shrink DIP (600 mil) Standard µPD75006GB-xxx-3B4 44-pin plastic QFP (■ ■ 10 mm) Standard µPD75008CU-xxx 42-pin plastic shrink DIP (600 mil) Standard µPD75008GB-xxx-3B4 44-pin plastic QFP (■ ■ 10 mm) Standard Remarks: xxx is ROM code number. Please refer to “Quality Grade on NEC Semiconductor Devices” (Document Number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. 2 µPD75004, 75006, 75008 FUNCTIONAL OUTLINE Item Function Instruction Execution Time 0.95, 1.91, and 15.3 µs, (Main system clock: operating at 4.19 MHz) 122 µs (Subsystem clock: operating at 32.768 kHz) Internal Memory 6016 × 8-bit (µPD75006) 4096 × 8-bit (µPD75004) ROM 8064 × 8-bit (µPD75008) RAM General-Purpose Registers 512 × 4-bit • 4-bit manipulation: 8 • 8-bit manipulation: 4 8 CMOS Input pins 18 I/O Port CMOS input/output pins 34 Internal pull-up resistor specification by software is possible. : 25 Can directly drive LED: 4 8 N-ch open-drain input/output Can directly drive LED: 8 Withstand voltage: 10V Internal pull-up resistor specification by mask option is possible. Timer/event counter Timer 3 chs Basic interval timer: Also serves as watchdog timer Watch timer: Buzzer output possible Serial Interface 3-line serial I/O mode 2-line serial I/O mode SBI mode Bit Sequential Buffer 16 bits Clock Output Function Φ, fx/2 , fx/2 , fx/2 3 4 6 Vector Interrupt External: 3, Internal: 3 Test Input External: 1, Internal: 1 System Clock Oscillator Main system clock oscillation ceramic/crystal oscillator Subsystem clock oscillation crysal ocillator Standby Function STOP/HALT mode Operating Temperature Range –40 to +85°C Operating Supply Voltage 2.7 to 6.0 V Package 42-pin plastic shrink DIP (600 mil) 44-pin plastic QFP (■ ■ 10 mm) 3 µPD75004, 75006, 75008 CONTENTS 4 1. PIN CONFIGURATION (TOP VIEW) ............................................................................................... 6 2. BLOCK DIAGRAM ........................................................................................................................... 8 3. PIN FUNCTIONS .............................................................................................................................. 9 3.1 PORT PINS ............................................................................................................................................. 9 3.2 NON PORT PINS ................................................................................................................................... 11 3.3 PIN INPUT/OUTPUT CIRCUITS ........................................................................................................... 12 3.4 SELECTION OF MASK OPTION .......................................................................................................... 14 3.5 RECOMMENDED PROCESSING OF UNUSED PINS .......................................................................... 14 3.6 NOTES ON USING THE P00/INT4, AND RESET PINS ...................................................................... 15 4. MEMORY CONFIGURATION .......................................................................................................... 16 5. PERIPHERAL HARDWARE FUNCTIONS ........................................................................................ 20 5.1 PORTS .................................................................................................................................................... 20 5.2 CLOCK GENERATOR CIRCUIT ............................................................................................................ 21 5.3 CLOCK OUTPUT CIRCUIT .................................................................................................................... 22 5.4 BASIC INTERVAL TIMER ..................................................................................................................... 23 5.5 WATCH TIMER ...................................................................................................................................... 24 5.6 TIMER/EVENT COUNTER ..................................................................................................................... 24 5.7 SERIAL INTERFACE .............................................................................................................................. 26 5.8 BIT SEQUENTIAL BUFFER ................................................................................................................... 28 6. INTERRUPT FUNCTIONS ................................................................................................................ 28 7. STANDBY FUNCTIONS .................................................................................................................. 30 8. RESET FUNCTION ........................................................................................................................... 31 9. INSTRUCTION SET ......................................................................................................................... 33 10. ELECTRICAL SPECIFICATIONS ...................................................................................................... 40 11. CHARACTERISTIC CURVES ........................................................................................................... 53 µPD75004, 75006, 75008 12. PACKAGE DRAWINGS ................................................................................................................... 58 13. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 61 APPENDIX A. DEVELOPMENT TOOLS .............................................................................................. 62 APPENDIX B. RELATED DOCUMENTS .............................................................................................. 63 5 µPD75004, 75006, 75008 1. PIN CONFIGURATION (Top View) • 42-pin plastic shrink DIP (600 mil) XT1 1 42 V SS XT2 2 41 P40 RESET 3 40 P41 X1 4 39 P42 P43 37 P50 P32 7 36 P51 P31 8 35 P52 34 P53 33 P60/KR0 32 P61/KR1 31 P62/KR2 µ PD75004CU-xxx 38 6 µ PD75006CU-xxx 5 µ PD75008CU-xxx X2 P33 P30 9 P81 10 P80 11 SI/SB1/P03 12 SO/SB0/P02 13 30 P63/KR3 SCK/P01 14 29 P70/KR4 INT4/P00 15 28 P71/KR5 TI0/P13 16 27 P72/KR6 INT2/P12 17 26 P73/KR7 INT1/P11 18 25 P20/PTO0 INT0/P10 19 24 P21 NC 20 23 P22/PCL V DD 21 22 P23/BUZ NC P12/INT2 P11/INT1 P10/INT0 NC V DD P23/BUZ P22/PCL P21 1 44 43 42 41 40 39 38 37 36 35 34 33 P71/KR5 2 32 P00/INT4 P70/KR4 3 31 P01/SCK P63/KR3 4 30 P02/SO/SB0 P62/KR2 5 29 P03/SI/SB1 P61/KR1 6 28 P80 P60/KR0 7 27 P81 P53 8 26 P30 P52 9 25 P31 P51 10 24 P32 P50 23 11 12 13 14 15 16 17 18 19 20 21 22 P33 µ PD75004GB–xxx–3B4 µ PD75006GB–xxx–3B4 X1 XT2 RESET XT1 V SS P40 P41 P42 P43 µ PD75008GB–xxx–3B4 X2 P72/KR6 NC 6 P20/PTO0 P73/KR7 • 44-pin plastic QFP (■ ■ 10 mm) P03/TI0 µPD75004, 75006, 75008 Pin names P00-P03 : Port 0 SO : Serial Output P10-P13 : Port 1 SB0,SB1 : Serial Bus 0,1 P20-P23 : Port 2 RESET : Reset Input P30-P33 : Port 3 TI0 : Timer Input 0 P40-P43 : Port 4 PTO0 : Programmable Timer Output 0 P50-P53 : Port 5 BUZ : Buzzer Clock P60-P63 : Port 6 PCL : Programmable Clock P70-P73 : Port 7 INT0, 1, 4 : External Test Interrupt 0,1,4 P80-P81 : Port 8 INT2 : External Test Input 2 KR0-KR7 : Key Return X1, 2 : Main System Clock Oscillation 1,2 SCK : Serial Clock XT1, 2 : Subsystem Clock Oscillation 1,2 SI : Serial Input NC : No Connection 7 8 2. INTBT TI0/P13 PTO0/P20 PROGRAM COUNTER * SP (8) TIMER/EVENT COUNTER #0 SI/SB1/P03 SO/SB0/P02 SCK/P01 CLOCKED SERIAL INTERFACE P00-P03 PORT 1 4 P10-P13 PORT 2 4 P20-P23 PORT 3 4 P30-P33 PORT 4 4 P40-P43 PORT 5 4 P50-P53 PORT 6 4 P60-P63 PORT 7 4 P70-P73 PORT 8 2 P80-P81 ALU BANK WATCH TIMER INTW 4 CY INTT0 BUZ/P23 PORT 0 BLOCK DIAGRAM BASIC INTERVAL TIMER GENERAL REG. PROGRAM MEMORY (ROM) 4096 × 8 BITS µ ( PD75004) 6016 × 8 BITS (µPD75006) 8064 × 8 BITS (µPD75008) DECODE AND CONTROL DATA MEMORY (RAM) 512 × 4 BITS INTCSI INT0/P10 INT1/P11 INTERRUPT CONTROL INT4/P00 KR0/P60 –KR7/P73 f X /2 N BIT SEQ. BUFFER (16) CLOCK OUTPUT CONTROL PCL/P22 CLOCK DIVIDER SYSTEM CLOCK GENERATOR SUB MAIN XT1 XT2 X1 X2 *: For µPD75004, 12 bits. For µPD75006 and µPD75008, 13 bits. STAND BY CONTROL CPU CLOCK V DD V SS RESET µPD75004, 75006, 75008 INT2/P12 µPD75004, 75006, 75008 3. PIN FUNCTIONS 3.1 PORT PINS (1/2) Also Served Pin Name Input/Output As P00 Input INT4 P01 Input/ Output SCK P02 Input/ Output SO/SB0 P03 Input/ Output SO/SB1 P10 INT0 P11 Input INT1 P12 INT2 P13 TI0 P20 PTO0 P21 Input/ Output P22 P23 — PCL Function 8-Bit I/O When Reset Input/ Output Circuit 1 TYPE* B 4-bit input port (PORT0) Pull-up resistors can be specified in 3-bit units for the P01 to P03 pins by software. F -A X Input F -B M -C With noise elimination function 4-bit input port (PORT1) Internal pull-up resistors can be specified in 4-bit units by software. X Input B -C 4-bit input/output port (PORT2) Internal pull-up resistors can be specified in 4-bit units by software. X Input E-B Programmable 4-bit input/output port (PORT3) This port can be specified for input/ output in bit units. Internal pull-up resistors can be specified in 4-bit units by software. X Input E-B BUZ P30* 2 P31* 2 — Input/ Output P32*2 P33*2 — — — 2 P40-43* Input/ Output — N-ch open-drain 4-bit input/output port (PORT4) Internal pull-up resistors can be specified in bit units. (mask option) Resistive voltage is 10 V in the opendrain mode. — N-ch open-drain 4-bit input/output port (PORT5) Internal pull-up resistors can be specified in bit units. (mask option) Resistive voltage is 10 V in the opendrain mode. ● P50-53*2 Input/ Output High level (with internal pull-up resistor) or high impedance High level (with internal pull-up resistor) or high impedance M M *1: Circles indicate Schmitt trigger inputs. 2: Can directly drive LED. 9 µPD75004, 75006, 75008 3.1 PORT PINS (2/2) Pin Name Input/Output Also Served As P60 P61 P62 KR0 Input/ Output KR1 KR2 P63 KR3 P70 KR4 P71 P72 Input/ Output P81 KR6 Programmable 4-bit input/output port (PORT6) This port can be specified for input/ output in bit units. Internal pull-up resistors can be specified in 4-bit units by software. When Reset Input/ Output Circuit 1 TYPE* Input F -A Input F -A Input E-B ● 4-bit input/output port (PORT7) Internal pull-up resistors can be specified in 4-bit units by software. Input/ Output — — 2-bit input/output port (PORT8) Internal pull-up resistors can be specified in 2-bit units by software. *1: Circles indicate Schmitt trigger inputs. 2: Can directly drive LED. 10 8-Bit I/O KR7 P73 P80 KR5 Function X µPD75004, 75006, 75008 3.2 NON PORT PINS Also Served Pin Name Input/Output As Functon When Reset Input/ Output Circuit TYPE*1 Input P13 Timer/event counter external event pulse Input Input B -C PTO0 Input/ Output P20 Timer/event counter output Input E-B PCL Input/ Output P22 Clock output Input E-B BUZ Input/ Output P23 Fixed frequency output (for buzzer or for trimming the system clock) Input E-B SCK Input/ Output P01 Serial clock input/output Input F -A SO/SB0 Input/ Output P02 Serial data output Serial bus input/output Input F -B SI/SB1 Input/ Output P03 Serial data input Serial bus input/output Input M -C Input P00 Edge detection vector interrupt input (both rising and falling edge detection are effective) Input B Input B -C TI0 INT4 P10 INT0 INT1 INT2 Input Clock synchronous P11 Edge detection vector interrupt input (detection edge can be selected) P12 Edge detection testable input (rising edge detection) Asynchronous Input B -C Input Asynchronous KR0-KR3 Input/ Output P60-P63 Parallel falling edge detection testable input Input F -A KR4-KR7 Input/ Output P70-P73 Parallel falling edge detection testable input Input F -A — To connect the crystal/ceramic oscillator to the main system clock generator. When inputting the external clock, input the external clock to pin X1, and the reverse phase of the external clock to pin X2. Input — — To connect the crystal oscillator to the subsystem clock generator. When the external clock is used, pin XT1 inputs the external clock. In this case, pin XT2 must be left open. X1, X2 Input XT1 Input Input — XT2 — RESET Input — System reset input — B NC *2 — — No connection — — VDD — — Positive power supply — — VSS — — GND — — — *1: Circles indicate Schmitt trigger inputs. 2: When sharing the printed circut board with the µPD75P008, the NC pin must be directly connected to VDD . 11 µPD75004, 75006, 75008 3.3 PIN INPUT/OUTPUT CIRCUITS The following shows a simplified input/output circuit diagram for each pin of the µPD75008. TYPE D (for TYPE E– B, F– A) TYPE A (for TYPE E–B) VDD VDD data P–ch OUT IN N–ch Input buffer of CMOS standard output disable Push–pull output that can be set in a output high–impedance state (both P–ch and N–ch are off) TYPE E–B TYPE B VDD P.U.R. P.U.R. enable P–ch IN data IN/OUT Type D output disable Type A Schmitt trigger input with hysteresis characteristics TYPE B–C P.U.R. : Pull–Up Resistor TYPE F–A VDD P.U.R. VDD P.U.R. enable P.U.R. P–ch P.U.R. enable P–ch data IN/OUT Type D IN output disable Type B P.U.R. : Pull–Up Resistor 12 P.U.R. : Pull–Up Resistor µPD75004, 75006, 75008 TYPE F–B TYPE M–C VDD VDD P.U.R. P.U.R. P.U.R. enable output disable (P) P–ch P.U.R. enable VDD P–ch IN/OUT P-ch IN/OUT data output disable data N-ch output disable (N) N-ch output disable P.U.R. : Pull–Up Resistor P.U.R. : Pull–Up Resistor TYPE M VDD P.U.R. enable (Mask option) data IN/OUT N-ch (withstand voltage: +10 V) output disable Middle voltage input buffer (withstand voltage: +10 V) P.U.R. : Pull–Up Resistor 13 µPD75004, 75006, 75008 3.4 SELECTION OF MASK OPTION The following mask operations are available and can be specified for each pin. Table 3-1 Mask Option Selection Pin P40-P43, P50-P53 Mask Option • With pull-up resistor • Without pull-up resistor *: Mask option can be specified in bit units. ★ 3.5 RECOMMENDED PROCESSING OF UNUSED PINS Table 3-2 Processing of Unused Pins Pin P00/INT4 Recommended Connections Connect to VSS P01/SCK P02/SO/SB0 Connect to VSS or VDD P03/SI/SB1 P10/INT0-P12/INT2 P13/TI0 Connect to VSS P20/PTO0 P21 P22/PCL P23/BUZ P30-P33 Input : Connect to VSS or VDD P40-P43 Output: Open P50-P53 P60-P63 P70-P73 P80-P81 14 XT1 Connect to VSS or VDD XT2 Open µPD75004, 75006, 75008 3.6 ★ NOTES ON USING THE P00/INT4, AND RESET PINS In addition to the functions described in Sections 3.1 PORT PINS and 3.2 NON PORT PINS, an exclusive function for setting the test mode, in which the internal fuctions of the µPD75008 are tested (solely used for IC tests), is provided to the P00/INT4 and RESET pins. If a voltage exceeding VDD is applied to either of these pins, the µPD75008 is put into test mode. Therefore, even when the µ PD75008 is in normal operation, if noise exceeding the VDD is input into any of these pins, the µPD75008 will enter the test mode, and this will cause problems for normal operation. As an example, if the wiring to the P00/INT4 pin or the RESET pin is long, stray noise may be picked up and the above montioned problem may occur. Therefore, all wiring to these pins must be made short enough to not pick up stray noise. If noise cannot be avoided, suppress the noise using a capacitor or diode as shown in the figure below. • Connect a diode having a low VF across P00/INT4 and RESET, and VDD . (0.3 V max.) • Connect a capacitor across P00/INT4 and RESET, and V DD. VDD VDD Low VF diode VDD VDD P00/INT4, RESET P00/INT4, RESET 15 µPD75004, 75006, 75008 4. MEMORY CONFIGURATION • Program memory (ROM) ... 4096 × 8 bits (0000H-0FFFH) : µPD75004 ... 6016 × 8 bits (0000H-177FH) : µPD75006 ... 8064 × 8 bits (0000H-1F7FH) : µPD75008 • 0000H-0001H : Vector table to which address from which program is started is written after reset • 0002H-000BH: Vector table to which address from which program is started is written after interrupt • 0020H-007FH : Table area referenced by GETI instruction • Data memory (RAM) • Data area .... 512 × 4 bits (000H–1FFH) • Peripheral hardware area .... 128 × 4 bits (F80H–FFFH) Address 000H 7 6 5 4 MBE 0 0 0 0 Internal reset start address (upper 4 bits) Internal reset start address (lower 8 bits) 002H MBE 0 0 0 INTBT/INT4 start address (upper 4 bits) INTBT/INT4 start address (lower 8 bits) 004H MBE 0 0 0 INT0 start address (upper 4 bits) INT0 start address (lower 8 bits) 006H MBE 0 0 0 INT1 start address (upper 4 bits) INT1 start address (lower 8 bits) 008H MBE 0 0 0 INTCSI start address (upper 4 bits) INTCSI start address (lower 8 bits) 00AH MBE 0 0 0 CALLF !faddr instruction entry address INTT0 start address (upper 4 bits) CALL ! addr instruction subroutine entry address INTT0 start address (lower 8 bits) BRCD ! caddr instruction branch address 020H GETI instruction reference table 07FH 080H Branch destination address and subroutine entry address for GETI instruction 7FFH 800H FFFH Fig. 4-1 Program Memory Map (µPD75004) 16 BR $addr instruction relational branch address (–15 to –1, +2 to +16) µPD75004, 75006, 75008 Address 0000H 7 6 5 MBE 0 0 0 Internal reset start address (upper 5 bits) Internal reset start address (lower 8 bits) 0002H MBE 0 0 INTBT/INT4 start address (upper 5 bits) INTBT/INT4 start address (lower 8 bits) 0004H MBE 0 0 INT0 start address (upper 5 bits) INT0 start address (lower 8 bits) 0006H MBE 0 0 INT1 start address (upper 5 bits) INT1 start address (lower 8 bits) 0008H MBE 0 0 INTCSI start address (upper 5 bits) INTCSI start address (lower 8 bits) 000AH MBE 0 0 CALLF ! faddr instruction entry address INTT0 start address (upper 5 bits) INTT0 start address (lower 8 bits) CALL ! addr instruction subroutine entry address BRCB ! caddr BR ! addr instruction instruction branch branch address address 0020H BR $addr instruction relational branch address (–15 to –1, +2 to +16) GETI instruction reference table 007FH 0080H Branch destination address and subroutine entry address for GETI instruction 07FFH 0800H 0FFFH 1000H BRCB ! caddr instruction branch address 177FH Fig. 4-2 Program Memory Map (µPD75006) 17 µPD75004, 75006, 75008 Address 0000H 7 6 5 MBE 0 0 0 Internal reset start address (upper 5 bits) Internal reset start address (lower 8 bits) 0002H MBE 0 0 INTBT/INT4 start address (upper 5 bits) INTBT/INT4 start address (lower 8 bits) 0004H MBE 0 0 INT0 start address (upper 5 bits) INT0 start address (lower 8 bits) 0006H MBE 0 0 INT1 start address (upper 5 bits) INT1 start address (lower 8 bits) 0008H MBE 0 0 INTCSI start address (upper 5 bits) INTCSI start address (lower 8 bits) 000AH MBE 0 0 CALLF ! faddr instruction entry address INTT0 start address (upper 5 bits) INTT0 start address (lower 8 bits) CALL ! addr instruction subroutine entry address BRCB ! caddr BR ! addr instruction instruction branch branch address address 0020H BR $addr instruction relational branch address (–15 to –1, +2 to +16) GETI instruction reference table 007FH 0080H Branch destination address and subroutine entry address for GETI instruction 07FFH 0800H 0FFFH 1000H BRCB ! caddr instruction branch address 1F7FH Fig. 4-3 Program Memory Map (µPD75008) 18 µPD75004, 75006, 75008 Data memory General-purpose register area Stack area 000H Memory bank (8 × 4) 007H 008H 0 256× 4 (248 × 4) Data area Static RAM (512 × 4) 0FFH 100H 256× 4 1 1FFH Not provided F80H 128× 4 Peripheral hardware area 15 FFFH Fig. 4-4 Data Memory Map 19 µPD75004, 75006, 75008 5. PERIPHERAL HARDWARE FUNCTIONS 5.1 PORTS I/O ports are classified into the following 3 kinds: • CMOS input (PORT0, 1) : 8 • CMOS input/output (PORT2, 3, 6, 7, and 8) : 18 • N-ch open-drain input/output (PORT4, 5) : Total : 34 8 Table 5-1 Port Function Port Name (Symbol) PORT0 Function 4-bit input PORT1 Operation and Feature Can be always read or tested regardless of operation mode of multiplexed pin. Multiplexed with SO/SB0, SI/SB1, SCK, INT0-2, 4, and TIO Can be set in input or output mode in 1-bit units. Port 6 is multiplexed with KR0 to KR3. PORT3* PORT6 4-bit input/output PORT2 PORT7 PORT4* PORT5* PORT8 20 Can be set in input or output mode in 4-bit units. Ports 6 and 7 are used in pairs to input/output data in 8-bit units. 4-bit input/output (N-ch open-drain, 10 V) Can be set in input or output mode in 4-bit units. Ports 4 and 5 are used in pairs to input/output data in 8-bit units. 2-bit input/output Can be set input or output mode in 2-bit units. *: Can directly drive LED. Remarks Port 2 is multiplexed with PTO0, PCL, and BUZ. Port 7 is multiplexed with KR4-KR7. Can be connected to a pull-up resistor in 1-bit units by using mask option. — µPD75004, 75006, 75008 5.2 CLOCK GENERATOR CIRCUIT The operation of the clock generator circuit is determined by the processor clock control regiser (PPC) and system clock control register (SCC). This circuit can generate two types of clocks: main system clock and subsystem clock. In addition, it can also change the instruction execution time. • 0.95 µ s, 1.91 µ s, 15.3 µ s (main system clock: 4.19 MHz) • 122 µs (subsystem clock: 32.768 kHz) ★ · Basic interval timer (BT) · Timer/event counter · Serial interface · Watch timer · INT0 noise rejecter circuit · Clock output circuit XT1 XT2 Subsystem clock oscillator f XT Watch timer X1 WM.3 SCC Oscillator disable signal SCC3 1/8 to 1/4096 Frequency divider 1/2 1/16 Frequency divider Selector Main system f X clock oscillator Selector X2 1/4 Internal bus SCC0 PCC PCC0 Φ · CPU · INT0 noise rejecter circuit · Clock output circuit PCC1 4 HALT F/F PCC2 S HALT* STOP* PCC3 R PCC2, PCC3 clear signal STOP F/F Q S Q Wait release signal from BT RESET signal R Standby release signal from interrupt control circuit *: instruction execution. Remarks 1: f X = Main system clock frequency 2: f XT = Subsystem clock frequency 3: Φ = CPU clock 4: PCC: Processor clock control register 5: SCC: System clock control register 6: One clock cysle (t CY) of Φ is one machine cycle of an instruction. For tCY, refer to AC characteristics in 10. ELECTRICAL SPECIFICATIONS. Fig. 5-1 Clock Generator Block Diagram 21 µPD75004, 75006, 75008 5.3 CLOCK OUTPUT CIRCUIT The clock output circuit outputs clock pulse from the P22/PCL pin. This clock output circuit is used to output clock pulses to the remote control output, peripheral LSIs, etc. • Clock output (PCL) : Φ, 524, 262, 65.5 kHz (operating at 4.19 MHz) • Buzzer output (BUZ) : 2 kHz (operating at 4.19 MHz, or 32.768 kHz) Fig. 5-2 shows the clock output circuit configuration. From the clock generator Φ Output buffer fX/23 Selector fX/24 PCL/P22 fX/26 PORT2.2 CLOM3 CLOM2 CLOM1 CLOM0 CLOM P22 output latch Bit 2 of PMGB Port 2 input/ output mode specification bit 4 Internal bus Fig. 5-2 Clock Output Circuit Configuration Remarks: A measures to prevent outputting narrow width pulse when selecting clock output enable/ disable is taken. 22 µPD75004, 75006, 75008 5.4 BASIC INTERVAL TIMER The basic interval timer has these functions: • Interval timer operation which generates a reference time interrupt • Watchdog timer application which detects a program runaway • Selects the wait time for releasing the standby mode and counts the wait time • Reads out the count value From the clock generator Clear Clear fX/25 fX/27 Set signal Basic interval timer (8-bit frequency divider circuit) MPX fX/29 BT fX/212 3 BTM3 SET1* BT interrupt request flag BTM2 BTM1 Vector interrupt request IRQBT signal Wait release signal for standby release BTM0 BTM 4 8 Internal bus Remarks : *: Instruction execution Fig. 5-3 Basic Interval Timer Configuration 23 µPD75004, 75006, 75008 5.5 WATCH TIMER The µPD75008 has a built-in 1-ch watch timer. The watch timer is configured as shown in Fig. 5-4. • Sets the test flag (IRQW) with 0.5 sec interval. The standby mode can be released by IRQW. • 0.5 second interval can be generated either from the main system clock or subsystem clock. • Time interval can be advanced to 128 times faster (3.91 ms) by setting the fast mode. This is convenient for program debugging, test, etc. • Fixed frequency (2.048 kHz) can be output to the P23/BUZ pin. This can be used for beep and system clock frequency trimming. • The frequency divider circuit can be cleared so that zero second watch start is possible. fW (256 Hz: 3.91 ms) 27 fX 128 From the (32.768 kHz) clock generator f XT (32.768 kHz) Selector fW Frequency divider (32.768 kHz) f W (2.048 16 kHz) fW 2 14 INTW (IRQW set signal) Selector (2 Hz 0.5 sec) Clear Output buffer P23/BUZ WM PORT2.3 WM7 WM6 WM5 WM4 WM3 WM2 WM1 WM0 8 P23 output latch Bit 2 of PMGB Port 2 input/output mode Bit test instruction Internal bus ( ) is for f X = 4.194304 MHz, fXT = 32.768 kHz. Fig. 5-4 Watch Timer Block Diagram 5.6 TIMER/EVENT COUNTER The µPD75008 has a built-in 1-ch timer/event counter. The timer/even counter has these functions: • Programmable interval timer operation • Outputs square-wave signal of an arbitrary frequency to the PTO0 pin. • Event counter operation • Divides the TI0 pin input in N and outputs to the PTO0 pin (frequency divider operation). • Supplies serial shift clock to the serial interface circuit. • Count condition read out function 24 Internal bus 8 SET1*1 TM0 8 8 TMOD0 TOE0 TO enable flag Modulo register (8) TM07 TM06 TM05 TM04 TM03 TM02 TM01 TM00 Coincidence Comparator (8) Input buffer Bit 2 of PGMB Port 2 input/ output mode To serial interface 8 PORT1.3 PORT2.0 P20 output latch 8 TOUT F/F Reset P20/PTO0 Output buffer T0 P13/TI0 2 From * the clock generator Count register (8) MPX CP Clear ( INTT0 IRQT0 set signal ) Timer operation start signal *1: SET1: Instruction execution *2: Refer to Fig. 5-1. Fig. 5-5 Timer/Event Counter Block Diagram 25 µPD75004, 75006, 75008 RESET IRQT0 clear signal µPD75004, 75006, 75008 5.7 SERIAL INTERFACE The µPD75008 is equipped with a serial interface that operates in the following modes: • Three-line serial I/O mode (MSB/LSB first selectable) • Two-line serial I/O mode (MSB first) • SBI mode (MSB first) In the three-line I/O mode, the microcomputer can be connected to a microcomputer in the 75X series or 78K series devices, or various I/O devices. In the two-line serial mode and SBI mode, communication can be established with two or more devices. 26 Internal bus 8/4 CSIM 8 Bit test 8 8 Slave address register (SVA) (8) SBIC Coincidence signal Address comparator (8) RELT CMDT SET CLR (8) D SO latch Q ACKT ACKE BSYE Selector P03/SI/SB1 Shift register (SIO) Bit test Bit manipulation Selector P02/SO/SB0 Busy/ acknowledge output circuit Bus release/ command/ acknowledge detector circuit P01/SCK P01 output latch Serial clock control circuit INTCSI control circuit ( Serial clock selector INTCSI IRQCSI set signal fX/23 fX/24 fX/26 TOUT F/F (from timer/ event counter) External SCK Fig. 5-6 Serial Interface Block Diagram ) 27 µPD75004, 75006, 75008 Serial clock counter RELD CMDD ACKD µPD75004, 75006, 75008 5.8 BIT SEQUENTIAL BUFFER .... 16 BITS The bit sequential buffer is a data memory specifically provided for bit manipulation. With this buffer, addresses and bit specifications can be sequentially up-dated in bit manipulation operation. Therefore, this buffer is very useful for processing long data in bit units. FC3H Address bit 3 Symbol L register 2 FC2H 1 0 3 BSB3 L=F 2 FC1H 1 0 3 BSB2 L=C L=B 2 FC0H 1 0 3 BSB1 L=8 L=7 2 1 0 BSB0 L=4 L=3 L=0 DECS L INCS L Remarks: For the pmem.@L addressing, the specification bit is shifted according to the L register. Fig. 5-7 Bit Sequential Buffer Format 6. INTERRUPT FUNCTIONS The µPD75008 has 8 different interrupt sources and multiplexed interrupt through the software control. In addition to that, the µPD75008 is also provided with two types of edge detection testable inputs. The interrupt control circuit of the µ PD75008 has these functions: • Hardware controlled vector interrupt function which can control whether or not to accept an interrupt by using the interrupt flag (IExxx) and interrupt master enable flag (IME). • The interrupt start address can be arbitrarily set. • Interrupt request flag (IRQxxx) test function (an interrupt generation can be confirmed by means of software). • Standby mode release (Interrupts to be released can be selected by the interrupt enable flag). 28 Internal bus 2 1 3 IM2 IM1 IM0 Interrupt enable flag (IE ××× ) INT BT INT0 /P10 INT1 /P11 Both edge delection circuit Edge Noise delection elimination circuit circuit Edge delection circuit IRQ1 INTT0 IRQT0 INTW IRQW Falling edge delection circuit Priority control circuit Vector table address generator IRQ2 Standby release signal IM2 Fig. 6-1 Interrupt Control Block Diagram 29 µPD75004, 75006, 75008 KR0/P60 KR7/P73 IRQ0 IRQCSI Rising edge delection circuit VRQn IRQ4 INTCSI INT2 /P12 IST0 Decoder IRQBT Selector INT4 /P00 IME µPD75004, 75006, 75008 7. STANDBY FUNCTIONS The µPD75008 has two different standby modes (STOP mode and HALT mode) to reduce the power consumption while waiting for program execution. Table 7-1 Each Status in Standby Mode STOP Mode Setting Instruction STOP instrtuction HALT instruction System Clock for Setting Can be set only when operating on the main system clock Can be set either with the main system clock or the subsystem clock Operation Status Clock Generator Only the main system clock stops its operation. Only the CPU clock Φ stops its operation. (oscillation continues) Basic Interval Timer No operation Can operate only when main system clock oscillates (Sets IRQBT at reference time interval) Serial Interface Can operate only when the external SCK input is selected for the serial clock Can operate only when external SCK input is selected as serial clock, or when main system clock oscillates Timer/Event Counter Can operate only when the TI0 pin input is selected for the count clock Can operate only when TI0 pin input is selected as count clock, or when main system clock oscillates Watch Timer Can operate when f XT is selected as the count clock Can operate External Interrupt INT1, INT2, and INT4 can operate. Only INT0 can not operate. CPU No operation Release Signal 30 HALT Mode An interrupt request signal from a hardware whose operation is enabled by the interrupt enable flag or the RESET signal input An interrupt request signal from a hardware whose operation is enabled by the interrupt enable flag or the RESET signal input µPD75004, 75006, 75008 8. RESET FUNCTION When the RESET signal is input, the µPD75008 is reset and each hardware is initialized as indicated in Table 8-1. Fig. 8-1 shows the reset operation timing. Wait (31.3ms/4.19MHz) RESET input Operation mode or standby mode HALT mode Operation mode Internal reset operation Fig. 8-1 Reset Operation by RESET Input Table 8-1 Status of Each Hardware after Reset (1/2) Hardware RESET Input in Standby Mode RESET Input during Operation The contents of the lower 4 bits of address 000H of the program memory are set to PC11-8, and the contents of address 001H are set to PC7-0. Same as at left Retained Undefined Skip Flag (SK0-2) 0 0 Interrupt Status Flag (IST0) 0 0 Program Counter (PC) PSW Carry Flag (CY) Bank Enable Flag (MBE) Stack Pointer (SP) The contents of bit 7 of address 000H of the program memory is set to MBE. Same as at left Undefined Undefined Data Memory (RAM) Retained * Undefined General-Purpose Register (X, A, H, L, D, E, B, C) Retained Undefined 0 0 Undefined Undefined 0 0 0 0 FFH FFH Bank Selection Register (MBS) Basic Interval Counter (BT) Timer Mode Register (BTM) Timer/Event Counter Counter (T0) Module Register (TMOD0) Mode Register (TM0) TOE0, TOUT F/F Watch Timer Mode Register (WM) 0 0 0, 0 0, 0 0 0 *: Data of address 0F8H to 0FDH of the data memory becomes undefined when a RESET signal is input. 31 µPD75004, 75006, 75008 Table 8-1 Status of Each Hardware after Reset (2/2) Hardware Serial Interface Clock Generator, Clock Output Circuit Interrupt Function Digital Port Shift Register (SIO) RESET Input during Operation Retained Undefined Operation Mode Register (CSIM) 0 0 SBI Control Register (SBIC) 0 0 Slave Address Register (SVA) Retained Undefined Processor Clock Control Register (PCC) 0 0 System Clock Control Register (SCC) 0 0 Clock Output Mode Register (CLOM) 0 0 Interrupt Enable Flag (IExxx) 0 0 Interrupt Master Enable Flag (IME) 0 0 INT0, INT1, INT2 Mode Registers (IM0, 1, 2) 0, 0, 0 0, 0, 0 Output Buffer Off Off Output Latch Clear (0) Clear (0) Input/Output Mode Register (PMGA, B, C) 0 0 Pull-Up Resistor Specification Register (POGA, B) 0 0 Retained Specified Bit sequential buffer (BSB0-3) 32 RESET Input in Standby Mode µPD75004, 75006, 75008 9. INSTRUCTION SET (1) Operand representation and description Describe one or more operands in the operand field of each instruction according to the operand representation and description methods of the instruction (for details, refer to RA75X Assembler Package User's Manual - Language (EEU-730)). With some instructions, only one operand should be selected from several operands. The uppercase characters, +, and – are keywords and must be described as is. Describe an appropriate numeric value or label as immediate data. The symbols in the register and flag symbols can be described as labels in the places of mem, fmem, pmem, and bit (for details, refer to µPD7500X Series User‘s Manual (IEM-5033)). However, fmem and pmem restricts the label that can be described. Representation Description reg reg1 X, A, B, C, D, E, H, L X, B, C, D, E, H, L rp rp1 rp2 XA, BC, DE, HL BC, DE, HL BC, DE rpa rpa1 HL, DE, DL DE, DL n4 n8 4-bit immediate data or label 8-bit immediate data or label mem* bit 8-bit immediate data or label 2-bit immediate data or label fmem pmem FB0H to FBFH,FF0H to FFFH immediate data or label FC0H to FFFH immediate data or label addr µPD75004 0000H to 0FFFH immediate data or label µPD75006 0000H to 177FH immediate data or label µPD75008 0000H to 1F7FH immediate data or label caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20H to 7FH immediate data (where bit0 = 0) or label PORTn IExxx MBn PORT0 to PORT8 IEBT, IECSI, IET0, IE0, IE1, IE2, IE4, IEW MB0, MB1, MB15 *: Only even address can be described as mem for 8-bit data processing. 33 µPD75004, 75006, 75008 (2) Legend of operation field A : A register; 4-bit accumulator B : B register; 4-bit accumulator C : C register; 4-bit accumulator D : D register; 4-bit accumulator E : E register; 4-bit accumulator H : H register; 4-bit accumulator L : L register; 4-bit accumulator X : X register; 4-bit accumulator XA : Register pair (XA); 8-bit accumulator BC : Register pair (BC); 8-bit accumulator DE : Register pair (DE); 8-bit accumulator HL : Register pair (HL); 8-bit accumulator PC : Program counter SP : Stack pointer CY : Carry flag; or bit accumulator PSW : Program status word MBE : Memory bank enable flag PORTn : Port n (n = 0 to 8) 34 IME : Interrupt mask enable flag IExxx : Interrupt enable flag MBS : Memory bank selector register PCC . : Processor clock control register (xx) : Contents addressed by xx xxH : Hexadecimal data : Delimiter of address and bit µPD75004, 75006, 75008 (3) Symbols in addressing area field *1 MB = MBE . MBS (MBS = 0, 1, 15) *2 MB = 0 *3 MBE = 0 : MB = 0 (00H-7FH) MB = 15 (80H-FFH) MBE = 1 : MB = MBS (MBS = 0, 1, 15) *4 MB = 15, fmem = FB0H-FBFH, FF0H-FFFH *5 MB = 15, pmem = FC0H-FFFH *6 addr = 000H-FFFH (µPD75004) 0000H-177FH (µPD75006) 0000H-1F7FH (µPD75008) *7 addr = (Current PC) – 15 to (Current PC) – 1 (Current PC) + 2 to (Current PC) + 16 *8 caddr = 000H-FFFH ( µPD75004) 0000H-0FFFH (PC 12 = 0 : µPD75006, 75008) 0000H-177FH (PC 12 = 1 : µPD75006) 0000H-1F7FH (PC 12 = 1 : µPD75008) *9 faddr = 0000H-07FFH *10 taddr = 0020H-007FH Remarks 1: (4) Data memory addressing Program memory addressing MB indicates memory bank that can be accessed. 2: In *2, MB = 0 regardless of MBE and MBS. 3: In *4 and *5, MB = 15 regardless of MBE and MBS. 4: *6 to *10 indicate areas that can be addressed. Machine cycle field In this field, S indicates the number of machine cycles required when an instruction having a skip function skips. The value of S varies as follows: • When no instruction is skipped ........................................................................ S=0 • When 1-byte or 2-byte instruction is skipped ................................................. S=1 • When 3-byte instruction (BR ! addr or CALL ! addr) is skipped .................. S=2 Note : The GETI instruction is skipped in one machine cycle. One machine cycle equals to one cycle of the CPU clock Φ, (=tCY), and can be changed in three steps depending on the setting of the processor clock control register (PCC). 35 µPD75004, 75006, 75008 Instructions Mnemonics Transfer MOV XCH MOVT Operand Machine Bytes Cycles Operation Addressing Area Skip Conditions A, #n4 1 1 A ← n4 reg1, #n4 2 2 reg1 ← n4 XA, #n8 2 2 XA ← n8 String effect A HL, #n8 2 2 HL ← n8 String effect B rp2, #n8 2 2 rp2 ← n8 A, @HL 1 1 A ← (HL) A, @rpa1 1 1 A ← (rpa1) *2 XA, @HL 2 2 XA ← (HL) *1 @HL, A 1 1 (HL) ← A *1 @HL, XA 2 2 (HL) ← XA *1 *3 String effect A *1 A,mem 2 2 A ← (mem) XA, mem 2 2 XA ← (mem) *3 mem, A 2 2 (mem) ← A *3 *3 mem, XA 2 2 (mem) ← XA A, reg 2 2 A ← reg XA, rp 2 2 XA ← rp reg1, A 2 2 reg1 ← A rp1, XA 2 2 rp1 ← XA A, @HL 1 1 A ↔ (HL) A, @rpa1 1 1 A ↔ (rpa1) *2 XA, @HL 2 2 XA ↔ (HL) *1 A, mem 2 2 A ↔ (mem) *3 XA, mem 2 2 XA ↔ (mem) *3 A, reg1 1 1 A ↔ reg1 XA, rp 2 2 XA ↔ rp XA, @PCDE 1 3 • µPD75004 XA ← (PC11-8+DE)ROM *1 • µPD75006, 75008 XA ← (PC12-8+DE)ROM XA, @PCXA 1 3 • µPD75004 XA ← (PC11-8+XA)ROM • µPD75006, 75008 XA ← (PC12-8+XA)ROM Arith- ADDS A, #n4 1 1+S Opera- ADDC A, @HL 1 1+S A, @HL 1 1 tion SUBS A, @HL 1 1+S SUBC A, @HL 1 AND A, #n4 2 A, @HL metic OR XOR Accumu- RORC lator ManipuNOT lation 36 A ← A+n4 carry A ← A+(HL) *1 A, CY ← A+(HL)+CY *1 A ← A-(HL) *1 1 A, CY ← A-(HL)-CY *1 2 A ← A ∧ n4 1 1 A ← A ∧ (HL) A, #n4 2 2 A ← A ∨ n4 A, @HL 1 1 A ← A ∨ (HL) A, #n4 2 2 A ← A ∨ n4 A, @HL 1 1 A ← A ∨ (HL) A 1 1 CY ← A0, A3 ← CY, An-1 ← An A 2 2 A←A *1 *1 *1 carry borrow µPD75004, 75006, 75008 Instructions Mnemonics Incre- INCS ment/ Decrement DECS Compare SKE Operand Machine Bytes Cycles Operation Addressing Area Skip Conditions reg 1 1+S reg ← reg+1 @HL 2 2+S (HL) ← (HL)+1 *1 (HL) = 0 mem 2 2+S (mem) ← (mem)+1 *3 (mem) = 0 reg 1 1+S reg ← reg-1 reg = FH reg, #n4 2 2+S Skip if reg = n4 reg = n4 @HL, #n4 2 2+S Skip if (HL) = n4 A, @HL 1 1+S Skip if A = (HL) A, reg 2 2+S Skip if A = reg reg = 0 *1 (HL) = n4 *1 A = (HL) A = reg Carry SET1 CY 1 1 CY ← 1 flag CLR1 CY 1 1 CY ← 0 Manipu- SKT CY 1 1+S lation CY 1 1 CY ← CY mem.bit 2 2 (mem.bit) ← 1 *3 Bit fmem.bit 2 2 (fmem.bit) ← 1 *4 Manipu- pmem.@L 2 2 (pmem7-2 + L 3-2.bit(L1-0)) ← 1 *5 lation @H+mem.bit 2 2 (H + mem 3-0.bit) ← 1 *1 mem.bit 2 2 (mem.bit) ← 0 *3 fmem.bit 2 2 (fmem.bit) ← 0 *4 pmem.@L 2 2 (pmem 7-2 + L 3-2.bit(L1-0)) ← 0 *5 @H+mem.bit 2 2 (H+mem3-0.bit) ← 0 *1 mem.bit 2 2+S Skip if (mem.bit) = 1 *3 fmem.bit 2 2+S Skip if (fmem.bit) = 1 *4 (fmem.bit) = 1 pmem.@L 2 2+S Skip if (pmem 7-2+L 3-2.bit (L1-0 )) = 1 *5 (pmem.@L) = 1 @H+mem.bit 2 2+S Skip if (H + mem 3-0.bit) = 1 *1 (@H+mem.bit) = 1 mem.bit 2 2+S Skip if (mem.bit) = 0 *3 (mem.bit) = 0 fmem.bit 2 2+S Skip if (fmem.bit) = 0 *4 (fmem.bit) = 0 (pmem.@L) = 0 NOT1 Memory/ SET1 CLR1 SKT SKF OR1 XOR1 CY = 1 (mem.bit) = 1 pmem.@L 2 2+S Skip if (pmem7-2 +L3-2.bit (L1-0)) = 0 *5 @H+mem.bit 2 2+S Skip if (H + mem 3-0.bit) = 0 *1 (@H+mem.bit) = 0 2 2+S Skip if (fmem.bit) = 1 and clear *4 (fmem.bit) = 1 pmem.@L 2 2+S Skip if (pmem 7-2+L 3-2.bit (L 1-0)) = 1 and clear *5 (pmem.@L) = 1 @H+mem.bit 2 2+S Skip if (H+mem 3-0.bit) = 1 and clear *1 (@H+mem.bit) = 1 *4 SKTCLR fmem.bit AND1 Skip if CY = 1 CY,fmem.bit 2 2 CY ← CY ∧ (fmem.bit) CY,pmem.@L 2 2 CY ← CY ∧ (pmem 7-2+L 3-2.bit(L1-0)) *5 CY,@H+mem.bit 2 2 CY ← CY ∧ (H+mem3-0.bit) *1 CY,fmem.bit 2 2 CY ← CY ∨ (fmem.bit) *4 CY,pmem.@L 2 2 CY ← CY ∨ (pmem 7-2+L3-2.bit (L1-0)) *5 CY,@H+mem.bit 2 2 CY ← CY ∨ (H+mem3-0.bit) *1 CY,fmem.bit 2 2 CY ← CY ∨ (fmem.bit) *4 CY,pmem.@L 2 2 CY ← CY ∨ (pmem7-2+L3-2.bit (L1-0)) *5 CY,@H+mem.bit 2 2 CY ← CY ∨ (H+mem3-0.bit) *1 37 µPD75004, 75006, 75008 Instructions Mnemonics Branch BR Operand addr Machine Bytes Cycles — — Operation • µPD75004 PC11-0 ← addr (The most suitable instruction is selectable from among BRCB !caddr, and BR $addr depending on the assembler.) Addressing Area Skip Conditions *6 • µPD75006, 75008 PC12-0 ← addr (The most suitable instruction is selectable from among BR !addr, BRCB !caddr, and BR $addr depending on the assembler.) !addr 3 3 • µPD75006, 75008 PC12-0 ← addr *6 $addr 1 2 • µPD75004 PC11-0 ← addr *7 • µPD75006, 75008 PC12-0 ← addr BRCB !caddr 2 2 • µPD75004 PC11-0 ← caddr 11-0 *8 • µPD75006, 75008 PC12-0 ← PC 12 + caddr11-0 Subroutine/ Stack Control CALL !addr 3 3 • µPD75004 (SP-4)(SP-1)(SP-2) ← PC11-0 (SP-3) ← MBE, 0, 0, 0 PC11-0 ← addr, SP ← SP-4 *6 • µPD75006, 75008 (SP-4)(SP-1)(SP-2) ← PC11-0 (SP-3) ← MBE, 0, 0, PC12 PC12-0 ← addr, SP ← SP-4 CALLF !faddr 2 2 • µPD75004 (SP-4)(SP-1)(SP-2) ← PC11-0 (SP-3) ← MBE, 0, 0, 0 PC11-0 ←0, faddr, SP ← SP-4 *9 • µPD75006, 75008 (SP-4)(SP-1)(SP-2) ← PC11-0 (SP-3) ← MBE, 0, 0, PC12 PC12-0 ← 0, 0, faddr, SP ← SP-4 RET 1 3 • µPD75004 MBE, x, x, x ← (SP+1) PC11-0 ← (SP)(SP+3)(SP+2) SP ← SP+4 • µPD75006, 75008 MBE, x, x, PC 12 ← (SP+1) PC11-0 ← (SP)(SP+3)(SP+2) SP ← SP+4 RETS 1 3+S • µPD75004 MBE, x, x, x ← (SP+1) PC11-0 ← (SP)(SP+3)(SP+2) SP ← SP+4, then skip unconditionally • µPD75006, 75008 MBE, x, x, PC 12 ← (SP+1) PC11-0 ← (SP)(SP+3)(SP+2) SP ← SP+4, then skip unconditionally 38 Undefined µPD75004, 75006, 75008 Instructions Mnemonics Subrou- RETI Operand Machine Bytes Cycles 1 3 tine/ Stack Control Operation PUSH POP • µPD75004 MBE, x, x, x ← (SP+1) PC11-0 ← (SP)(SP+3)(SP+2) PSW ← (SP+4)(SP+5), SP ← SP+6 rp 1 1 (SP-1)(SP-2) ← rp, SP ← SP-2 BS 2 2 (SP-1) ← MBS, (SP-2) ← 0, SP ← SP-2 rp 1 1 rp ← (SP+1)(SP), SP ← SP+2 BS 2 2 MBS ← (SP+1), SP ← SP+2 2 2 IME ← 1 2 2 IExxx ← 1 2 2 IME ← 0 IExxx 2 2 IExxx ← 0 A, PORTn 2 2 A ← PORTn (n = 0-8) XA, PORTn 2 2 XA ← PORTn+1,PORTn (n = 4, 6) EI rupt IExxx Control DI I/O IN * OUT * PORTn, A 2 2 PORTn ← A (n = 2-8) PORTn, XA 2 2 PORTn+1 , PORTn ← XA (n = 4, 6) CPU HALT 2 2 Set HALT Mode (PCC.2 ← 1) Control STOP 2 2 Set STOP Mode (PCC.3 ← 1) NOP 1 1 No Operation Special Skip Conditions • µPD75006, 75008 MBE, x, x, PC 12 ← (SP+1) PC11-0 ← (SP)(SP+3)(SP+2) PSW ← (SP+4)(SP+5), SP ← SP+6 (Cont‘d) Inter- Addressing Area SEL MBn 2 2 GETI taddr 1 3 MBS ← n (n = 0, 1, 15) • µPD75004 Where TBR instruction, PC11-0 ← (taddr)3-0+(taddr+1) ......................................................... Where TCALL instruction, (SP-4)(SP-1)(SP-2) ← PC11-0 (SP-3) ← MBE, 0, 0, 0 PC11-0 ← (taddr)3-0+(taddr+1) SP ← SP-4 ......................................................... Except for TBR and TCALL instructions, Instruction execution of (taddr)(taddr+1) *10 • µPD75006, 75008 Where TBR instruction, PC12-0 ← (taddr)4-0+(taddr+1) ......................................................... Where TCALL instruction, (SP-4)(SP-1)(SP-2) ← PC11-0 (SP-3) ← MBE, 0, 0, PC12 PC12-0 ← (taddr)4-0+(taddr+1) SP ← SP-4 ......................................................... Except for TBR and TCALL instructions, Instruction execution of (taddr)(taddr+1) ............................. ............................. Depends on referenced instruction ............................. ............................. Depends on referenced instruction *: When executing the IN/OUT instruction, MBE = 0, or MBE = 1, and MBS = 15. 39 µPD75004, 75006, 75008 10. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (Ta = 25°C) Parameter Supply Voltage Input Voltage Symbol Conditions Ratings VDD VI1 Other than ports 4, 5 VI2 Ports 4, 5 w/pull-up resistor -0.3 to +7.0 V -0.3 to V DD+0.3 V -0.3 to V DD+0.3 Open drain Output Voltage VO High-Level Output Current IOH Low-Level Output IOL* Current Unit -0.3 to +11 V V -0.3 to V DD+0.3 V 1 pin -10 mA All pins -30 mA Ports 0, 3, 4, 5 Peak 30 mA 1 pin rms 15 mA Other than ports 0, 3, 4, 5 Peak 20 mA 1 pin rms 10 mA Total of ports 0, 3, 4, 5, 8 Peak 160 mA rms 120 mA Peak 66 mA rms 33 mA Total of ports 2, 6, 7 Operating Temperature Topt -40 to +85 °C Storage Temperature Tstg -65 to +150 °C *: rms = Peak value x √Duty CAPACITANCE (T a = 25°C, V DD = 0 V) Parameter 40 Symbol Input Capacitance CIN Output Capacitance COUT Input/Output Capacitance CIO Conditions f = 1 MHz Pins other than thosemeasured are at 0 V MIN. TYP. MAX. Unit 15 pF 15 pF 15 pF µPD75004, 75006, 75008 MAIN SYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = -40 to +85°C, V DD = 2.7 to 6.0 V) Recommended Constants Oscillator Ceramic Item Oscillation frequency(fXX)* 1 X1 X2 C1 C2 Crystal Conditions VDD = Oscillation voltage range X2 C1 TYP. MAX. 5.0 * 1.0 Oscillation stabiliza- After VDD come to tion time*2 MIN. of oscillation voltage range Oscillation frequency (fXX)* 1 X1 MIN. 3 4 1.0 Oscillation stabiliza- VDD = 4.5 to 6.0 V tion time*2 4.19 5.0 * Unit MHz ms 3 MHz 10 ms 30 ms C2 External Clock X1 input frequency (f X)*1 X1 X2 µ PD74HCU04 X1 input high-, low-level widths (t XH, t XL) 1.0 5.0 *3 100 500 MHz ns *1: The oscillation frequency and X1 input frequency are indicated only to express the characteristics of the oscillator circuit. For instruction execution time, refer to AC Characteristics. 2: Time required for oscillation to stabilize after VDD has been applied or the STOP mode has been released. 3: When the oscillation frequency is 4.19 MHz < fx ≤ 5.0 MHz, do not select PCC = 0011 as the ★ instruction execution time: otherwise, one machine cycle is set to less than 0.95 µs, falling short of the rated minimum value of 0.95 µs. ★ Note: When using the oscillation circuit of the main system clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: • Keep the wiring length as short as possible. • Do not cross the wiring over the other signal lines. • Do not route the wiring in the vicinity of lines through which a high alternating current flows. • Always keep the ground point of the capacitor of the osccillator circuit at the same potential as VSS . Do not connect the ground pattern through which a high current flows. • Do not extract signals from the oscillation circuit. 41 µPD75004, 75006, 75008 SUBSYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = -40 to +85°C, V DD = 2.7 to 6.0 V) Oscillator Recommended Constants Crystal XT1 Conditions Oscillation frequency (fXT)*1 XT2 R C3 Item MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.0 2 s 10 s Oscillation stabiliza- VDD = 4.5 to 6.0 V tion time*2 C4 External Clock XT1 XT2 Open XT1 input frequency (f XT)*1 32 100 kHz XT1 input high-, low-level widths (tXTH, t XTL ) 5 15 µs *1: Express the characteristcs of the oscillator circuit. 2: Time required for oscillator to stabilize after VDD has been applied. ★ Note: When using the oscillation circuit of the subsystem clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: • Keep the wiring length as short as possible. • Do not cross the wiring over the other signal lines. • Do not route the wiring in the vicinity of lines through which a high alternating current flows. • Always keep the ground point of the capacitor of the oscillator circuit at the same potential as VSS. Do not connect the ground pattern through which a high current flows. • Do not extract signals from the oscillation circuit. The amplification factor of the subsystem clock oscillation circuit is designed to be low to reduce the current dissipation and therefore, the subsystem clock oscillation circuit is influenced by noise more easily than the main system clock oscillation circuit. When using the subsystem clock, therefore, exercise utmost care in wiring the circuit. 42 µPD75004, 75006, 75008 RECOMMENDED OSCILLATION CIRCUIT CONSTANTS MAIN SYSTEM CLOCK: CERAMIC OSCILLATOR (Ta = -40 to +85°C) Manufacturer Murata Mfg. Product Name CSA x.xxMK* Frequency (MHz) 1.00 to 1.99 CSA x.xxMG093* Operating Voltage Range Recommended Circuit Constants C1 (pF) C2 (pF) MIN. (V) 30 30 2.7 30 30 2.7 MAX. (V) 2.00 to 2.44 CST x.xxMG093* — — 2.7 CSA x.xxMGU* 30 30 2.7 — — 2.7 30 30 3.0 — — 3.0 2.45 to 5.00 CST x.xxMGU* CSA x.xxMG* 6.0 2.00 to 5.00 CST x.xxMG* Kyoto Ceramic Toko KBR-1000H 1.00 100 100 2.7 KBR-2.0MS 2.00 47 47 2.7 KBR-4.0MS 4.00 33 33 2.7 KBR-5.0M 5.00 33 33 3.0 CRHB4.00M 4.00 27 27 3.0 6.0 *: x.xx indicates frequency. MAIN SYSTEM CLOCK: XTAL (Ta = -20 to +70°C) Manufacturer Kinseki Product Name Frequency (MHz) HC-6U 1.0 to 2.0 HC-18U HC-43U, 49/U 2.0 to 5.0 Operating Voltage Range Recommended Circuit Constants C1 (pF) 20 * C2 (pF) MIN. (V) MAX. (V) 22 2.7 6.0 *: Adjust the oscillation frequency in a range of C1 = 15 to 33 pF. SUBSYSTEM CLOCK: XTAL (Ta = -10 to +60°C) Manufacturer Kinseki Product Name P-3 Frequency (MHz) 32.768 Operating Voltage Range Recommended Circuit Constants C3 (pF) C4 (pF) R (kΩ) MIN. (V) MAX. (V) 18 * 18 330 2.7 6.0 *: Adjust the oscillation frequency in a range of C3 = 10 to 33 pF. 43 µPD75004, 75006, 75008 DC CHARACTERISTICS (Ta = -40 to +85°C, VDD = 2.7 to 6.0 V) Parameter High-Level Input Voltage Low-level Input Voltage Symbol Conditions MIN. TYP. MAX. Unit VIH1 Ports 2, 3, 8 0.7V DD VDD V VIH2 Ports 0, 1, 6, 7, RESET 0.8VDD VDD V VIH3 Ports 4, 5 w/pull-up resistor 0.7VDD VDD V Open-drain 0.7V DD 10 V VDD -0.5 VDD V VIH4 X1, X2, XT1 VIL1 Ports 2, 3, 4, 5, 8 0 0.3VDD V VIL2 Ports 0, 1, 6, 7, RESET 0 0.2VDD V VIL3 X1, X2, XT1 0 0.4 V High-Level Output Voltage VOH1 Ports 0, 2, 3, 6, 7, 8 Low-Level Output Voltage VOL1 Ports 0, 2, 3, 4, 5, 6, 7, 8 VOL2 High-Level Input Leakage Current Low-Level Input Leakage Current High-Level Output Leakage Current Low-Level Output Leakage Current ILIH1 SB0, 1 Open-drain VIN = V DD ILIH2 V DD = 4.5 to 6.0 V, IOH = -1 mA VDD -1.0 V IOH = -100 µA VDD -0.5 V Ports 4 and 5 V DD = 4.5 to 6.0 V IOL = 15 mA 0.4 2.0 V Ports 3 V DD = 4.5 to 6.0 V IOL = 15 mA 0.6 2.0 V V DD = 4.5 to 6.0 V IOL = 1.6 mA 0.4 V IOL = 400 µA 0.5 V Pull-up ≥ 1 kΩ V DD = 4.5 to 6.0 V 0.2VDD V Pull-up ≥ 5 kΩ 0.2VDD V Other than below 3 µA X1, X2, XT1 20 µA ILIH3 VIN = 10 V Ports 4, 5 (open-drain) 20 µA ILIL1 VIN = 0 V Other than below -3 µA X1, X2, XT1 -20 µA ILOH1 VOUT = VDD Other than below 3 µA ILOH2 VOUT = 10 V Ports 4, 5 (open-drain) 20 µA ILOL VOUT = 0 V -3 µA ILIL2 Internal Pull-Up Resistor RL1 RL2 Ports 0, 1, 2, 3, 6, 7, 8 V DD = 5.0 V±10% (except P00) VIN = 0V V DD = 3.0 V±10% Ports 4, 5 VOUT = V DD-2.0 V 15 40 30 V DD = 5.0 V±10% 15 V DD = 3.0 V±10% 10 40 80 kΩ 300 kΩ 70 kΩ 60 kΩ .... 44 µPD75004, 75006, 75008 Parameter Symbol Supply Current *1 IDD1 IDD2 TYP. MAX. 4.19 MHz*4 Conditions V DD = 5.0 V±10%* 2 2.5 8 mA crystal oscillator V DD = 3.0 V±10%* 3 0.35 1.2 mA C1 = C2 = 22pF HALT mode IDD3 32.768 kHz*5 IDD4 crystal oscillator IDD5 XT1 = 0 V STOP mode HALT mode MIN. Unit V DD = 5 V±10% 500 1500 µA V DD = 3 V±10% 150 450 µA V DD = 3 V±10% 30 90 µA V DD = 3 V±10% 5 15 µA V DD = 5 V±10% 0.5 20 µA 0.1 10 µA 0.1 5 µA VDD = 3 V±10% T a = 25°C *1: Current for the built-in pull-up resistor is not included. 2: When operand in the high-speed mode with the processor clock control register (PCC) set to 0011. 3: When operated in the low-speed mode with the PCC set to 0000. 4: Including when the subsystem clock is operated. 5: When operated with the subsystem clock by setting the system clock control register (SCC) to 1011 to stop the main system clock operation. 45 µPD75004, 75006, 75008 AC CHARACTERISTICS (Ta = -40 to +85°C, V DD = 2.7 to 6.0 V) Parameter Symbol Time*1 Conditions w/main system clock MIN. VDD = 4.5 to 6.0 V TYP. MAX. Unit 0.95 64 µs 3.8 64 µs 125 µs CPU Clock Cycle (Minimum Instruction Execution Time = 1 Machine Cycle) tCY TI0 Input Frequency fTI VDD = 4.5 to 6.0 V 0 1 MHz 0 275 kHz TI0 Input High-, LowLevel Widths tTIH, tTIL VDD = 4.5 to 6.0 V 0.48 µs 1.8 µs Interrupt Input High-, Low-Level Widths tINTH, tINTL INT0 *2 µs INT1, 2, 4 10 µs 10 µs RESET Low-Level Width tRSL 10 µs w/subsystem clock 114 KR0-7 *1: The CPU clock (Φ) cycle time (minimum instruction execution time) 122 tCY vs VDD is (with main system clock) 70 determined by the oscillation frequency 64 60 of the connected oscillator, system clock control register (SCC), and processor 6 The figure on the right is cycle time tCY 5 vs. supply voltage VDD characteristics 4 at the main system clock. 2: 2tCY or 128/f X depending on the setting of the interrupt mode register (IM0). Cycle time tCY [µs] clock control register (PCC). Operation guaranteed range 3 2 1 0.5 0 1 2 3 4 Supply voltage VDD [V] 46 5 6 µPD75004, 75006, 75008 SERIAL TRANSFER OPERATION Two-Line and Three-Line Serial I/O Modes (SCK: internal clock output): Parameter SCK Cycle Time SCK High-, Low-Level Widths SI Set-Up Time (vs. SCK ↑) Symbol tKCY1 tKL1 Conditions MIN. VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V MAX. Unit 1600 ns 3800 ns tKCY1/2-50 ns tKH1 tKCY1/2-150 ns tSIK1 150 ns SI Hold Time (vs. SCK ↑ ) tKSI1 SCK ↓→ SO Output Delay Time TYP. tKSO1 400 R = 1 kΩ, C = 100 pF* VDD = 4.5 to 6.0 V ns 0 250 ns 0 1000 ns MAX. Unit TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: external clock input): Parameter SCK Cycle Time SCK High-, Low-Level Widths Symbol tKCY2 tKL2 Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V MIN. TYP. 800 ns 3200 ns 400 ns tKH2 1600 ns SI Set-Up Time (vs. SCK ↑) tSIK2 100 ns SI Hold Time (vs. SCK ↑) tKSI2 400 SCK ↓→ SO Output Delay Time tKSO2 R = 1 kΩ, C = 100 pF* VDD = 4.5 to 6.0 V ns 0 300 ns 0 1000 ns *: R and C are load resistance and load capacitance of the SO output line. 47 µPD75004, 75006, 75008 SBI MODE (SCK: internal clock output (master)): Parameter SCK Cycle Time Symbol tKCY3 Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V MIN. TYP. MAX. Unit 1600 ns 3800 ns SCK High-, Low-Level Widths tKL3 tKH3 SB0, 1 Set-Up Time (vs. SCK ↑ ) tSIK3 SB0, 1 Hold Time (vs. SCK ↑ ) tKSI3 SCK ↓→ SB0, 1 Output Delay Time tKSO3 SCK ↑→ SB0, 1 ↓ tKSB tKCY3 ns SB0,1 ↓→ SCK tSBK tKCY3 ns SB0, 1 Low-Level Width tSBL tKCY3 ns SB0, 1 High-Level Width tSBH tKCY3 ns R = 1 kΩ, C = 100 pF* VDD = 4.5 to 6.0 V tKCY3/2-50 ns tKCY3/2-150 ns 150 ns tKCY3/2 ns 0 250 ns 0 1000 ns SBI MODE (SCK: external clock input (slave)): Parameter Symbol Conditions MIN. TYP. MAX. tKCY4 VDD = 4.5 to 6.0 V SCK High-, Low-Level Widths tKL4 tKH4 VDD = 4.5 to 6.0 V SB0, 1 Set-Up Time (vs. SCK ↑ ) tSIK4 SB0, 1 Hold Time (vs. SCK ↑ ) tKSI4 SCK ↓→ SB0, 1 Output Delay Time tKSO4 SCK ↑→ SB0, 1 ↓ tKSB tKCY4 ns SB0,1 ↓→ SCK ↓ tSBK tKCY4 ns SB0, 1 Low-Level Width tSBL tKCY4 ns SB0, 1 High-Level Width tSBH tKCY4 ns R = 1 kΩ, C = 100 pF* VDD = 4.5 to 6.0 V 800 ns 3200 ns 400 ns 1600 ns 100 ns tKCY4/2 ns 0 300 0 1000 *: R and C are load resistance and load capacitance of the SB0 and SB1 output lines. 48 Unit SCK Cycle Time ns ns µPD75004, 75006, 75008 AC TIMING TEST POINT (excluding X1 and XT1 inputs) 0.8 VDD 0.8 VDD Test points 0.2 VDD 0.2 VDD CLOCK TIMING 1/fX tXL tXH X1 input VDD –0.5V 0.4 V 1/fXT tXTL tXTH XT1 input VDD –0.5V 0.4 V TI0 TIMING 1/fTI tTIL tTIH TI0 49 µPD75004, 75006, 75008 SERIAL TRANSFER TIMING THREE-LINE SERIAL I/O MODE: tKCY1 tKL1 tKH1 SCK tSIK1 SI tKSI1 Input data tKSO1 Output data SO TWO-LINE SERIAL I/O MODE: tKCY2 tKH2 tKL2 SCK tSIK2 SB0,1 tKSO2 50 tKSI2 µPD75004, 75006, 75008 SERIAL TRANSFER TIMING BUS RELEASE SIGNAL TRANSFER: t KCY3,4 tKL3,4 tKH3,4 SCK tKSB tSBL tSBH tSIK3,4 tSBK tKSI3,4 SB0,1 tKSO3,4 COMMAND SIGNAL TRANSFER: tKCY3,4 tKL3,4 tKH3,4 SCK tKSB tSIK3,4 tSBK tKSI3,4 SB0,1 tKSO3,4 INTERRUPT INPUT TIMING: tINTL tINTH INT0, 1, 2, 4 KR0-7 RESET INPUT TIMING: tRSL RESET 51 µPD75004, 75006, 75008 LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE (Ta = –40 to +85°C) Parameter Symbol Data Retention Supply Voltage VDDDR Data Retention Supply Current*1 IDDDR Release Signal Set Time tSREL Oscillation Stabilization tWAIT Conditions MIN. TYP. MAX. Unit 6.0 V 10 µA 2.0 VDDDR = 2.0 V 0.1 µs 0 Released by RESET Wait Time*2 Released by interrupt request 217/fX ms *3 ms *1: Does not include current flowing through internal pull-up resistor 2: The oscillation stabilization wait time is the time during which the CPU is stopped to prevent unstable operation when oscillation is started. 3: Depends on the setting of the basic interval timer mode register (BTM) as follows: BTM3 BTM2 BTM1 BTM0 – 0 0 0 2 20/fXX (approx. 250 ms) – 0 1 1 2 17/fXX (approx. 31.3 ms) – 1 0 1 2 15/fXX (approx. 7.82 ms) – 1 1 1 2 13/fXX (approx. 1.95 ms) DATA RETENTION TIMING WAIT time ( ): fXX = 4.19 MHz (releasing STOP mode by RESET) Internal reset operation HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt) HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT 52 µPD75004, 75006, 75008 11. CHARACTERISTIC CURVES IDD vs VDD (Crystal oscillation) (Ta = 25°C) 5000 Main system clock High-speed mode PCC = 0011 Middle-speed mode PCC = 0010 Low-speed mode PCC = 0000 1000 HALT mode Operating current I DD [ µ A] 500 Subsystem clock* Operation mode 100 50 HALT mode* X1 10 X2 X'tal 4.19 MHz 20 pF 5 XT1 XT2 X'tal 32.768 kHz 330 k Ω 18 pF 18 pF 18 pF 1 0 1 2 3 4 5 6 7 Operating voltage V DD [V] *: Main system clock halts. 53 µPD75004, 75006, 75008 I DD vs V DD (Ceramic oscillation) (Ta = 25°C) 5000 Main system clock High-speed mode PCC = 0011 Middle-speed mode PCC = 0010 Low-speed mode PCC = 0000 1000 HALT mode*1 Operating current I DD [ µ A] 500 Subsystem clock*2 Operation mode 100 50 HALT mode*2 X1 X2 Ceramic oscillator 10 30 pF 5 XT1 X'tal XT2 CSA4.19 MGU 32.768 kHz 330 k Ω 30 pF 18 pF 18 pF 1 0 1 2 3 4 5 6 Operating voltage V DD [V] *1: When compared to crystal oscillation, increased by approximately 10%. 2: Main system clock halts. 54 7 µPD75004, 75006, 75008 I DD vs V DD (Ceramic oscillation) (Ta = 25°C) 5000 Main system clock High-speed mode PCC = 0011 Middle-speed mode PCC = 0010 Low-speed mode PCC = 0000 1000 HALT mode Operating current I DD [ µ A] 500 Subsystem clock* Operation mode 100 50 HALT mode* X1 X2 Ceramic oscillator 10 30 pF 5 XT1 X'tal XT2 CSA2.00MG093 32.768 kHz 330 k Ω 30 pF 18 pF 18 pF 1 0 1 2 3 4 5 6 7 Operating voltage V DD [V] *: Main system clock halts. 55 µPD75004, 75006, 75008 3 I DD vs f x X1 (V DD = 5V, Ta = 25°C) X2 High-speed mode PCC = 0011 Middle-speed mode PCC = 0010 I DD [mA] 2 0.5 (V DD = 3V, Ta = 25°C) I DD vs fx Middle-speed High-speed mode mode PCC = 0010 X1 PCC = 0011 I DD [mA] 0.4 1 Low-speed mode PCC = 0000 0 0.3 0.2 0 1 2 3 4 Low-speed mode PCC = 0000 Main system clock HALT mode 0.1 Main system clock HALT mode 5 1 2 VOL vs I OL (Port 0) (T a = 25°C) 40 40 VDD = 6 V 20 5 ★ V OL vs I OL (Port 2, 6, 7) (T a = 25°C) VDD = 20 6 V VDD = 5 V V DD = 4 V VDD = 3 V VDD = 3 V V DD = 2.7 V V DD = 2.7 V 10 0 4 30 V DD = 4 V VDD = 5 V I OL [mA] I OL [mA] 30 3 fx [MHz] fx [MHz] 10 1 2 3 V OL [V] 56 X2 4 5 0 1 2 3 V OL [V] 4 5 µPD75004, 75006, 75008 V OL vs I OL (Port 4, 5) 40 VDD = 6 V VDD = 5 V V DD = 4 V 30 20 VDD = 3 V (T a = 25°C) 40 I OL [mA] I OL [mA] 30 V OL vs I OL (Port 3) (T a = 25°C) VDD = 6 V VDD = 5 V V DD = 4 V 20 VDD = 3 V V DD = 2.7 V V DD = 2.7 V 10 0 10 1 2 3 4 5 V OL [V] VOH vs IOH V DD = 6 V 1 2 3 4 5 V OL [V] 20 15 0 (T a = 25°C) V DD = 5 V I OH [mA] V DD = 4 V 10 V DD = 3 V 5 0 V DD = 2.7 V 1 2 3 4 5 V DD - V OH [V] 57 µPD75004, 75006, 75008 12. PACKAGE DRAWINGS 42PIN PLASTIC SHRINK DIP (600 mil) 42 22 1 21 A K H G J I L F B D N R M C M NOTES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel. ITEM MILLIMETERS INCHES A 39.13 MAX. 1.541 MAX. B 1.78 MAX. 0.070 MAX. C 1.778 (T.P.) 0.070 (T.P.) D 0.50±0.10 0.020 +0.004 –0.005 F 0.9 MIN. 0.035 MIN. G 3.2±0.3 0.126±0.012 H 0.51 MIN. 0.020 MIN. I 4.31 MAX. 0.170 MAX. J 5.08 MAX. 0.200 MAX. K 15.24 (T.P.) L 13.2 M 0.25 +0.10 –0.05 N 0.17 0.007 R 0~15° 0~15° 0.600 (T.P.) 0.520 0.010 +0.004 –0.003 P42C-70-600A-1 58 µPD75004, 75006, 75008 44 PIN PLASTIC QFP ( ★ 10) A B 23 22 33 34 detail of lead end C D S R Q 12 11 44 1 F G J H I M K M P N L NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 13.6±0.4 0.535 +0.017 –0.016 B 10.0±0.2 0.394 +0.008 –0.009 C 10.0±0.2 0.394 +0.008 –0.009 D 13.6±0.4 0.535 +0.017 –0.016 F 1.0 0.039 G 1.0 0.039 H 0.35±0.10 0.014 +0.004 –0.005 I 0.15 0.006 J 0.8 (T.P.) 0.031 (T.P) K 1.8±0.2 0.071 +0.008 –0.009 L 0.8±0.2 0.031 +0.009 –0.008 M 0.15 +0.10 –0.05 0.006 +0.004 –0.003 N P Q R S 0.10 2.7 0.1±0.1 5°±5° 3.0 MAX. 0.004 0.106 0.004±0.004 5°±5° 0.119 MAX. P44GB-80-3B4-3 59 µPD75004, 75006, 75008 ★ 13. RECOMMENDED SOLDERING CONDITIONS It is recommended that µPD75004, 75006, and 75008 be soldered under the following conditions. For details on the recommended soldering conditions, refer to Information Document "Semiconductor Devices Mounting Manual" (IEI-616). The soldering methods and conditions are not listed here, consult NEC. Table 13-1 Soldering Conditions µ PD75004GB - xxx - 3B4: 44-pin plastic QFP (■ ■ 10 mm) µ PD75006GB - xxx - 3B4: 44-pin plastic QFP (■ ■ 10 mm) µ PD75008GB - xxx - 3B4: 44-pin plastic QFP (■ ■ 10 mm) Soldering Method *: Soldering Conditions Symbol for Recommended Condition Infrared Reflow Package peak temperature: 230°C, time: 30 seconds max. (210°C min.), number of times: 1, number of days: 7 days*, (afterwards, 10 hours of prebaking at 125°C is required.) IR30-107-1 VPS Package peak temperature: 215°C, time: 40 seconds max. (200°C min.), number of times: 1, number of days: 7 days*, (afterwards, 10 hours of prebaking at 125°C is required.) VP15-107-1 Wave Soldering Soldering bath temperature: 260°C max., time: 10 seconds max., number of times: 1, number of days: 7 days*, (afterwards, 10 hours of prebaking at 125°C is required.) pre-heating temperature: 120°C max. (package surface temperature) WS60-00-1 Pin Partial Heating Pin temperature: 300°C max., time: 3 seconds max. (per side) — This means the number of days after unpacking the dry pack. Storage conditions are 25°C and 65% RH max. Caution: Do not use two or more soldering methods in combination (except the pin partial heating method). Table 13-2 Soldering Conditions of Through-Hole Type µPD75004CU - xxx : 42-pin plastic shrink DIP (600 mil) µPD75006CU - xxx : 42-pin plastic shrink DIP (600 mil) µPD75008CU - xxx : 42-pin plastic shrink DIP (600 mil) Soldering Method Soldering Conditions Wave Soldering (Only for lead part) Soldering bath temperature: 260°C max., Time: 10 seconds max. Pin Partial Heating Pin temperature: 260°C max., Time: 10 seconds max. Notice A model that can be soldered under the more stringent conditions (infrared reflow peak temperature: 235°C, number of times: 2, and an extended number of days) is also available. For details, consult NEC. 61 µPD75004, 75006, 75008 APPENDIX A. DEVELOPMENT TOOLS The following development support tools are readily available to support development of systems using µPD75008: Hardware Software IE-75000-R *1 IE-75001-R In-circuit emulator for 75X series IE-75000-R-EM *2 Emulation board for IE-75000-R and IE-75001-R EP-75008CU/GB-R Emulation prove for µPD75004CU/GB, 75006CU/GB, 75008CU/GB PG-1500 PROM programmer PA-75P008CU PROM programmer adapter solely used for µPD75P008CU/GB. It is connected to PG-1500. IE Control Program Host machine TM • PC-9800 series (MS-DOS Ver.3.30 to Ver.5.00A* 3) PG-1500 Controller RA75X Relocatable Assembler • IBM PC/ATTM (PC DOS TM Ver.3.1) *1: Maintenance product 2: Not provided with IE-75001-R. 3: Ver.5.00/5.00A has a task swap function, but this function cannot be used with this function. Remarks: For development tools from other companies, refer to 75X Series Selection Guide (IF-151). 62 µPD75004, 75006, 75008 ★ APPENDIX B. RELATED DOCUMENTS 63 µPD75004, 75006, 75008 [MEMO] 64 µPD75004, 75006, 75008 GENERAL NOTES ON CMOS DEVICES 1 STATIC ELECTRICITY (ALL MOS DEVICES) Exercise care so that MOS devices are not adversely influenced by static electricity while being handled. The insulation of the gates of the MOS device may be destroyed by a strong static charge. Therefore, when transporting or storing the MOS device, use a conductive tray, magazine case, or conductive buffer materials, or the metal case NEC uses for packaging and shipment, and use grounding when assembling the MOS device system. Do not leave the MOS device on a plastic plate and do not touch the pins of the device. Handle boards on which MOS devices are mounted similarly . 2 PROCESSING OF UNUSED PINS (CMOS DEVICES ONLY) Fix the input level of CMOS devices. Unlike bipolar or NMOS devices, if a CMOS device is operated with nothing connected to its input pin, intermediate level input may be generated due to noise, and an inrush current may flow through the device, causing the device to malfunction. Therefore, fix the input level of the device by using a pull-down or pull-up resistor. If there is a possibility that an unused pin serves as an output pin (whose timing is not specified), each pin should be connected to VDD or GND through a resistor. Refer to “Processing of Unused Pins” in the documents of each devices. 3 STATUS BEFORE INITIALIZATION (ALL MOS DEVICES) The initial status of MOS devices is undefined upon power application. Since the characteristics of an MOS device are determined by the quantity of injection at the molecular level, the initial status of the device is not controlled during the production process. The output status of pins, I/O setting, and register contents upon power application are not guaranteed. However, the items defined for reset operation and mode setting are subject to guarantee after the respective operations have been executed. When using a device with a reset function, be sure to reset the device after power application. 65 µPD75004, 75006, 75008 [MEMO] No p art of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties b y or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for uses in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for the applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime system, etc. M4 92.6 MS-DOS is a trademark of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation. 66