DATA SHEET MOS INTEGRATED CIRCUIT µ PD8670A 7400 PIXELS CCD LINEAR IMAGE SENSOR The µ PD8670A is a high sensitive and high-speed CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal. The µ PD8670A is a 2-output type CCD sensor with 2 rows of high-speed charge transfer register, which transfers the photo signal electrons of 7400 pixels separately in odd and even pixels. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for 600 dpi/A3 high-speed digital copiers, multi-function products and so on. FEATURES • Valid photocell : 7400 pixels • Photocell pitch : 4.7 µ m • Photocell size : 4.7 × 4.7 µ m2 • Resolution : 24 dot/mm (600 dpi) A3 (297 × 420 mm) size (shorter side) • Data rate : 44 MHz MAX. (22 MHz/1 output) • Output type : 2 outputs in-phase operation, and out of phase also supported • High sensitivity : 17.0 V/lx•s TYP. (Light source: Daylight color fluorescent lamp) • Peak response wavelength : 550 nm (green) • Low image lag : 1 % MAX. • Drive clock level : CMOS output under +5 V operation • Power supply : +12 V • On-chip circuits : Reset feed-through level clamp circuits : Voltage amplifiers ORDERING INFORMATION Part Number Package µ PD8670ACY CCD linear image sensor 32-pin plastic DIP (10.16 mm (400)) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S17147EJ1V0DS00 (1st edition) Date Published August 2004 NS CP (K) Printed in Japan 2004 µ PD8670A DIFFERENCE BETWEEN µ PD8670ACY AND µ PD3747D Part Item µ PD8670ACY µ PD3747D Referential Page Features Output type 2 outputs out of phase or in phase 2 outputs in phase only TYP. 17 V/lx•s TYP. 19 V/lx•s 32-pin plastic DIP 22-pin ceramic DIP (CERDIP) φ CP1, φ CP2 separated, φ CP common, 4 φ R1, φ R2 separated, φ R common, 3 φ 2L1, φ 2L2 separated φ 2L common (Output: in/out of phase) (Output: in phase) 2SA1206, 2SC1842 2SA1005, 2SC945 0 to +60°C –25 to +55°C Storage temperature –40 to +70°C –40 to +100°C Each clock amplitude Addition of specifications – Sensitivity (Daylight 1 color fluorescent lamp) Ordering information Package Pin configuration Input clock Block diagram Application circuit example Equivalent circuit Tr. Absolute maximum Operating ambient ratings temperature Recommended operating condition 21 5 (from 4.5 V to 5.8 V) Electrical ADS, DSNU, DR1, characteristics DR2 RF RFTN Change of specifications – TYP. 17 V/lx•s TYP. 19 V/lx•s Addition of PRFTN, RFTN1, Only RFTN 6 RFTN2 TYP. 13 ns td TYP. 14 ns Addition of min. max. Input pin capacitance σ bit, σ line, σ shot Addition of condition (t6) – Capacitance Change of specification – 7 – 8, 9 MIN. 5 ns MIN. 0 ns 12, 14 Addition of note Timing chart Addition of out-of-phase Operation timing chart t6 t10 t13, t16, t17 Close point – Definitions VOS, RFTN Recommended Partial heating method MIN. 0 ns MIN. t3 MAX. 10000 ns – 14 Change of specifications – 15 Additional item – 19 350°C or blow, 3 seconds or less 300°C or blow, 3 seconds or less 24 23 soldering condition Package drawing Package 32-pin plastic DIP 22-pin ceramic DIP (CERDIP) Cap Plastic cap 0.7t Glass cap 0.7t From CCD to bottom 2.45 ± 0.3 mm 2.38 ± 0.3 mm (2.0) mm (1.95) mm of package From CCD to top of cap Remark 2 TA = +25°C, VOD = 12 V Data Sheet S17147EJ1V0DS µ PD8670A BLOCK DIAGRAM VOUT2 (Even) GND φ CP2 φ R2 φ 2L2 φ 22 φ 12 31 30 29 28 24 23 32 CCD analog shift register ··· D12 D7 S7400 ··· S7399 S2 S1 ··· D6 D1 ··· OB96 OB1 Transfer gate 22 φ TG Transfer gate VOUT1 (Odd) 1 CCD analog shift register 2 3 4 5 9 10 11 VOD φ CP1 φ R1 φ 2L1 φ 11 φ 21 GND Data Sheet S17147EJ1V0DS 3 µ PD8670A PIN CONFIGURATION (Top View) CCD linear image sensor 32-pin plastic DIP (10.16 mm (400)) • µ PD8670ACY Output signal 1 (Odd) VOUT1 1 32 VOUT2 Output signal 2 (Even) Output drain voltage VOD 2 31 GND Ground Reset feed-through level clamp clock 1 φ CP1 3 30 φ CP2 Reset feed-through level clamp clock 2 Reset gate clock 1 φ R1 4 29 φ R2 Reset gate clock 2 Last stage shift register clock 1 φ 2L1 5 28 φ 2L2 Last stage shift register clock 2 Internal connection IC 6 27 IC Internal connection Internal connection IC 7 26 IC Internal connection No connection NC 8 25 NC No connection Shift register clock 1-1 φ 11 9 24 φ 22 Shift register clock 2-2 Shift register clock 2-1 φ 21 10 23 φ 12 Shift register clock 1-2 Ground GND 11 22 φ TG Transfer gate clock Internal connection IC 12 21 IC Internal connection Internal connection IC 13 20 IC Internal connection No connection NC 14 19 NC No connection No connection NC 15 18 NC No connection No connection NC 16 17 NC No connection Cautions 1. Leave pins 6, 7, 12, 13, 20, 21, 26 and 27 (IC) unconnected. 2. Connect the No connection pins (NC) to GND. PHOTOCELL STRUCTURE DIAGRAM 3.2 µ m 4.7 µ m 1.5 µ m Aluminum shield 4 Data Sheet S17147EJ1V0DS Channel stopper µ PD8670A ABSOLUTE MAXIMUM RATINGS (TA = +25°C) Parameter Symbol Ratings Unit Output drain voltage VOD −0.3 to +14.0 V Shift register clock voltage Vφ 1, Vφ 2 −0.3 to +8.0 V Last stage shift register clock voltage Vφ 2L −0.3 to +8.0 V Reset gate clock voltage Vφ R −0.3 to +8.0 V Transfer gate clock voltage Vφ TG −0.3 to +8.0 V Vφ CP Reset feed-through level clamp clock voltage Operating ambient temperature Note Storage temperature −0.3 to +8.0 V TA 0 to +60 °C Tstg −40 to +70 °C Note Use at the condition without dew condensation. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. RECOMMENDED OPERATING CONDITIONS (TA = +25°C) Parameter Symbol Conditions MIN. TYP. MAX. Unit 11.4 12.0 12.6 V Output drain voltage VOD Shift register clock high level Vφ 1H, Vφ 2H 4.5 5.0 5.5 V Shift register clock low level Vφ 1L, Vφ 2L −0.3 0 +0.5 V Last stage shift register clock high level Vφ 2LH 4.5 5.0 5.5 V Last stage shift register clock low level Vφ 2LL −0.3 0 +0.5 V Reset gate clock high level Vφ RH 4.5 5.0 5.5 V Reset gate clock low level Vφ RL −0.3 0 +0.5 V Reset feed-through level clamp clock high level Vφ CPH 4.5 5.0 5.5 V Reset feed-through level clamp clock low level Vφ CPL −0.3 0 +0.5 V Transfer gate clock high level Vφ TGH 4.5 5.0 5.5 V Transfer gate clock low level Vφ TGL −0.3 0 +0.5 V Shift register clock amplitude Vφ 1_pp, f < 10 MHz/ch 4.0 5.0 5.8 V Vφ 2_pp f ≥ 10 MHz/ch 4.5 5.0 5.8 V Last stage shift register clock amplitude Vφ 2L_pp 4.5 5.0 5.8 V Reset gate clock amplitude Vφ R_pp 4.5 5.0 5.8 V Reset feed-through level clamp clock amplitude Vφ CP_pp 4.5 5.0 5.8 V Transfer gate clock amplitude Vφ TG_pp 4.5 5.0 5.8 V Data rate 2fφ R 1 2 44 MHz Data Sheet S17147EJ1V0DS 5 µ PD8670A ELECTRICAL CHARACTERISTICS TA = +25°C, VOD = 12 V, fφ R = 1 MHz, data rate = 2 MHz, storage time = 10 ms, input signal clock = 5 Vp-p, light source : 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm) Parameter Symbol Saturation voltage Test Conditions Vsat MIN. TYP. MAX. Unit 1.5 2.0 − V Saturation exposure SE Daylight color fluorescent lamp − 0.10 − lx•s Photo response non-uniformity PRNU VOUT = 500 mV − 5.0 10.0 % Average dark signal ADS Light shielding − 1.0 6.0 mV Dark signal non-uniformity DSNU Light shielding − 16.0 28.0 mV Power consumption PW − 350 420 mW Output impedance ZO − 0.2 0.3 kΩ Response RF Daylight color fluorescent lamp 13.6 17.0 20.4 V/lx•s IL VOUT = 500 mV − 0.5 1.0 % 3.7 4.7 5.7 V td VOUT = 500 mV 11.0 13.0 15.0 ns Total transfer efficiency TTE VOUT = 1 V, data rate = 44 MHz 94 98 − % Register imbalance RI VOUT = 500 mV 0 1.0 4.0 % − 550 − nm DR1 Vsat/DSNU − 125 − times DR2 Vsat/σ bit, t6 ≥ 20 ns − 1000 − times PRFTN Light shielding, t4 = 5 ns − +0.4 − V RFTN1 −1.0 −0.4 +0.2 V RFTN2 −0.3 +0.2 +0.7 V Image lag Offset level Note 1 Output fall delay time VOS Note 2 Response peak Dynamic range Reset feed-through noise Random noise Note 1 σ bit σ line Light shielding, t6 = 5 ns − 2.6 − mV bit clamp mode t6 ≥ 20 ns − 2.0 − mV Light shielding, t6 ≥ 5 ns − 8.0 − mV t6 ≥ 5 ns − 10.0 − mV line clamp mode Shot noise σ shot VOUT = 500 mV, bit clamp mode Notes 1. Refer to 13 and 14 of DEFINITION OF CHARACTERISTIC ITEMS. 2. When the fall time of φ 2L (t2’) is the TYP. value (refer to TIMING CHART 5, 6). Note that VOUT1 and VOUT2 are the outputs of the two steps of emitter-follower shown in APPLICATION CIRCUIT EXAMPLE. 6 Data Sheet S17147EJ1V0DS µ PD8670A INPUT PIN CAPACITANCE (TA = +25°C, VOD = 12 V) Parameter Symbol Note φ1 Shift register clock pin capacitance 1 C Shift register clock pin capacitance 2 Cφ 2Note Last stage shift register clock pin capacitance Cφ L Reset gate clock pin capacitance Cφ R Reset feed-through level clamp clock pin capacitance Cφ CP Transfer gate clock pin capacitance Cφ TG Pin name Pin No. MIN. TYP. MAX. Unit φ 11 9 225 250 275 pF φ 12 23 200 220 240 pF φ 21 10 200 220 240 pF φ 22 24 225 250 275 pF φ 2L1 5 4 5 6 pF φ 2L2 28 4 5 6 pF φ R1 4 4 5 6 pF φ R2 29 4 5 6 pF φ CP1 3 7 8 9 pF φ CP2 30 7 8 9 pF φ TG 22 240 270 300 pF Note Cφ 1, Cφ 2 are equivalent capacitance with driving device, including the co-capacitance between φ 1 and φ 2. Remark Pins 9 and 23 (φ 11 and φ 12), Pins 10 and 24 (φ 21 and φ 22) aren't each connected inside of the device. Data Sheet S17147EJ1V0DS 7 8 TIMING CHART 1 (Bit clamp mode, Out of phase operation) φ TG φ 11 φ 21 φ 2L1 φ R1 7541 7539 7537 7535 7533 7531 137 135 133 131 129 127 125 35 33 31 29 5 3 VOUT1 φ 12 φ 22 φ 2L2 φ R2 7542 7540 7538 7536 7534 7532 138 136 134 132 130 128 126 36 34 32 30 6 4 φ CP2 2 Data Sheet S17147EJ1V0DS 1 φ CP1 VOUT2 Dummy cell (32 pixels) Optical black (96 pixels) Valid photocells (7400 pixels) Invalid photocell (6 pixels) Note Set the φ R1, φ R2, φ CP1 and φ CP2 to low level during this period. Invalid photocell (6 pixels) µ PD8670A Note TIMING CHART 2 (Line clamp mode, Out of phase operation) φ TG φ 11 φ 21 φ 2L1 φ R1 7541 7539 7537 7535 7533 7531 137 135 133 131 129 127 125 35 33 31 29 5 3 Data Sheet S17147EJ1V0DS 1 φ CP1 VOUT1 φ 12 φ 22 φ 2L2 φ R2 7542 7540 7538 7536 7534 7532 138 136 134 132 130 128 126 36 34 32 30 6 4 2 φ CP2 VOUT2 Dummy cell (32 pixels) Optical black (96 pixels) Valid photocells (7400 pixels) Invalid photocell (6 pixels) 9 Note Set the φ R1, φ R2, φ CP1 and φ CP2 to low level during this period. Invalid photocell (6 pixels) µ PD8670A Note 10 TIMING CHART 3 (Bit clamp mode, In phase operation) φ TG φ 11, φ 12 φ 21, φ 22 φ 2L1, φ 2L2 127 129 131 133 135 137 7531 7533 7535 7537 7539 7541 128 130 132 134 136 138 7532 7534 7536 7538 7540 7542 33 34 125 31 32 126 29 30 35 5 6 36 3 4 1 φ CP1, φ CP2 VOUT1 2 Data Sheet S17147EJ1V0DS φ R1, φ R2 VOUT2 Note Dummy cell (32 pixels) Optical black (96 pixels) Valid photocells (7400 pixels) Note Set the φ R1, φ R2, φ CP1 and φ CP2 to low level during this period. Invalid photocell (6 pixels) µ PD8670A Invalid photocell (6 pixels) TIMING CHART 4 (Line clamp mode, In phase operation) φ TG φ 11, φ 12 φ 21, φ 22 φ 2L1, φ 2L2 127 129 131 133 135 137 7531 7533 7535 7537 7539 7541 128 130 132 134 136 138 7532 7534 7536 7538 7540 7542 33 34 125 31 32 126 29 30 35 5 6 36 3 4 1 φ CP1, φ CP2 VOUT1 2 Data Sheet S17147EJ1V0DS φ R1, φ R2 VOUT2 Note Dummy cell (32 pixels) Optical black (96 pixels) Valid photocells (7400 pixels) 11 Note Set the φ R1, φ R2, φ CP1 and φ CP2 to low level during this period. Invalid photocell (6 pixels) µ PD8670A Invalid photocell (6 pixels) µ PD8670A TIMING CHART 5 (Bit clamp mode) φ 11 φ 21 φ 2L1 t1 t2 t1' t2' 90% 10% 90% 10% 90% 10% t4 t3 t5 t6 φ R1 90% 10% t10 t8 t7 t9 t11 90% φ CP1 10% td VOUT1 VOS 10% Symbol MIN. TYP. MAX. Unit t1, t2 0 50 − ns t1’, t2’ 0 5 − ns t3 10 125 − ns t4, t5 0 5 − ns t6 5 125 − ns t7 5 125 − ns t8, t9 0 5 − ns t10 0 125 − ns t11 0 250 − ns Caution This shows timing chart of VOUT1 side (φ 11, φ 21, φ 2L1, φ R1, φ CP1, VOUT1). The timing chart of VOUT2 side (φ 12, φ 22, φ 2L2, φ R2, φ CP2, VOUT2) is equal. 12 Data Sheet S17147EJ1V0DS µ PD8670A TIMING CHART 6 (Line clamp mode) φ 11 φ 21 φ 2L1 t1 t2 t1' t2' 90% 10% 90% 10% 90% 10% t4 t3 t5 φ R1 φ CP1 t12 90% 10% "L" td VOUT1 VOS 10% Symbol MIN. TYP. MAX. Unit t1, t2 0 50 − ns t1’, t2’ 0 5 − ns t3 10 125 − ns t4, t5 0 5 − ns t12 5 250 − ns Caution This shows timing chart of VOUT1 side (φ 11, φ 21, φ 2L1, φ R1, φ CP1, VOUT1). The timing chart of VOUT2 side (φ 12, φ 22, φ 2L2, φ R2, φ CP2, VOUT2) is equal. Data Sheet S17147EJ1V0DS 13 µ PD8670A TIMING CHART 7 (Bit clamp mode, Line clamp mode) t14 t15 t13 90% φ TG 10% t16 φ 11 90% 90% φ 21, φ 2L1 t17 t4 t3 t5 t6 90% φ R1 10% t10 t8 t7 t9 t11 90% φ CP1 10% Note Note Set the φ R and φ CP to low level during this period. Symbol MIN. TYP. MAX. Unit t3 10 125 − ns t4, t5 0 5 − ns t6 5 125 − ns t7 5 125 − ns t8, t9 0 5 − ns t10 0 125 − ns t11 0 250 − ns t13 1000 1500 10000 ns t14, t15 0 50 − ns t16, t17 200 300 10000 ns Caution This shows timing chart of VOUT1 side (φ 11, φ 21, φ 2L1, φ R1, φ CP1, VOUT1). The timing chart of VOUT2 side (φ 12, φ 22, φ 2L2, φ R2, φ CP2, VOUT2) is equal. 14 Data Sheet S17147EJ1V0DS µ PD8670A φ 11, φ 21 cross points φ 11, φ 2L1 cross points φ 11 φ 11 1.5 V or more 1.5 V or more 1.5 V or more φ 21 φ 2L1 φ 12, φ 22 cross points 0 V or more φ 12, φ 2L2 cross points φ 12 φ 12 1.5 V or more 1.5 V or more φ 22 1.5 V or more φ 2L2 0 V or more Remark Adjust cross points of (φ 11, φ 21), (φ 11, φ 2L1), (φ 12, φ 22) and (φ 12, φ 2L2) with input resistance of each pin. φ 11, φ 12, φ 21, φ 22, φ 2L1, φ 2L2 clock width 0 ns or more φ 11, φ 12, φ 21, φ 22, φ 2L1, φ 2L2 4.5 V 0.5 V 0 ns or more Data Sheet S17147EJ1V0DS 15 µ PD8670A DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage : Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure : SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity : PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula. PRNU (%) = ∆x × 100 x ∆x: maximum of xj − x 7400 Σx x= j j=1 7400 xj: Output voltage of valid pixel number j VOUT Register dark DC level x ∆x 4. Average dark signal : ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula. 7400 Σd j ADS (mV) = j=1 7400 dj: Dark signal of valid pixel number j 16 Data Sheet S17147EJ1V0DS µ PD8670A 5. Dark signal non-uniformity : DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV): maximum of dj − ADS j = 1 to 7400 dj: Dark signal of valid pixel number j VOUT ADS Register dark DC level DSNU 6. Output impedance : ZO Impedance of the output pins viewed from outside. 7. Response : R Output voltage divided by exposure (lx•s). Note that the response varies with a light source (spectral characteristic). 8. Image lag : IL The rate between the last output voltage and the next one after read out the data of a line. φ TG Light ON OFF VOUT V1 VOUT IL (%) = V1 × 100 VOUT 9. Total transfer efficiency : TTE The total transfer rate of CCD analog shift register. This is calculated by the following formula, it is difined by each output. TTE (%) = (1 − Vb / average output of all the valid pixels) × 100 Vb Va−1 : The last pixel output − 1 (Odd pixel: 7537th pixel) Va : The last pixel output (Odd pixel: 7539th pixel) Vb : The spilt pixel output (Odd pixel: 7541st pixel) Va−1 Va Data Sheet S17147EJ1V0DS 17 µ PD8670A 10. Register imbalance : RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels. n 2 2 n ∑ (V2j – 1 – V2j) j=1 RI (%) = × 100 n 1 n ∑ Vj j=1 n : Number of valid pixels Vj : Output voltage of each pixel 11. Random noise : σ Random noise σ is defined as the standard deviation of a valid pixel output signal with 100 times (= 100 lines) data sampling at dark (light shielding). 100 Σ (V – V) i σ (mV) = i=1 100 2 , V= 1 100 ΣV i 100 i = 1 Vi : A valid pixel output signal among all of the valid pixels VOUT V1 line 1 V2 line 2 … … V100 line 100 This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling). 12. Shot noise : σ shot Shot noise is defined as the standard deviation of a valid pixel output signal with 100 times (= 100 lines) data sampling in the light. This includes the random noise. The formula is the same with that of random noise. 18 Data Sheet S17147EJ1V0DS µ PD8670A 13. Offset level : VOS DC level of output signal is defined as follows. 14. Reset feed-through noise and peak reset feed-through noise : RFTN and PRFTN RTFN is switching noise of φ R and φ CP. Reset feed-through noise (RFTN) and peak of RFTN (PRFTN) are defined as follows. <1> Bit clamp operation 2L1 φ R1 φ CP1 RFTN2 VOUT1 PRFTN RFTN1 VOS Caution This shows timing of VOUT1 side (φ 2L1, φ R1, φ CP1, VOUT1). The definition of VOUT2 side (φ 2L2, φ R2, φ CP2, VOUT2) is equal. <2> Line clamp operation φ 2L1 φ R1 φ CP1 VOUT1 "L" PRFTN RFTN1 VOS Caution This shows timing of VOUT1 side (φ 2L1, φ R1, φ CP1, VOUT1). The definition of VOUT2 side (φ 2L2, φ R2, φ CP2, VOUT2) is equal. Data Sheet S17147EJ1V0DS 19 µ PD8670A STANDARD CHARACTERISTIC CURVES (Reference Value) DARK OUTPUT TEMPERATURE CHARACTERISTIC STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25°C) 2 8 4 Relative Output Voltage Relative Output Voltage 1 2 1 0.5 0.2 0.25 0.1 0.1 0 10 20 30 40 1 50 5 10 Storage Time (ms) Operating Ambient Temperature TA (°C) TOTAL SPECTRAL RESPONSE CHARACTERISTIC (without infrared cut filter and heat absorbing filter) (TA = +25°C) 100 Response Ratio (%) 80 60 40 20 0 400 600 800 Wavelength (nm) 20 Data Sheet S17147EJ1V0DS 1000 1200 µ PD8670A APPLICATION CIRCUIT EXAMPLE +12 V µ PD8670A +5 V B1 1 2 10 µ F/16 V 0.1 µ F φ CP1 φ R1 φ 2L1 3 φ CP1 47 Ω 4 φ R1 47 Ω 5 7 8 φ 21 VOD 47 Ω 6 φ 11 VOUT1 2Ω 2Ω 9 10 11 12 13 14 15 16 φ 2L1 0.1 µ F 47 µ F/25 V VOUT2 GND 32 B2 31 φ CP2 30 47 Ω φ R2 29 47 Ω 28 47 Ω φ 2L2 IC IC IC IC NC NC φ 11 φ 22 24 2Ω 2Ω GND φ TG 22 IC NC NC NC NC NC NC φ R2 φ 2L2 25 23 IC φ CP2 26 φ 12 IC 0.1 µ F 10 µ F/16 V 27 φ 21 IC +5 V 21 10 Ω φ 22 φ 12 φ TG 20 19 18 17 Cautions 1. Leave pins 6, 7, 12, 13, 20, 21, 26 and 27 (IC) unconnected. 2. Connect the No connection pins (NC) to GND. Remark The inverters shown in the above application circuit example are the 74AC04. Data Sheet S17147EJ1V0DS 21 µ PD8670A B1, B2 EQUIVALENT CIRCUIT +12 V 47 µ F/25 V 4.7 kΩ 110 Ω CCD VOUT 47 Ω + 2SC1842 2SA1206 Output 1 kΩ 22 Data Sheet S17147EJ1V0DS µ PD8670A PACKAGE DRAWING µ PD8670CY, µ PD8670ACY CCD LINEAR IMAGE SENSOR 32-PIN PLASTIC DIP (10.16 mm (400) ) (Unit : mm) 55.2±0.5 54.8±0.5 1st valid pixel 3.2±0.3 1 9.05±0.3 9.25±0.3 17 32 16 1 46.7 4 2.0 12.6±0.5 4 4.1±0.5 4.55±0.5 1.02±0.15 10.16±0.20 (2.0) 2 2.45±0.3 0.46±0.1 2.54±0.25 (5.42) 4.21±0.5 10.16 +0.70 −0.20 3 0.25±0.05 Name Dimensions Refractive index Plastic cap 52.2×6.4×0.8 (0.7 5) 1.5 1 1st valid pixel The center of the pin1 2 The surface of the CCD chip The top of the cap 3 The bottom of the package The surface of the CCD chip 4 Mirror finishied surface 5 Thickness of mirror finished surface 32C-1CCD-PKG10-2 Data Sheet S17147EJ1V0DS 23 µ PD8670A RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. Type of Through-hole Device µ PD8670ACY : CCD linear image sensor 32-pin plastic DIP (10.16 mm (400)) Process Partial heating method Conditions Pin temperature : 350°C or below, Heat time : 3 seconds or less (per pin) Cautions 1. During assembly care should be taken to prevent solder or flux from contacting the plastic cap. The optical characteristics could be degraded by such contact. 2. Soldering by the solder flow method may have deleterious effects on prevention of plastic cap soiling and heat resistance. So the method cannot be guaranteed. 24 Data Sheet S17147EJ1V0DS µ PD8670A NOTES ON HANDLING THE PACKAGES 1 DUST AND DIRT PROTECTING The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. Don’t either touch plastic cap surface by hand or have any object come in contact with plastic cap surface. Should dirt stick to a plastic cap surface, blow it off with an air blower. For dirt stuck through electricity ionized air is recommended. And if the plastic cap surface is grease stained, clean with our recommended solvents. CLEANING THE PLASTIC CAP Care should be taken when cleaning the surface to prevent scratches. We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is recommended that a clean surface or cloth be used. RECOMMENDED SOLVENTS The following are the recommended solvents for cleaning the CCD plastic cap. Use of solvents other than these could result in optical or physical degradation in the plastic cap. Please consult your sales office when considering an alternative solvent. Solvents Ethyl Alcohol Methyl Alcohol Isopropyl Alcohol N-methyl Pyrrolidone Symbol EtOH MeOH IPA NMP 2 MOUNTING OF THE PACKAGE The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't have any object come in contact with plastic cap. You should not reform the lead frame. We recommended to use a IC-inserter when you assemble to PCB. Also, be care that the any of the following can cause the package to crack or dust to be generated. 1. Applying heat to the external leads for an extended period of time with soldering iron. 2. Applying repetitive bending stress to the external leads. 3. Rapid cooling or heating 3 OPERATE AND STORAGE ENVIRONMENTS Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid storage or usage in such conditions. Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the devices are transported from a low-temperature environment to a high-temperature environment. Avoid such rapid temperature changes. For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E) 4 ELECTROSTATIC BREAKDOWN CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes detected. Before handling be sure to take the following protective measures. 1. 2. 3. 4. 5. 6. Ground the tools such as soldering iron, radio cutting pliers of or pincer. Install a conductive mat or on the floor or working table to prevent the generation of static electricity. Either handle bare handed or use non-chargeable gloves, clothes or material. Ionized air is recommended for discharge when handling CCD image sensor. For the shipment of mounted substrates, use box treated for prevention of static charges. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 MΩ. Data Sheet S17147EJ1V0DS 25 µ PD8670A [ NOTE ] 26 Data Sheet S17147EJ1V0DS µ PD8670A NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Data Sheet S17147EJ1V0DS 27 µ PD8670A • The information in this document is current as of August, 2004. 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(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1