DATA SHEET MOS INTEGRATED CIRCUIT µPD3719 10600 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR The µPD3719 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The µPD3719 has 3 rows of 10600 pixels, and each row has a single-sided readout type of charge transfer register. It has reset feed-through level clamp circuits and voltage amplifiers. Moreover, a large dynamic range is realized by using a large saturation voltage and a low-noise amplifier. Therefore, it is suitable for 1200 dpi/A4 professional color image scanners and so on. FEATURES • Valid photocell : 10600 pixels × 3 • Photocell's pitch : 7 µm • Line spacing : 70 µm (10 lines) Red line-Green line, Green line-Blue line • Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 107 lx•hour) • Resolution : 48 dot/mm A4 (210 × 297 mm) size (shorter side) 1200 dpi US letter (8.5” × 11”) size (shorter side) • Drive clock level : CMOS output under 5 V operation • Data rate : 2 MHz MAX. • Power supply : +15 V • On-chip circuits : Reset feed-through level clamp circuits Voltage amplifiers ORDERING INFORMATION Part Number Package µPD3719D CCD linear image sensor 36-pin ceramic DIP (600 mil) The information in this document is subject to change without notice. Document No. S13492EJ1V0DS00(1st edition) Date published September 1998 N CP(K) Printed in Japan © 1998 µPD3719 BLOCK DIAGRAM 34 32 15 25 24 ······ Photocell (Blue) D67 3 D66 31 D65 φ1 S10600 φ2 S10599 GND S2 GND S1 GND D64 GND D14 φ CLB Transfer gate VOUT1 33 (Blue) 23 φ TG 21 GND 14 GND D67 D66 D65 S10600 Photocell (Green) S10599 S2 S1 D64 D14 ······ Transfer gate D67 D66 D65 S10600 Photocell (Red) S10599 S2 S1 ······ D64 D14 CCD analog shift register Transfer gate 2 GND CCD analog shift register VOUT2 (Green) 35 VOUT3 (Red) 22 CCD analog shift register 2 4 5 6 12 13 VOD φ RB VRD φ2 φ1 µPD3719 PIN CONFIGURATION (Top View) CCD linear image sensor 36-pin ceramic DIP (600 mil) 36 NC No connection Output signal 3 (Red) VOUT3 2 35 VOUT2 Output signal 2 (Green) Ground GND 3 34 GND Ground Output drain voltage VOD 4 33 VOUT1 Output signal 1 (Blue) Reset gate clock φ RB 5 32 GND Ground Reset drain voltage VRD 6 31 φ CLB Reset feed-through level clamp clock No connection NC 7 30 NC No connection No connection NC 8 29 NC No connection No connection NC 9 28 NC No connection No connection NC 10 27 NC No connection No connection NC 11 26 NC No connection Shift register clock 2 φ2 12 25 φ2 Shift register clock 2 Shift register clock 1 φ1 13 24 φ1 Shift register clock 1 Ground GND 14 23 φ TG Transfer gate clock Ground GND 15 22 GND Ground No connection NC 16 21 GND Ground No connection NC 17 20 NC No connection No connection NC 18 19 NC No connection Blue 10600 Green 10600 Red 10600 1 1 1 NC 1 No connection 3 µPD3719 PHOTOCELL STRUCTURE DIAGRAM PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing) 7 µm 4 µm 10 lines (70 µm) 3 µm 7 µm 7 µm 4 Green photocell array 10 lines (70 µm) Channel stopper 7 µm Aluminum shield Blue photocell array Red photocell array µPD3719 ABSOLUTE MAXIMUM RATINGS (TA = +25 °C) Parameter Symbol Ratings Unit Output drain voltage VOD –0.3 to +16 V Reset drain voltage VRD –0.3 to +16 V Shift register clock voltage V φ1 , V φ2 –0.3 to +8 V Reset gate clock voltage VφRB –0.3 to +8 V Reset feed-through level clamp clock voltage VφCLB –0.3 to +8 V Transfer gate clock voltage VφTG –0.3 to +8 V Operating ambient temperature TA –25 to +60 °C Storage temperature Tstg –40 to +100 °C Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently. RECOMMENDED OPERATING CONDITIONS (TA = +25 °C) Parameter Symbol MIN. TYP. MAX. Unit Output drain voltage VOD 14.0 15.0 16.0 V Reset drain voltage VRD 14.0 VOD VOD V Shift register clock high level Vφ1H, Vφ2H 4.5 5.0 5.5 V Shift register clock low level Vφ1L, Vφ2L –0.3 0 +0.5 V Reset gate clock high level VφRBH 4.5 5.0 5.5 V Reset gate clock low level VφRBL –0.3 0 +0.5 V Reset feed-through level clamp clock high level VφCLBH 4.5 5.0 5.5 V Reset feed-through level clamp clock low level VφCLBL –0.3 0 +0.5 V Transfer gate clock high level VφTGH 4.5 Vφ1HNote Vφ1HNote V Transfer gate clock low level VφTGL –0.3 0 +0.3 V Data rate fφRB – 1 2 MHz Note When Transfer gate clock high level (VφTGH) is higher than Shift register clock high level (Vφ1H), Image lag can increase. 5 µPD3719 ELECTRICAL CHARACTERISTICS TA = +25 °C, VOD = 15 V, VRD = 15 V, data rate (fφRB) = 2 MHz, storage time = 5.5 ms, light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1mm), input signal clock = 5 Vp-p Parameter Symbol Saturation voltage Test Conditions Vsat Saturation exposure – V SEG 0.57 lx•s Blue SEB 0.94 lx•s Dark signal non-uniformity DSNU Power consumption Output impedance 6 20 % Light shielding 0.8 3.0 mV Light shielding 1.5 5.0 mV PW 400 600 mW ZO 0.5 1 kΩ Red RR 6.8 9.7 12.6 V/lx•s Green RG 6.2 8.8 11.4 V/lx•s Blue RB 3.8 5.3 6.8 V/lx•s 2.0 5.0 % 10.8 12.8 V Image lag IL Note1 VOUT = 2.5 V VOS Note2 8.8 70 ns 98 % Red 630 nm Green 540 nm Blue 460 nm Total transfer efficiency Dynamic range Random noise 5.0 Green ADS Reset feed-through noise 4.0 lx•s Average dark signal Response peak Unit 0.52 VOUT = 2.5 V Output fall delay time MAX. SER PRNU Offset level TYP. Red Photo response non-uniformity Response MIN. Note1 td VOUT = 2.5 V TTE VOUT = 2.5 V 92 DR1 Vsat /DSNU 3333 times DR2 Vsat /σ 10000 times RFTN Light shielding 0 1500 2500 mV σ Light shielding – 0.5 – mV Notes 1. Refer to TIMING CHART 2. 2. When the fall time of φ1 (t1) is the TYP. value (refer to TIMING CHART 2). 6 µPD3719 INPUT PIN CAPACITANCE (TA = +25 °C, VOD = VRD = 15 V) Parameter Shift register clock pin capacitance 1 Shift register clock pin capacitance 2 Symbol C φ1 C φ2 Pin name φ1 φ2 Pin No. MIN. TYP. MAX. Unit 13 1600 pF 24 1600 pF 12 1600 pF 25 1600 pF Reset gate clock pin capacitance CφRB φRB 5 15 pF Reset feed-through level clamp clock pin capacitance CφCLB φCLB 31 15 pF Transfer gate clock pin capacitance CφTG φTG 23 200 pF Remark Pins 13 and 24 (φ1), 12 and 25 (φ2) are each connected inside of the device. 7 φ TG φ1 φ2 φ RB φ CLB Note 61 62 63 64 65 66 10663 10664 10665 10666 10667 10668 10669 Note 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 8 TIMING CHART 1 (for each color) VOUT1 to VOUT3 Optical black (49 pixels) Valid photocell (10600 pixels) Invalid photocell (2 pixels) Note Invalid photocell (3 pixels) Input the φRB and φCLB pulses continuously during this period, too. µPD3719 TIMING CHART 2 (for each color) t1 90 % φ1 10 % 90 % φ2 10 % t5 φ RB t3 t6 t4 90 % 10 % t10 φ CLB t2 t8 t7 t9 t11 90 % 10 % td RFTN VOUT1 to VOUT3 VOS 10 % µPD3719 9 µPD3719 φTG, φ1, φ2 TIMING CHART t12 t14 t13 90 % φTG 10 % t16 t15 90 % φ1 φ2 Symbol Remark MIN. TYP. MAX. Unit t1, t2 0 25 — ns t3 30 50 — ns t4 70 150 — ns t5, t6 0 25 — ns t7 30 75 — ns t8, t9 0 25 — ns t10 10 20 — ns t11 5 10 — ns t12, t13 0 50 — ns t14 3000 10000 — ns t15, t16 900 1000 — ns TYP. is an example of at 1 MHz data rate (fφRB) operation. φ1, φ2 cross points φ1 φ2 Remark 10 2 V or more 2 V or more Adjust cross points of φ1 and φ2 with input resistance of each pin. µPD3719 DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage: Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure: SE Product of intensity of illumination (IX) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity: PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula. PRNU (%) = ∆x × 100 x ∆x : maximum of xj − x 10600 Σx j x= j=1 10600 xj : Output voltage of valid pixel number j VOUT Register Dark DC level 4. x ∆x Average dark signal: ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula. 10600 d Σ j=1 j ADS (mV) = 10600 dj : Dark signal of valid pixel number j 5. Dark signal non-uniformity: DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV) : maximum of dj − ADS j = 1 to 10600 dj : Dark signal of valid pixel number j VOUT ADS Register Dark DC level DSNU 11 µPD3719 6. Output impedance: ZO Impedance of the output pins viewed from outside. 7. Response: R Output voltage divided by exposure (Ix•s). Note that the response varies with a light source (spectral characteristic). 8. Image Lag: IL The rate between the last output voltage and the next one after read out the data of a line. φTG ON Light OFF VOUT V1 VOUT V1 IL (%) = 9. VOUT ×100 Random noise: σ Random noise σ is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). 100 σ (mV) = Σi=1 (V – V) i 2 100 , V= 1 100 ΣV i 100 i=1 Vi: A valid pixel output signal among all of the valid pixels for each color VOUT V1 line 1 V2 line 2 … … V100 line 100 This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling). 12 µPD3719 STANDARD CHARACTERISTIC CURVES DARK OUTPUT TEMPERATURE CHARACTERISTIC 8 STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25 °C) 2 Relative Output Voltage 2 1 0.5 1 0.2 0.25 0.1 0 10 20 30 40 0.1 50 1 5 Operating Ambient Temperature TA(°C) 10 Storage Time (ms) TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter) (TA = +25 °C) 100 R B G 80 Response Ratio (%) Relative Output Voltage 4 60 40 G 20 B 0 400 500 600 700 800 Wavelength (nm) 13 µPD3719 APPLICATION CIRCUIT EXAMPLE +5 V +15 V 10 Ω µ PD3719 + 1 10 µ F/16 V 0.1 µF B3 2 3 4 φ RB 47 Ω 5 6 + 7 47 µ F/25 V 8 9 10 11 φ2 NC VOUT3 VOUT2 GND GND VOD VOUT1 φ RB GND VRD φ CLB NC NC NC NC NC NC NC NC NC NC 36 35 34 + 33 B1 32 31 0.1 µ F 10 µ F/16 V 47 Ω 29 28 27 26 φ2 25 4.7 Ω 4.7 Ω φ2 13 φ1 φ1 24 4.7 Ω φ TG 23 4.7 Ω 16 17 18 GND GND GND NC GND NC NC NC NC 22 21 20 19 The inverters shown in the above application circuit example are the 74HC04. B1 to B3 EQUIVALENT CIRCUIT 15 V + 100 Ω CCD VOUT 100 Ω 2SC945 2 kΩ 14 φ CLB 30 12 15 +5 V 0.1 µ F 47 µ F/25 V B2 4.7 Ω 14 Remark NC + 47 µF/25 V φ1 φ TG µPD3719 PACKAGE DRAWING CCD LINEAR IMAGE SENSOR 36-PIN CERAMIC DIP (600mil) (Unit : mm) 94.00±0.50 1 14.99±0.3 8.1±0.6 36.4±0.6 2 The 1st valid pixel 15.24 1.27±0.05 0.46±0.05 (4.33) (2.33) 3 2.54 2.0±0.3 20.32 88.9±0.6 4 0.25±0.05 3.50±0.5 0.97±0.3 3.30±0.35 Name Dimensions Refractive index Glass cap 93.0 × 13.6 × 1.0 1.5 1 The 1st valid pixel 2 The 1st valid pixel 3 The surface of the chip 4 The bottom of the package The center of the pin1 The center of the package The top of the glass cap (Reference) The surface of the chip 36D-1CCD-PKG-1 15 µPD3719 NOTES ON THE USE OF THE PACKAGE The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when mounting the package on the circuit board. When mounting the package, use a circuit board which will not subject the package to bending stress, or use a socket. For this product, the reference value for the three-point bending strengthNote is 30 kg. Avoid imposing a load, however, on the inside portion as viewed from the face on which the window (glass) is bonded to the package body (ceramic). Note Three-point bending strength test Distance between supports: 70 mm, Support R: R 2 mm, Loading rate: 0.5 mm / min. 16 Load Load 70 mm 70 mm µPD3719 [MEMO] 17 µPD3719 [MEMO] 18 µPD3719 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 19 µPD3719 [MEMO] The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. 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