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DATA SHEET MOS INTEGRATED CIRCUIT μPD8827B 7500 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR DESCRIPTION The μPD8827B is a high-speed and high sensitive color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The μPD8827B has the high speed voltage amplifiers and the high speed registers. In addition, the positioning error, which occurs when some manuscripts are fed, is small since the RGB pixel line space is also small (2 lines). So, it is possible that the image of the high density is read at high speed. Therefore, it is suitable for 600 dpi/A3 high-speed color digital copiers, color scanners and so on, by the use of the plastic package with heat sink that has high heat radiation. FEATURES • Valid photocell : 7500 pixels × RGB 3 lines • Photocell’s size : 9.325 μ m • Line spacing : 18.65 μ m (2 lines) Red line - Green line, Green line - Blue line • Color filter : Primary colors (red, green and blue), Pigment filter Light resistance 107 lx•hour with standard sunlight and ultraviolet cut filter (L40) • On-chip micro lens : Stripe type lens on RGB pixel rows • Resolution : 24 dot/mm • Data rate : 70 MHz Max. (35 MHz/ch max.) A3 (297 × 420 mm) size (shorter side) • Output type : 2 outputs in phase • Power supply : +10 V • Drive clock level : CMOS output under 5 V operation • On-chip circuits : Reset feed-through level clamp circuits Voltage amplifiers ORDERING INFORMATION Part Number Package μ PD8827BCZ-A CCD linear image sensor 40-pin plastic DIP with heat sink (15.24 mm (600)) Remark "-A" indicates Pb-free (This product does not contain Pb in external electrode and other parts). The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S20022EJ1V1DS00 (1st edition) Date Published March 2010 NS Printed in Japan The mark <R> shows major revised points. The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field. 2009 μ PD8827B BLOCK DIAGRAM VOD1 φCP φ2L GND φ1BO φ2AO φ2A φ1B GND 35 34 33 32 31 29 28 26 5 25 VDD VOUT2 (Blue-even) 37 CCD analog shift register (even) 14 Transfer gate 2 VOUT1 (Blue-odd) 38 φTG2 CCD analog shift register (odd) ⋅⋅⋅ D134 D129 Photocell (Blue) S7500 ⋅⋅⋅ S7499 S2 ⋅⋅⋅ S1 39 VDD D128 D27 Transfer gate 1 16 40 VOUT3 (Green-odd) VDD CCD analog shift register (odd) ⋅⋅⋅ D134 D129 Photocell (Green) S7500 ⋅⋅⋅ S7499 S2 S1 ⋅⋅⋅ D128 D27 Transfer gate 1 15 Transfer gate 1 1 ⋅⋅⋅ D134 D129 Photocell (Red) S7500 ⋅⋅⋅ S7499 S2 ⋅⋅⋅ S1 2 D27 VDD GND CCD analog shift register (even) D128 VOUT4 (Green-even) 27 Transfer gate 1 VOUT5 (Red-odd) 3 φTG1 CCD analog shift register (odd) Transfer gate 2 VOUT6 (Red-even) 4 CCD analog shift register (even) 11 VOD2 36 2 30 HS-VDD 6 7 8 9 10 12 13 φR φ2L GND φ2BO φ1AO φ1A φ2B Data Sheet S20022EJ1V1DS μ PD8827B PIN CONFIGURATION (Top View) CCD linear image sensor 40-pin plastic DIP with heat sink (15.24 mm (600)) 1 1 1 40 Output signal 3(Green odd) VDD 39 Digital power supply VOUT5 VOUT1 38 Output signal 1(Blue odd) 4 VOUT6 VOUT2 37 Output signal 2(Blue even) Output unit drain voltage 1 5 VOD1 VOD2 36 Output unit drain voltage 2 Reset gate clock 6 φR φCP 35 Reset feed through level clamp clock Last stage shift register clock 2L 7 φ2L φ2L 34 Last stage shift register clock 2L Ground 8 GND GND 33 Ground Shift register clock 2BO 9 φ2BO φ1BO 32 Shift register clock 1BO Shift register clock 1AO 10 φ1AO φ2AO 31 Shift register clock 2AO Heat sink Vdd 11 HS-VDD HS-VDD 30 Heat sink Vdd Shift register clock 1A 12 φ1A φ2A 29 Shift register clock 2A Shift register clock 2B 13 φ2B φ1B 28 Shift register clock 1B Transfer gate clock 2 14 φTG2 φTG1 27 Transfer gate clock 1 Ground 15 GND GND 26 Ground Digital power supply 16 VDD VDD 25 Digital power supply NC 17 NC NC 24 NC NC 18 NC NC 23 NC NC 19 NC NC 22 NC NC 20 NC NC 21 NC 1 VOUT4 Digital power supply 2 VDD Output signal 5(Red odd) 3 Output signal 6(Red even) Red Blue Green VOUT3 Output signal 4(Green even) 7500 7500 7500 Data Sheet S20022EJ1V1DS 3 μ PD8827B 1 μm On-chip lens (Stripe type) 8.325 μm 9.325 μm PHOTOCELL STRUCTURE DIAGRAM Aluminum shield LINE SPACE 9.325 μm Blue 2 line (18.65 μm) 9.325 μm Green 2 line (18.65 μm) 9.325 μm 4 Red Data Sheet S20022EJ1V1DS μ PD8827B ABSOLUTE MAXIMUM RATINGS Parameter Symbol Ratings Unit Output drain voltage VOD1, VOD2 –0.3 to +12.0 V Digital power supply VDD –0.3 to +12.0 V Heat sink VDD HS-VDD –0.3 to +12.0 V Shift register clock voltage Vφ1, Vφ2 ,Vφ10, Vφ20 –0.3 to +8.0 V Last stage shift register clock voltage Vφ 2L –0.3 to +8.0 V Reset gate clock voltage Vφ R –0.3 to +8.0 V Reset feed-through level clamp clock voltage Vφ CP –0.3 to +8.0 V Transfer gate clock voltage Vφ TG1, Vφ TG2 –0.3 to +8.0 V TA 0 to +60 ˚C Tstg –40 to +100 ˚C Operating ambient temperature Note Storage temperature Note The operating ambient temperature TA is defined as an atmosphere temperature in a point 10 mm away on the circuit board, and 10 mm away from the short side of package (pin 1 side). Refer to below figure. Use it at the condition without dewy condensation. 1pin TA 10mm 10mm Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Data Sheet S20022EJ1V1DS 5 μ PD8827B RECOMMENDED OPERATING CONDITIONS Parameter Symbol MIN. TYP. MAX. Unit Output drain voltage VOD1, VOD2 9.7 10.0 10.3 V Digital power supply VDD 9.7 10.0 10.3 V Heat sink VDD HS-VDD 9.7 10.0 10.3 V Shift register clock high level Vφ 1H, Vφ 2H, Vφ 10H, Vφ 20H 4.75 5.0 6.0 V Shift register clock low level Vφ 1L, Vφ 2L, Vφ 10L, Vφ 20L -0.3 0.0 0.5 V Last stage shift register clock high level Vφ 2LH 4.75 5.0 6.0 V Last stage shift register clock low level Vφ 2LL -0.3 0.0 0.5 V Reset gate clock high level Vφ RH 4.75 5.0 5.5 V Reset gate clock low level Vφ RL -0.3 0.0 0.5 V Reset feed-through level clamp clock high level Vφ CPH 4.75 5.0 6.0 V Reset feed-through level clamp clock low level Vφ CPL -0.3 0.0 0.5 V Transfer gate clock high level Vφ TG1H, Vφ TG2H 4.75 5.0 6.0 V Transfer gate clock low level Vφ TG1L, Vφ TG2L -0.3 0.0 0.5 V Shift register clock amplitude Vφ 1p-p,Vφ 2p-p,Vφ 10p-p,Vφ 20p-p 4.75 5.0 6.5 V Last stage shift register clock amplitude Vφ 2Lp-p 4.75 5.0 6.5 V Reset gate clock amplitude Vφ Rp-p 4.75 5.0 6.0 V Reset feed-through level clamp clock amplitude Vφ CPp-p 4.75 5.0 6.5 V Transfer gate clock amplitude Vφ TG1p-p, Vφ TG2p-p 4.75 5.0 6.5 V Data rate 2xfφ R 0.2 2.0 70 MHz 6 Data Sheet S20022EJ1V1DS μ PD8827B <R> ELECTRICAL CHARACTERISTICS TA = +25°C, VOD1 = VOD2 = VDD = +10 V, fφR = 1 MHz, Data rate = 2 MHz, Storage time = 10 ms, Input clock = 5 Vp-p Light source (except Response2): 3200 K halogen lamp + C-500S (Infrared cut filter, t = 1 mm) + HA-50 (Heat absorbing filter, t = 3 mm) Parameter Symbol Saturation voltage Saturation exposure Test Conditions Vsat MIN. TYP. MAX. Unit 1.5 2.0 – V Red SE(R) – 0.05 – lx•s Green SE(G) – 0.04 – lx•s Blue SE(B) – 0.08 – lx•s Photo response non-uniformity PRNU – 6 18 % VOUT = 1.0 V Average dark signal ADS Light shielding – 1.0 5.0 mV Dark signal non-uniformity DSNU Light shielding – 2.0 12.0 mV Total power consumption PW – 900 1170 mW Power consumption (VOD1) POD1 – 250 325 mW Power consumption (VOD2) POD2 – 580 755 mW Power consumption (VDD) PDD – 70 90 mW Output impedance Response1 ZO Red RR Green RG Blue RB Response2 Red RR (Corresponding value 3200 k + C500S + HA50 A light source + CM500S – 0.2 0.4 kΩ 26.25 37.5 48.75 V/lx•s 32.97 47.1 61.23 V/lx•s 17.64 25.2 32.76 V/lx•s – (34.5) – V/lx•s – V/lx•s Green RG – (45.7) from Response1) Blue RB – (22.0) – V/lx•s Response peak Red – 610 – nm Green – 535 – nm Blue – 460 – nm Image lag IL Offset level VOS Output fall delay time td VOUT = 0.5 V – 1 30 mV 4.0 5.0 6.0 V – 6 – ns Register imbalance RI VOUT = 1.0 V – 1.0 7.0 % Total transfer efficiency TTE VOUT = 1 V, fφ 1,2 = 35 MHz 92 98 – % Vp-pφ 1,2 = 4.75 V Dynamic range DR1 Vsat / DSNU – 1000 – times DR2 Vsat / σ dark – 800 – times Reset feed-through noise RFTN Light shielding –1.5 –0.2 +0.5 V Light shielding random noise σdark Light shielding, Bit clamp – 2.5 – mV Shot noise σ shot VOUT = 1.0 V – 14.5 – mV Data Sheet S20022EJ1V1DS 7 μ PD8827B INPUT PIN CAPACITANCE (VOD1 = VOD2 = VDD = +10 V) Parameter Shift register clock pin capacitance Symbol Note Cφ 1 Pin name Pin No. MIN. TYP. MAX. Unit φ 1AO 10 140 160 180 pF φ 1A 12 140 160 180 φ 1B 28 140 160 180 φ 1BO 32 TOTAL Cφ 2 140 160 180 560 640 720 φ 2BO 9 140 160 180 φ 2B 13 140 160 180 φ 2A 29 140 160 180 φ 2AO 31 140 160 180 560 640 720 6 8 10 TOTAL pF Last stage shift register clock pin capacitance Cφ 2L φ 2L 34 6 8 10 Reset gate clock pin capacitance Cφ R φR 6 11 13 15 pF Reset feed-through level clamp clock pin capacitance Cφ CP φ CP 35 12 14 16 pF Transfer gate clock pin capacitance Cφ TG1 φ TG1 27 7 9 11 pF CφTG2 φ TG2 14 11 13 15 pF 7 pF Note Cφ1 and Cφ2 are equivalent capacitance with driving device, including the co-capacitance between φ1 and φ2. Pin 10, 12, 28 and 32 (φ1) are connected inside of the device. Pin 9, 13, 29 and 31(φ2) are also connected. 8 Data Sheet S20022EJ1V1DS TIMING CHART 1 φTG1 φTG2 φ1 φ2 φ2L Note3 φCP (Bit clamp) B Note1 7625 7627 7629 7631 7633 7635 7626 7628 7630 7632 7634 7636 131 129 121 122 130 119 120 127 31 32 128 29 30 125 27 28 126 25 26 123 7 8 124 5 Note2 Dummy cell (13 pixels/ch) Optical black (48 pixels/ch) Invalid cell (3 pixels/ch) Note1: Set the φR and φCP to low level during this period A. 9 Note2 : Refer to TIMING CHART 4 during this period B. Note3: In the case of Bit clamp mode, it is possible to omit this pulse inside the dotted line. Valid cell (3750 pixels/ch) Invalid cell (3 pixels/ch) μ PD8827B A 6 3 VOUT2,4,6 4 VOUT1,3,5 1 φCP (Line clamp) 2 Data Sheet S20022EJ1V1DS φR 10 TIMING CHART 2 (Bit Clamp) t7 t6 φ2, φ20 φ2L t7L Data Sheet S20022EJ1V1DS 0.5V t10 4.5V 4.5V 0.5V 0.5V t17 t15 4.5V 0.5V t16 φCP 0.5V 4.5V 4.5V t9 0.5V 0.5V t6L 0.5V t8 φR 4.5V 4.5V φ1, φ10 t12 t13 t14 4.5V 0.5V 0.5V td VOUT1- VOUT6 10% VOS μ PD8827B TIMING CHART 3 (Line Clamp) t6 4.5V 4.5V φ1, φ10 φ2, φ20 t7L 0.5V 0.5V 4.5V 4.5V 0.5V 0.5V t6L 4.5V 4.5V φ2L 0.5V t8 t9 t10 0.5V t15 4.5V Data Sheet S20022EJ1V1DS φR φCP t7 0.5V 0.5V “Low” td VOUT1-VOUT6 10% VOS μ PD8827B 11 μ PD8827B TIMING CHART4 (The period B of TIMING CHART 1) t2 t3 t4 4.5V 4.5V φTG1 0.5V 0.5V 4.5V φTG2 t1 φ1, φ10 4.5V 0.5V t5 t4 4.5V t21 0.5V t4 t25 t2 4.5V t20 t2 t19 4.5V 4.5V 0.5V 4.5V φ2, φ20 4.5V 0.5V 4.5V φ2L t15 φR 0.5V t23 φCP 0.5V Symbol t1 t2, t4 TYP. MAX. Unit 100 200 2000 ns 0 10 - ns 1000 1100 5000 ns t5 0 200 1000 ns t6, t7 0 10 - ns t6L, t7L 0 3 - ns t8, t10 0 3 - ns t9 2 125 - ns t12, t14 0 3 - ns t13 8 125 - ns t15 0 250 - ns t16 0 125 - ns t17 2 125 - ns t19 300 400 2000 ns t20 100 200 2000 ns t21 300 400 2000 ns t3 12 MIN. t23 300 400 - ns t25 1500 1600 5000 ns Data Sheet S20022EJ1V1DS 0.5V μ PD8827B CROSS POINTS (φ1∗, φ2∗) CROSS POINTS (φ1AO, φ2L) (φ1BO, φ2L) CROSS POINTS φ1AO, φ1BO φ1∗ 1.7 V or more φ2∗ 1.7 V or more 1.7 V or more φ2L 0.5 V or more Remark Adjust cross points of (φ1A, φ2A), (φ1B, φ2B), (φ1AO, φ2AO), (φ1BO, φ2BO), (φ1AO, φ2L) and (φ1BO,φ2L) with an input resistance of each pin. CLOCK HIGH/LOW LEVEL WIDTH Min. 7 ns Min. 3 ns 4.75 V 4.75 V φ1∗, φ2∗ φ2L φ1∗, φ2∗ φ2L 0.25 V 0.25 V Min. 7 ns Min. 3 ns Data Sheet S20022EJ1V1DS 13 μ PD8827B DEFINITIONS OF CHARACTERISTICS 1. Saturation voltage: Vsat The output signal voltage at which the response linearity is lost 2. Saturation exposure: SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs 3. Photo response non-uniformity: PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula, and it is defined by each six of them. Δx PRNU (%) = x 3750 × 100 x Σ j=1 j x= 3750 Δx : maximum of | xj − x | xj : Output voltage of valid pixel number j VOUT x Register Dark DC level Δx 4. Average dark signal: ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula, and it is defined by each six of them. 3750 ADS (mV) = d Σ j=1 j dj : Dark signal of valid pixel number j 3750 5. Dark signal non-uniformity: DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula, and it is defined by each six of them. DSNU (mV) : maximum of | dj − ADS | j = 1 to 3750 dj : Dark signal of valid pixel number j VOUT ADS Register Dark DC level DSNU 6. Output impedance: ZO Impedance of the output pins viewed from outside 14 Data Sheet S20022EJ1V1DS μ PD8827B 7. Response: R Output voltage divided by exposure (lx•s). Note that the response varies with a light source (spectral characteristic). 8. Image lag: IL IL is the average signal output just after light off. IL (mV) = V1 φ TG Light ON OFF VOUT V1 VOUT 9. Register imbalance: RI RI is the rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels. n 2 2 n Σ (V2j – 1 – V2j) j=1 RI (%) = 1 n × 100 n ΣV j j=1 n : Number of valid pixels Vj : Output voltage of each pixel 10. Random noise (light shielding): σdark Shot noise: σshot σdark and σshot are defined as the standard deviation of a valid pixel output signal with 100 times (100 lines) data sampling. These are measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling) 100 σ (mV) = Σ i=1 (Vi – V)2 100 , 1 V= 100 100 Σ i=1 Vi Vi : A valid pixel output signal among all of the valid pixels for each color. VOUT V1 line1 V2 line2 V100 line100 Data Sheet S20022EJ1V1DS 15 μ PD8827B 11. Total transfer efficiency: TTE TTE is the total transfer rate of CCD analog shift register. The rate is calculated by the following formula, and it is defined by each odd output. TTE (%) = (1 - Vb / Average output of all the valid pixels) × 100 Vb Vb: The spilt pixel output (Odd 7635th pixel) 7635 7631 7633 12. Reset feed-through noise: RFTN RFTN is switching noise of φR. RFTN is defined as follows. φR φCP φ2L VOS VOUT RFTN 16 Data Sheet S20022EJ1V1DS μ PD8827B STANDARD CHARACTERISTIC CURVES (Nominal) DARK OUTPUT TEMPERATURE CHARACTERISTIC STORAGE TIME OUTPUT VOLTAGE CHARACTERISTICS (TA =25°C) 8 2 Relative Output Voltage 2 1 0.5 0.25 0.1 1 0.2 0 10 20 30 40 50 0.1 1 60 Operating Ambient Temperature TA (°C) 10 5 Storage Time (ms) TOTAL SPECTRAL RESPONSE CHARACTERISTICS 120 (without IR cut filter and heat absorbing filter at TA = 25°C) G 100 Response Ratio(%) Relative Output Voltage 4 R B 80 60 40 G 20 B 0 300 400 500 600 700 800 900 Wavelength(nm) Data Sheet S20022EJ1V1DS 17 μ PD8827B APPLICATION CIRCUIT EXAMPLE + B4 1 VOUT4 VOUT3 2 VDD +5 V + Note 2 B5 3 VOUT5 B6 4 VOUT6 A VOUT1 VOUT2 5 VOD1 6 39 Ω φR 7 90 Ω φ2L 8 GND 20 Ω VDD 9 φ2BO 10 φ1AO VOD2 φCP φ2L GND φ1BO φ2AO 20 Ω +5 V 40 +10 V B3 39 +5 V 38 B1 37 + B2 36 A 35 34 39 Ω 33 90 Ω 32 20 Ω 31 20 Ω +5 V Note 3 + Note 4 + 11 12 20 Ω 13 20 Ω 14 90 Ω 15 16 17 18 +5 V 19 + 20 Note 1 HS-VDD HS-VDD φ1A φ2A φ2B φ1B φTG2 φTG1 GND GND VDD VDD NC NC NC NC NC NC NC NC 30 29 28 20 Ω 27 20 Ω 26 90 Ω 25 24 23 Inverters: 74AC04 22 21 Inverters: 74AC04 Notes 1. Connect the NC pins to GND. 2. Arrange a circuit A near each power supply terminals (VDD1, VDD2) to prevent the interference between VDD1 and VDD2. 3. Connect 3 inverters for each terminal of φ1∗∗ and φ2∗∗. 4. HS-VDD is connected only to the heat sink, it is not connected to VOD1 and VOD2, and VDD inside the device. Set HS-VDD to VDD in common on a board. EQUIVALENT CIRCUIT A EQUIVALENT CIRCUIT B1 to B6 + 1 kΩ + CCD VOUT 18 2SA1461 100 Ω Data Sheet S20022EJ1V1DS +10 V μ PD8827B PACKAGE DRAWING PD8827BCZ-A CCD LINEAR IMAGE SENSOR 40-PIN PLASTIC DIP (WITH HEAT SINK) (15.24mm (600)) (Unit : mm) 94.4±0.5 94.0±0.5 1st valid pixel 35.5±0.4 2 14.3±0.3 1 8.95±0.4 14.7±0.3 21 40 20 1 1.27±0.15 A 6.22±0.5 B 15.24±0.20 B A 0.46±0.1 11.1±0.2 5 11.1±0.2 5 3.0±0.2 43.18±0.4 0.9±0.1 0.25±0.05 4.0±0.5 SECTION A-A (1.66) 16.67±0.5 2.54±0.25 10.0±0.2 SECTION B-B 3 7.4±0.3 7 6 4.56±0.3 4 5° 5° 1° 5 14.1±0.2 1° 5 14.8±0.2 Name Glass cap Dimensions 91.0×11.6×0.7 Refractive index 1.5 1 1st valid pixel The center of the pin1 2 1st valid pixel The center of the packa ge 3 The surface of the CCD chip The top of t he cap 4 The bottom of the package The surface of the CCD chip 5 The draft angle of the shaded portions (4 places) are 1 dgree. 6 There is no heat sink exposure from the package. 7 The center of the CCD chip Package side(s haded portion) 40C-1CCD-PKG2 NEC Electronics Corporation 2009 Data Sheet S20022EJ1V1DS 19 μ PD8827B RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. Type of Through-hole Device μ PD8827BCZ-A: CCD linear image sensor 40-pin plastic DIP with heat sink (15.24 mm (600)) Process Partial heating method Conditions Pin temperature: 380°C or below, Heat time: 3 seconds or less (per pin). Cautions 1. During assembly care should be taken to prevent solder or flux from contacting the glass cap. The optical characteristics could be degraded by such contact. 2. Soldering by the solder flow method may have deleterious effects on prevention of glass cap soiling and heat resistance. So the method cannot be guaranteed. NOTES OF HANDLING THE PACKAGES The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when mounting the package on the circuit board. You should not reform the lead frame. We recommend to use a IC-inserter when you assemble to PCB. For this product, the reference value for the three-point bending strength Note is 280[N]. Avoid imposing a load, however, on the inside portion as viewed from the face on which the window (glass) is bonded to the package body. Note Three-point bending strength test Distance between supports: 70 mm, Support R: R2 mm, Loading rate: 0.5 mm/min. 20 Load Load 70 mm 70 mm Data Sheet S20022EJ1V1DS μ PD8827B NOTES OF HANDLING 1. MOUNTING OF THE PACKAGE The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when mounting the package on the circuit board. Don’t have any object come in contact with glass cap. You should not reform the lead frame. We recommend to use a ICinserter when you assemble to PCB. Also, be care that any of the following can cause the package to crack or dust to be generated. 1. Applying heat to the external leads for an extended period of time with soldering iron. 2. Rapid cooling or heating 3. Applying repetitive bending stress to the external leads. 2. GLASS CAP Don’t either touch glass cap surface by hand or have any object come in contact with glass cap surface. Care should be taken to avoid mechanical or thermal shock because the glass cap is easily to damage. For dirt stuck through electricity ionized air is recommended. 3. OPERATE AND STORAGE ENVIRONMENTS Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid storage or usage in such conditions. Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the devices are transported from a low-temperature environment to a high-temperature environment. Avoid such rapid temperature changes. For more detail, refer to our document “Review of Quality and Reliability Handbook” (C12769E) 4. ELECTOROSTATIC BREAKDOWN CCD image sensor is protected against static electricity, but destruction due to static electricity is something detected. Before handling, be sure to take the following protective measures. 1. Ground the tools such as soldering iron, radio cutting pliers of or pincer. 2. Install a conductive mat or on the floor or working table to prevent the generation of static electricity. 3. Either handle bare handed or use non chargeable gloves, clothes or material. 4. Ionized air is recommended for discharge when handling CCD image sensor. 5. For the shipment of mounted substrates, use box treated for prevention of static charges. 6. Anyone who is handling CCD image sensors, mounting them on PCB or testing or inspecting PCBs on which semiconductor devices have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1MΩ. Data Sheet S20022EJ1V1DS 21 μ PD8827B NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). (2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. (4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. (5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. 22 Data Sheet S20022EJ1V1DS μ PD8827B [MEMO] Data Sheet S20022EJ1V1DS 23 μ PD8827B • The information in this document is current as of March, 2010. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. 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