SM5849AF NIPPON PRECISION CIRCUITS INC. Asynchronous Sample Rate Converter OVERVIEW The SM5849AF is a digital audio signal, asynchronous sample rate converter LSI. It supports 16/20/24-bit word length input data, 16/20/24-bit word length output data, 2kHz to 100kHz input sample rate range, and 4kHz to 200kHz output sample rate range. It also features a built-in digital deemphasis filter and digital attenuator. FEATURES Functions ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Left/right-channel processing (stereo) 2 to 100kHz input sample rate range (fsi) 4 to 200kHz output sample rate range (fso) 0.45 to 2.2-times variable sample rate conversion ratio (fso/fsi) Asynchronous input and output timing (clock inputs) System clock inputs (input and output clocks independent) • 256fsi or 384fsi input system clock select • 256fso or 384fso output system clock select Deemphasis filter • IIR-type filter • 44.1, 48 or 32kHz Digital attenuator • 11-bit data, 1025 levels • Smooth attenuation change • +12dB gain shift function Direct mute function Through mode operation • Direct connection from input to output Output data clocks (LRCO, BCKO) • Slave mode: external input • Master mode: output system clock generated internally Dither round-off processing • Dither round-off ON/OFF selectable 3.3V single supply 80-pin QFP Silicon-gate CMOS process Filter Characteristics and Converter Efficiency ■ ■ ■ ■ ■ 24-bit internal data word length Deemphasis filter characteristics (IIR filter) • ±0.03dB gain deviation from ideal filter characteristics Anti-aliasing LPF characteristics • Output/input sample rate conversion ratio automatic filter select (6 FIR filters) - Up converter LPF 1.0 to 2.2 times - Down converter LPF I 0.92 times: 48.0 to 44.1kHz - Down converter LPF II 0.73 times: 44.1 to 32.0kHz - Down converter LPF III 0.67 times: 48.0 to 32.0kHz - Down converter LPF IV 0.5 times: 48.0 to 24.0kHz - Down converter LPF V 0.45 times: 48.0 to 22.1kHz • ±0.00005dB passband ripple • > 110dB stopband attenuation Converter noise levels • ≤ −110dB internal calculation (quantization) noise • −98dB (16-bit output), −122dB (20-bit output), and −146dB (24-bit output) word rounding noise Output S/N ratio (theoretical values) S/N ratio Output signal w ord length 16-bit input w ord length 20-bit input w ord length 24-bit input w ord length 16 bits 94.8dB 97.7dB 97.7dB 20 bits 97.7dB 109.5dB 109.7dB 24 bits 97.7dB 109.7dB 110dB NIPPON PRECISION CIRCUITS—1 SM5849AF Interfaces ■ Input data format • 2s-complement, L/R alternating, serial • IIS/non-IIS format ■ Output data format • 2s-complement, MSB first, L/R alternating, serial • Continuous bit clock Data position Data sequence Mode W ord length 1 Right justified M S B fi rst 1 16 bits 2 Right justified LSB first 2 20 bits 3 Left justified M S B fi rst 3 24 bits 4 IIS M S B fi rst 4 24 bits 5 Right justified M S B fi rst 5 16 bits 6 Right justified LSB first 6 20 bits 7 Left justified M S B fi rst 7 24 bits 8 IIS M S B fi rst 9 Right justified M S B fi rst Right justified LSB first 11 Left justified M S B fi rst 12 IIS M S B fi rst Mode W ord length 16 bits Data position Nor mal (non IIS) Right justified Left justified 20 bits 10 IIS selection IIS 24 bits APPLICATIONS ■ Digital audio equipment-interface sample rate conversion (AV amplifiers, CD-R, DAT, MD and 8mm VTRs) ■ Commercial recording/editing equipment sample rate conversion ORDERING INFORMATION D e vice P ackag e SM5849AF 80-pin QFP NIPPON PRECISION CIRCUITS—2 SM5849AF PINOUT 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 SM5849AF JAPAN 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. MLEN/DEEM MCK/FSI2 MDT/FSI1 MCOM DMUTE VDD VDD DI BCKI LRCI VSS ICLK ICKSL IFM1 IFM2 IWL1 IWL2 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VDD OCKSL OCLK VSS LRCO BCKO DOUT N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VSS 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 60 59 58 57 VSS N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. SLAVE THRUN RSTN DITHN TST2N STATE IISN OWL1 OWL2 VDD Top view PACKAGE DIMENSIONS (Unit: mm) 80-pin QFP 1.4 0.1 0.05 0.125 0.025 0 to 10 0.1 0.5 0.1 0.18 0.05 1.7max 14 0.4 12 0.1 14 0.4 12 0.1 0.5 0.2 NIPPON PRECISION CIRCUITS—3 SM5849AF BLOCK DIAGRAM IWL1 IWL2 IFM1 IFM2 MCOM MDT/FSI1 MCK/FSI2 BCKI DI Input data interface Deemphasis and attenuator setup MLEN/DEEM Arithmetic operations ICLK ICKSL LRCI RSTN Input-stage divider Deemphasis operation Input timing controller Attenuator Filter characteristic select Interpolation filter operation Dither operation DITHN TST2N Output operation timing controller Output operation OWL1 OWL2 Output format controller Output data interface IISN SLAVE OCLK OCKSL Output-stage clock select LRCI BCKI DI Output-stage divider Through mode switching Mute generator Direct mute THRUN DMUTE STATE LRCO BCKO DOUT NIPPON PRECISION CIRCUITS—4 SM5849AF PIN DESCRIPTION I/O 1 Number Name Description 1 VDD – Supply voltage 2 DI Ip Digital input signal 3 BCKI Ip Bit clock input 4 LRCI Ip W ord clock input 5 VSS – Ground 6 ICLK I System clock input 7 ICKSL Ip System clock select. 384fs clock when HIGH, and 256fs clock when LOW . Input format select 8 9 IFM1 IFM2 Ip Ip IFM1 IFM2 Data position LOW LOW Right justified LOW HIGH Right justified 1 HIGH LOW Left justified HIGH HIGH IIS 1. Data is in LSB first sequence Input word length select 10 11 IWL1 IWL2 Ip Ip IWL1 IWL2 Data length LOW LOW 16 bits LOW HIGH 24 bits HIGH LOW 20 bits HIGH HIGH 24 bits 12 NC – No connection (must be open) 13 NC – No connection (must be open) 14 NC – No connection 15 NC – No connection (must be open) 16 NC – No connection (must be open) 17 NC – No connection (must be open) 18 NC – No connection (must be open) 19 NC – No connection (must be open) 20 VSS – Ground 21 VDD – Supply voltage 22 DMUTE Ip Direct mute pin. Muting ON when HIGH. 23 MCOM Ip Microcontroller control select. Microcontroller control when HIGH. 24 MDT/FSI1 Ip W h e n M C O N = H I G H : Microcontroller interface data input (MDT) W h e n M C O N = L OW : Deemphasis filter fs select 1 (FSI1) 25 MCK/FSI2 Ip W h e n M C O N = H I G H : Microcontroller interface clock (MCK) W h e n M C O N = L OW : Deemphasis filter fs select 2 (FSI2) 26 MLEN/DEEM Ip W h e n M C O M i s H I G H : Microcontroller interface latch enable (MLEN) W h e n M C O M i s L OW : Deemphasis function select (DEEM) 27 NC – No connection (must be open) 28 NC – No connection (must be open) 29 NC – No connection (must be open) 30 NC – No connection (must be open) 31 NC – No connection (must be open) 32 NC – No connection (must be open) 33 NC – No connection (must be open) 34 NC – No connection (must be open) 35 NC – No connection (must be open) 36 NC – No connection (must be open) 37 NC – No connection (must be open) NIPPON PRECISION CIRCUITS—5 SM5849AF Number Name I/O 1 38 NC – No connection (must be open) 39 NC – No connection (must be open) 40 VSS – Ground 41 VDD – Description Supply voltage Output word length select 42 43 OWL2 OWL1 Ip Ip OWL1 OWL2 Data length LOW LOW 16 bits LOW HIGH 24 bits HIGH LOW 20 bits HIGH HIGH 24 bits 1 1. Data is in left justified sequence. 44 IISN Ip IIS output mode select. Normal mode when HIGH, and IIS mode when LOW . 45 S TAT E O Status output 46 TST2N Ip IC test mode pin 2. Test mode when LOW . Leave HIGH or open circuit for normal operation. 47 DITHN Ip Output dither control pin. Dither when LOW , and normal mode when HIGH. 48 RSTN Ip Reset input. Reset when LOW . 49 THRU N Ip Through mode set. Normal mode when HIGH, and through mode when LOW . 50 S L AV E Ip Slave mode set. Slave mode when HIGH, and master mode when LOW . 51 NC – No connection (must be open) 52 NC – No connection (must be open) 53 NC – No connection (must be open) 54 NC – No connection (must be open) 55 NC – No connection (must be open) 56 NC – No connection (must be open) 57 NC – No connection (must be open) 58 NC – No connection (must be open) 59 NC – No connection (must be open) 60 VSS – Ground 61 VDD – Supply voltage 62 OCKSL Ip Output system clock select. 384fs when HIGH, and 256fs when LOW . Output system clock input 63 OCLK I 64 VSS – Ground 65 LRCO O W ord clock output 66 B C KO O Bit clock output 67 DOUT O Data output 68 NC – No connection (must be open) 69 NC – No connection (must be open) 70 NC – No connection (must be open) 71 NC – No connection (must be open) 72 NC – No connection (must be open) 73 NC – No connection (must be open) 74 NC – No connection (must be open) 75 NC – No connection (must be open) 76 NC – No connection (must be open) 77 NC – No connection (must be open) 78 NC – No connection (must be open) 79 NC – No connection (must be open) 80 VSS – Ground 1. Ip = input pin with internal pull-up resistor NIPPON PRECISION CIRCUITS—6 SM5849AF SPECIFICATIONS Absolute Maximum Ratings VSS = 0V Symbol Rating 1 Unit Supply voltage range VDD −0.3 to 4.0 V Input voltage range V IN V S S − 0.3 to V D D + 0.3 V Storage temperature range T stg −55 to 125 °C Pow er dissipation PD 400 mW Symbol Rating Unit Supply voltage range VDD 3.0 to 3.6 V Operating temperature range T opr −40 to 85 °C P arameter 1. Ratings also apply at supply switch ON and OFF. Recommended Operating Conditions VSS = 0V P arameter DC Electrical Characteristics VDD = 3.0 to 3.6V, VSS = 0V, Ta = −40 to 85°C Rating P arameter Current consumption Symbol ID D Condition No output load Unit min typ max – 70 100 mA HIGH-level input voltage 1 V IH1 2.0 – – V L O W -level input voltage 1 V IL1 – – 0.8 V HIGH-level input voltage 2 V IH2 2.0 – – V L O W -level input voltage 2 V IL2 – – 0.8 V V D D –0.4 – – V HIGH-level output voltage 3 VOH I O H = −1 . 0 m A L O W -level output voltage 3 VOL IO L = 1.0mA – – 0.4 V HIGH-level input current 2 IIH V IN = V D D – – 1.0 µA L O W -level input current 2 IIL V IN = 0V – – 90 µA IL H V IN = V D D – – 1.0 µA IL L V IN = 0V – – 1.0 µA Input leakage current 1 1. Pins ICLK and OCLK. 2. Pins DI, BCKI, LRCI, ICKSL, IFM1, IFM2, IWL1, IWL2, DMUTE, MCOM, MDT/FSI1, MCK/FSI2, MLEN/DEEM, OW L 1 , OWL2, IISN, DITHN, TST2N, RSTN, T H R UN, SLAVE, OCKSL. 3. Pins STAT E , L R C O, BCKO , D O U T. NIPPON PRECISION CIRCUITS—7 SM5849AF AC Electrical Characteristics Input clock (ICLK) Condition P arameter HIGH-level clock pulsewidth L O W -level clock pulsewidth Clock pulse cycle Rating Symbol Unit tC W H 1 System clock min typ max 256fsi 17.5 – – 384fsi 11.7 – – 256fsi 17.5 – – 384fsi 11.7 – – 256fsi 39.0 – 2000 384fsi 26.0 – 1300 ns tC W L 1 ns tC Y 1 ns Output clock (OCLK) Condition P arameter HIGH-level clock pulsewidth L O W -level clock pulsewidth Clock pulse cycle Rating Symbol Unit tC W H 2 System clock min typ max 256fso 8.7 – – 384fso 5.8 – – 256fso 8.7 – – 384fso 5.8 – – 256fso 19.5 – 1000 384fso 13.0 – 650 ns tC W L 2 ns tC Y 2 ns ICLK and OCLK timing ICLK OCLK 0.5VDD t CWH1, t CWH2 t CWL1, t CWL2 t CY1, t CY2 NIPPON PRECISION CIRCUITS—8 SM5849AF Serial inputs (DI, LRCI, BCKI) Rating P arameter Symbol Unit min typ max 50 – – ns BCKI HIGH-level pulsewidth tB C W H 1 B C K I L OW -level pulsewidth tB C W L 1 50 – – ns BCKI pulse cycle tB C Y 1 100 – – ns DI setup time tD S 50 – – ns DI hold time tD H 50 – – ns Last BCKI rising edge to LRCI edge tB L 1 50 – – ns LRCI edge to first BCKI rising edge tL B 1 50 – – ns t BCY1 t BCWH1 t BCWL1 BCKI 0.5VDD t DS t DH 0.5VDD DI t BL1 LRCI t LB1 0.5VDD NIPPON PRECISION CIRCUITS—9 SM5849AF Serial inputs (LRCO, BCKO: SLAVE = HIGH) Rating P arameter Symbol Unit min typ max B C K O HIGH-level pulsewidth tB C W H 2 39 – – ns B C K O L OW -level pulsewidth tB C W L 2 39 – – ns tB C Y 2 78 – – ns Last BCKO rising edge to LRCO edge tB L 2 39 – – ns LRCO edge to first BCKO rising edge tL B 2 39 – – ns B C K O pulse cycle Note: B C KO clock inputs exceeding 64 fso cannot be detected, and will cause incorrect operation. t BCY2 t BCWH2 t BCWL2 BCKO 0.5VDD t BL2 LRCO t LB2 0.5VDD NIPPON PRECISION CIRCUITS—10 SM5849AF Microcontroller interface (MCK, MDT, MLEN) Rating P arameter Symbol Unit min typ max M C K L O W -level pulsewidth tM C W L 50 – – ns MCK HIGH-level pulsewidth tM C W H 50 – – ns MDT setup time tM D S 50 – – ns MDT hold time tM D H 50 – – ns M L E N L OW -level pulsewidth tM LW L 50 – – ns MLEN HIGH-level pulsewidth tM LW H 50 – – ns MLEN setup time tM L S 50 – – ns MLEN hold time tM L H 50 – – ns MDT 0.5VDD t MDS t MDH 0.5VDD MCK t MCWL t MCWH t MLS t MLH MLEN 0.5VDD t MLWL t MLWH Reset input (RSTN) Rating P arameter Symbol Unit min typ max First HIGH-level pulsewidth after supply ON tH R S T – 640 – tC Y RSTN pulsewidth tR S T 64 – – tC Y Note: tC Y is the system clock input cycle time. tR S T = approximately 3.8 µs when t C Y = 59ns. VDD RSTN t HRST t RST NIPPON PRECISION CIRCUITS—11 SM5849AF Serial outputs (DOUT, BCKO, LRCO) SLAVE = LOW, CL = 15pF Rating P arameter Symbol Condition Unit min typ max LRCO pulse cycle tL O C Y – 1/fso – ns L R C O L OW -level pulsewidth tL O W L – 1/2fso – ns LRCO HIGH-level pulsewidth tL O W H – 1/2fso – ns O C K S L = L OW – 1/64fso – B C K O pulse cycle tB O C Y OCKSL = HIGH – 1/48fso – O C K S L = L OW – 1/128fso – OCKSL = HIGH – 1/96fso – O C K S L = L OW – 1/128fso – OCKSL = HIGH – 1/96fso – tB D H 1 B C K O fall to DOUT, LRCO rise –5 – 20 ns tB D L 1 B C K O fall to DOUT, LRCO fall –5 – 20 ns Symbol Condition B C K O L OW -level pulsewidth tB O W L B C K O HIGH-level pulsewidth tB O W H B C K O to DOUT and LRCO delay time ns ns ns SLAVE = HIGH, CL = 15pF Rating P arameter B C K O to DOUT delay time Unit min typ max tB D H 2 B C K O fall to DOUT rise 0 – 50 ns tB D L 2 B C K O fall to DOUT fall 0 – 50 ns t BOCY t BOWL t BOWH 0.5VDD BCKO t BDH1, t BDL1 t BDH2, t BDL2 DOUT 0.5VDD t BDH t BDL LRCO 0.5VDD t LOWH t LOWL t LOCY NIPPON PRECISION CIRCUITS—12 SM5849AF Filter Characteristics Anti-aliasing filter frequency characteristic Filter5 48 to 24kHz Filter3 44.1 to 32kHz Filter1 Up converter 0 Filter4 48 to 32kHz Filter6 48 to 22.05kHz Filter2 48 to 44.1kHz -20 Attenuation [dB] -40 -60 -80 -100 -120 -140 0.15 0.17 0.19 0.22 0.24 0.26 0.28 0.3 0.33 0.35 0.37 0.39 0.41 0.43 0.46 0.48 0.5 0.52 0.54 0.57 0.59 0.61 0.63 Frequency [× fsi] Deemphasis filter frequency characteristic 0.00 -4.00 -6.00 -8.00 44.1KHz 48KHz 32KHz -10.00 -12.00 10 20.23 40.93 82.79 167.5 338.8 685.5 1387 2805 5675 11482 23227 Frequency [Hz] 0 Phase Characteristics θ [°] Attenuation [dB] -2.00 32KHz 44.1KHz 48KHz -20 -40 -60 -80 -100 -120 10 17.3 29.92 51.76 89.54 154.9 267.9 463.4 801.7 1387 2399 4150 7178 12417 21478 Frequency [Hz] NIPPON PRECISION CIRCUITS—13 SM5849AF FUNCTIONAL DESCRIPTION Input Data Interface (DI, LRCI, BCKI, IFM1, IFM2, IWL1, IWL2) Table 1. Input data format (IFM1, IFM2, IWL1, IWL2) Mode IFM1 IFM2 1 LOW LOW 2 LOW HIGH IWL1 IWL2 LOW LOW W ord length Data position Data sequence Right justified M S B fi rst Right justified LSB first 16 bits 3 HIGH LOW Left justified M S B fi rst 4 HIGH HIGH IIS M S B fi rst 5 LOW LOW Right justified M S B fi rst 6 LOW HIGH Right justified LSB first HIGH LOW 20 bits 7 HIGH LOW Left justified M S B fi rst 8 HIGH HIGH IIS M S B fi rst 9 LOW LOW Right justified M S B fi rst 10 LOW HIGH Right justified LSB first L O W or HIGH HIGH 24 bits 11 HIGH LOW Left justified M S B fi rst 12 HIGH HIGH IIS M S B fi rst Attenuator and Deemphasis Selection The attenuator is set using the microcontroller interface. When the attenuator is used, deemphasis settings also need to be set using the microcontroller interface. The microcontroller interface comprises MDT, MCK and MLEN, and is used to transfer all input serial data. Table 2. Attenuator and deemphasis function select Function set method Function Deemphasis ON/OFF Deemphasis frequency (fsi) select Attenuator data set Test mode select External pins ( M C O M = L OW ) Microcontroller interface (MCOM = HIGH) DEEM FDEEM FSI1, FSI2 FFSI1, FFSI2 N/A (no attenuation) 11 bits (B0 to B10) N/A (test mode 1) FTST1, FTST2 MCON should not be switched after a power-ON reset. When MCOM is LOW, the logic levels on FSI1, FSI2 and DEEM select the device function. When MCOM is HIGH, serial data received on MDT, MCK and MLEN sets the attenuation data and control flag data. NIPPON PRECISION CIRCUITS—14 SM5849AF Microcontroller Interface (MCOM, MDT, MCK, MLEN) When MCOM is HIGH, the microcontroller interface is active, comprising MDT (data), MCK (clock) and MLEN (latch enable clock) interface pins. Input data on MDT is synchronized to the MCK clock. Data is read into the input stage shift register on the rising edge of MCK. Accordingly, the input data should change on the falling edge of MCK. Input data enters an internal SIPO (serial-to-parallel converter register), and then the parallel data is latched into the mode register on the rising edge of the latch enable clock MLEN. The mode register addressed is determined by bit D1 of the 12 data bits before MLEN goes HIGH. If this bit is LOW, then the data is read into the attenuation data register as shown in figure 1. If this bit is HIGH, then the data is read into the mode flag register as shown in figure 2. The function of each bit in the mode flag register is described in table 3. MLEN ,,,,,,,,, ,,,,,,,,, ,,,,,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, 1 MDT D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 MSB "L" ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, 12 MCK B0 D12 LSB B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 Figure 1. Attenuation data format (D1 = LOW) MLEN ,,,,,,,, ,,,,,,,, ,,,,,,,, ,,,,, ,,,, ,,,,, ,,,,,,,,, ,,,, 1 12 MCK MDT D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 "H" "L" "L" "L" "L" FTST1 FTST2 FRATE F12DB FFSI1 FFSI2 FDEEM ,,,, ,,,, ,,,, ,,,, ,,,, ,,,, Figure 2. Mode flag data format (D1 = HIGH) NIPPON PRECISION CIRCUITS—15 SM5849AF Table 3. Mode flag description Mode function select D1 Bit P arameter D2 to D7 D8 D9 Reset mode M o d e fl ag (Not used) F R AT E F12DB L OW/HIGH Select IC test mode flags. Not used for normal operation. D2 to D7 should be set LOW . Test mode select LOW HIGH Set the input/output sample rate ratio for each output sample LOW Set the input/output sample rate ratio with high accuracy every 2048 output samples HIGH +12dB gain shift LOW No gain shift (normal operation) Input/output rate LOW Attenuator LOW HIGH fsi select D10 FFSI1 Deemphasis filter fs select 1 FFSI2 FFSI1 fsi LOW LOW LOW HIGH HIGH LOW 48.0kHz HIGH HIGH 32.0kHz LOW 44.1kHz D11 D12 FFSI2 FDEEM Deemphasis filter fs select 2 Deemphasis control ON/OFF HIGH Deemphasis filter ON LOW Deemphasis filter OFF LOW LOW Deemphasis (DEEM, FSI1, FSI2 pins or FDEEM, FFSI1, FFSI2 flags) The digital deemphasis filter is an IIR filter with variable coefficients to faithfully reproduce the gain and phase characteristics of analog deemphasis filters. Table 4. Deemphasis ON/OFF DEEM ( M C O M = L OW ) The filter coefficients are selected by FSI1 (or FFSI1 flag) and FSI2 (or FFSI2 flag) to correspond to the sampling frequencies fs = 44.1, 48.0 and 32.0kHz. FDEEM (MCOM = HIGH) Deemphasis HIGH ON LOW OFF Table 5. Deemphasis fs select (FSI1, FSI2 pins or FFSI1, FFSI2 flags) M C O M = L OW ( M C O M = H I G H ) fs FSI1 (FFSI1) FSI2 (FFSI2) LOW LOW HIGH LOW LOW HIGH 48.0kHz HIGH HIGH 32.0kHz 44.1kHz NIPPON PRECISION CIRCUITS—16 SM5849AF Attenuation (MDT, MCK, MLEN) The digital attenuator coefficients are read in as serial data on the microcontroller interface. Data on MDT is read into the internal shift register on the rising edge of MCK, and then 12 bits are latched internally on the rising edge of MLEN. When the leading bit is 0 (D1 = LOW), the following 11 bits are read into the attenuation register and used as an unsigned integer in MSB first format. See figure 3. MLEN ,,,,,,,,, ,,,,,,,,, ,,,,,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, 1 MDT D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 MSB "L" ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, 12 MCK B0 D12 LSB B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 Figure 3. Attenuation data format (microcontroller interface) Although the attenuation data comprises 11 bits, only 1025 levels are valid as given by the following. 10 DATT = ∑ ai × 2 DATT Gain = 20 × log ---------------- [dB] 1024 when F12DB = LOW ( 10 – i ) i=0 DATT = 20 × log ---------------- [dB] 256 The gain of the attenuator for values of DATT from 001H to 400H are given by the following equations. Note that when the F12DB flag is HIGH, the gain is shifted by a fixed +12.0412dB. when F12DB = HIGH After a system reset initialization, DATT is set to 400H and the F12DB flag is LOW, corresponding to 0dB gain. (The F12DB flag is described in table 3.) Table 6. Attenuator settings D1 LOW Attenuation data D AT T F 1 2 D B = L OW (default) F12DB = HIGH Gain (dB) Linear expression Gain (dB) Linear expression 000H −∞ 0.0 −∞ 0.0 001H −60.206 1/1024 −48.165 1/256 ↓ ↓ ↓ ↓ ↓ 100H −12.041 256/1024 0.0 256/256 ↓ ↓ ↓ ↓ ↓ 3FFH −0.0085 1023/1024 12.032 1023/256 400H (to 7FFH) 0 1.0 12.041 4.0 NIPPON PRECISION CIRCUITS—17 SM5849AF Attenuator operation A change in the attenuation data DATT causes the gain to change smoothly from its previous value towards the new setting. The new attenuation data is stored in the attenuation data register and the current attenuation level is stored in a temporary register. Consequently, if a new attenuation level is read in before the previously set level is reached, the gain changes smoothly from the current value towards the latest setting as shown in figure 4. The attenuation counter output changes, and hence the gain changes, by 1 step every output sample. The time taken to reduce the gain from 0dB (or 12dB) to −∞dB is (1024/fso), which corresponds to approximately 23.2ms when fso = 44.1kHz. Level 1 Level 5 0 dB Level 3 Gain Level 2 —∞ ∆t Level 4 Time Figure 4. Attenuator operation example Mute (DMUTE) Direct mute Table 7. DMUTE operation ON/OFF DMUT E Function LOW Nor mal data is output from the next output word (mute OFF) HIGH 0 data is output from the next output word (mute ON) Other mute operations The direct mute function is also invoked at the following times. ■ ■ ■ ■ When the reset input (RSTN) changes. When the fs setting changes, for deemphasis, using either FSI1, FSI2 inputs or FFSI1, FFSI2 flags. When the ICKSL, IFM1, or IFM2 setting changes. When the ICLK input system clock stops. Table 8. Other mute operations Input Function R S T N = L OW 0 data is output from the next output word (mute ON) RSTN = HIGH Nor mal data is output from the 3073rd output word (mute OFF) FSI1, FSI2 input settings c h a n g e d ( M C O M = L OW). FFSI1, FFSI2 input settings changed (MCOM = HIGH) ICKSL, IFM1, IFM2 input settings change. 0 data is output from the next output word (mute ON). Nor mal data is output from the 3073rd output word (mute OFF) ICLK input system clock stops. 0 data is output from the next output word (mute ON) ICLK input system clock restarts. Nor mal data is output from the 3073rd output word (mute OFF) NIPPON PRECISION CIRCUITS—18 SM5849AF Internal Operating Status (STATE) Internally, all functions are performed on 24-bit serial data, and the conversion rate and filter type are selected accordingly. The output format is 24-bit left-justified. Table 9. Status data description Output bit position 1 to 20 21 Content (Output data cycle/input data cycle) − 129 Ex. 1st 20th 00.111111111111011111 ⇒ 1.0 times 01.111111111111011111 ⇒ 2.0 times (1/2 conversion rate ratio) 00.011111111111011111 ⇒ 0.5 times (2.0 conversion rate ratio) Not used. Selected filter type 22 23 24 DA2 DA1 DA0 DA2 DA1 DA0 Filter type 0 0 0 1 Up converter C o nversion frequency (example) 0 0 1 2 48 to 44.1kHz 0 1 0 3 44.1 to 32kHz 0 1 1 4 48 to 32kHz 1 0 0 5 96 to 48kHz, 48 to 24kHz 1 0 1 6 96 to 44.1kHz, 48 to 22.05kHz Note that when THRUN is LOW, LRCO and BCKO are not guaranteed to be synchronized to the STATE output. Input System Clock (ICLK, ICKSL) The input system clock can be set to run at either 256fsi or 384fsi, where fsi is the input frequency on LRCI. Table 10. ICKSL and input system clock Note that ICLK and LRCI should be divided from a common clock source or PLL to maintain synchronism. ICKSL ICLK system clock rate HIGH 384fsi LOW 256fsi Output System Clock (OCLK, OCKSL) The output system clock can be set to run at either 256fso or 384fso, where fso is the output frequency on LRCO. In through mode, OCLK and OCKSL have no function and are not used. Note that even in slave mode, a suitable clock must be input on OCLK. A malfunction prevention circuit uses this clock so that operation continues when the ICLK stops. Table 11. SLAVE, OCKSL and output system clock S L AV E OCKSL O C L K s y s t e m clock rate HIGH 384fso LOW 256fso × Not used LOW HIGH NIPPON PRECISION CIRCUITS—19 SM5849AF Output Data Interface and Output Clock Selection (LRCO, BCKO, DOUT, SLAVE) Table 12. Output mode description Function THRUN S L AV E Mode Description L R C O , B C KO state LOW Master mode Output word clock (LRCO) and output bit clock ( B C KO) are divided from OCLK. Outputs HIGH Slave mode Output word clock (LRCO) and output bit clock ( B C KO) are supplied externally. Inputs 1 Through mode Output word clock (LRCO), output bit clock (BCKO) and output data (DOUT) are the same as LRCI, BCKI and DI, respectively. DMUTE is valid. Outputs HIGH × LOW 1. The number of BCKO input clock cycles should not exceed 64 per word. Correct operation is not guaranteed beyond these limits. Output Format Control (OWL1, OWL2, IISN) The output is in MSB-first, 2s-complement, L/R alternating, bit serial format with a continuous bit clock. Inputs Output format Mode OWL2 OWL1 W ord length LOW LOW 16 bits LOW HIGH 20 bits 3 HIGH LOW 24 bits 4 HIGH HIGH 24 bits 5 LOW LOW 16 bits LOW HIGH 20 bits HIGH × 24 bits IISN 1 2 HIGH 6 7 LOW IIS selection Nor mal (non IIS) IIS Data position Right justified Left justified Output Timing Calculation The output timing is controlled to maintain the desired ratio between the output data cycle and the input data cycle. Output round-off processing The internal processor data length and output data length are different, making output data round-off processing necessary. The SM5849AF supports selectable normal round-off processing and trigonometric function dither round-off processing*. * DITHN Output round-off processing HIGH Nor mal round-off LOW Dither round-off TPDF: Triangular Probability Density Function NIPPON PRECISION CIRCUITS—20 SM5849AF Filter Characteristic Selection Conversion rates from 0.45 to 2.2 times are supported using the following 6 filter types. The ratio between the output sample rate and input sample rate is measured automatically and the most suitable filter type for this ratio is selected automatically. When the selected fs conversion ratio and the actual sample rate conversion ratio do not coincide, the following phenomenon occur. Table 14. Mismatch condition and response Condition 1 Table 13. fs ratio and filter selection Filter mode fs ratio (fso/fsi) Selects range C o nversion frequency (example) 1 1.0 to 2.2 ≥ 0.969697 Up converter 2 0.91875 0.864865 to 0.969697 48.0 to 44.1kHz 3 0.72562 0.711111 to 0.864865 44.1 to 32.0kHz 4 0.66667 0.627451 to 0.711111 48 to 32kHz 5 0.50000 0.492308 to 0.627451 48 to 24kHz, 96 to 48kHz 6 0.459375 ≤ 0.492308 48 to 22.05kHz, 96 to 44.1kHz Response Actual sample rate conversion ratio is low er than the selected filter conversion ratio The audio band high-pass develops aliasing noise. Actual sample rate conversion ratio is higher than the selected filter conversion ratio The audio band high-pass is cut off. 1. An output noise may be generated if the fs conversion ratio changes at a rate greater 0.119%/sec. System Reset (RSTN) At power-ON, all device functions must be reset. The device is reset by applying a LOW-level pulse on RSTN. At system reset, the internal arithmetic operation, output timing counter and internal flag register operation are synchronized on the next LRCI rising edge. Note that all flags are set to their defaults (all LOW). A power-ON reset signal can be applied from an external microcontroller. For systems where ICLK and LRCI are stable at power ON, initialization can be performed by connecting a 0.001µF capacitor between RSTN and VSS. Otherwise, a capacitor value should be chosen such that RSTN does not go HIGH until after LRCI and ICLK have stabilized. Through Mode (THRUN) Table 15. Through mode function description THRUN Mode Description LOW Through mode Direct connections are made: LRCI to LRCO, BCKI to BCKO , and DI to D O U T. DMUTE is valid. HIGH Nor mal mode Sample rate converter operation Synchronizing Internal Arithmetic Timing The clock on LRCI should pass through 1 cycle for every 384 (ICKSL = HIGH) or 256 (ICKSL = LOW) ICLK clock cycles to maintain correct internal arithmetic sequence. If the number of ICLK cycles is different, increases or decreases, or any jitter is present, device operation could be affected. Table 16. ICLK and clock tolerance There is a fixed-value tolerance within which the internal sequence and LRCI clock timing are not adversely affected. Whenever the allowable tolerance is exceeded, the internal sequence start-up may be delayed or fail. When this occurs, there is a possibility that a click noise will be generated. ICKSL Allow a b le clock variation HIGH (384fs mode) +8 to −6 cycles L O W (256fs mode) +4 to −3 cycles NIPPON PRECISION CIRCUITS—21 SM5849AF TIMING DIAGRAMS Input Timing Examples (DI, BCKI, LRCI) Audio data input timing (right-justified 16-bit word, IFM1 = L, IFM2 = L, IWL1 = L, IWL2 = L) LRCI(fsi) 1 24 25 48 BCKI(48fsi) MSB DI LSB MSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Audio data input timing (right-justified 24-bit word, IFM1 = L, IFM2 = L, IWL1 = H, IWL2 = H) LRCI(fsi) 1 24 25 MSB LSBMSB 48 BCKI(48fsi) DI LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Audio data input timing (left-justified 20-bit word, IFM1 = H, IFM2 = L, IWL1 = H, IWL2 = L) LRCI(fsi) 1 24 25 48 BCKI(48fsi) MSB DI LSB MSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 All data bits after the LSB (20th bit) are ignored. Note that more than 20 BCKI cycles are required. Audio data input timing (IIS-format 24-bit word, IFM1 = H, IFM2 = H, IWL1 = L, IWL2 = H) LRCI(fsi) 1 32 33 64 BCKI(64fsi) MSB DI LSB MSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Audio data input timing (right-justified 24-bit word, LSB first, IFM1 = H, IFM2 = H, IWL1 = L, IWL2 = H) LRCI(fsi) 1 32 33 64 BCKI(64fsi) LSB DI MSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 LSB MSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NIPPON PRECISION CIRCUITS—22 SM5849AF Output Timing Examples (DOUT, BCKO, LRCO) Audio data output timing (right-justified 16-bit word, IISN = H, OWL1 = L, OWL2 = L) LRCO(fso) 1 24 25 48 BCKO(48fso) MSB DOUT LSB MSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Audio data output timing (right-justified 24-bit word, IISN = H, OWL1 = L, OWL2 = H) LRCO(fso) 1 24 25 MSB LSBMSB 48 BCKO(48fso) DOUT LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Audio data output timing (left-justified 24-bit word, IISN = H, OWL1 = H, OWL2 = H) LRCO(fso) 1 32 33 64 BCKO(64fso) MSB DOUT LSB MSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Audio data output timing (IIS-format 24-bit word, IISN = L, OWL1 = L, OWL2 = H) LRCO(fso) 1 32 33 64 BCKO(64fso) MSB DOUT LSB MSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Audio data output timing (right-justified 24-bit word, IISN = H, OWL1 = L, OWL2 = H) LRCO(fso) 1 32 33 64 BCKO(64fso) MSB DOUT LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 MSB LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NIPPON PRECISION CIRCUITS—23 SM5849AF State Data Output Timing State data output timing IISN = H LRCO(fso) 1 32 33 64 BCKO(64fso) MSB STATE LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 IISN = L LRCO(fso) 1 32 33 64 BCKO(64fso) MSB STATE LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Delay Time tINPUT is the time when the serial input data read in is completed (on the rising edge of LRCI). tOUTPUT is the time when the serial output data read out is completed (on the rising edge of LRCO). The delay between input and output is given by tOUTPUT − tINPUT = (55 ± 5)/fsi. 1/fs 55 ± 5 Serial data input t input Serial data output 1/fso t output t INPUT t OUTPUT — t INPUT t OUTPUT NIPPON PRECISION CIRCUITS—24 SM5849AF TYPICAL APPLICATIONS Input Interface Circuit Digital audio interface receiver (CS8414) (256fsi) MCK ICLK FSYNC LRCI Level Shifter (5V to 3.3V) SCK BCKI SDATA DI Co/F0 MLEN/DEEM 5V DIR CS8414 SEL SM5849AF ICKSL CS12/FCK MCOM 3.3V M3 IFM1 M2 IFM2 M1 IWL1 M0 IWL2 Output Interface Circuit Digital audio interface receiver (CS8404) External Clock 24.576MHz (256fso) 3.3V 12.288MHz (128fso) 5V OCLK MCK LRCO FSYNC Level Shifter (3.3V to 5V) BCKO SCK DOUT SDATA 5V PRO SM5849AF OCKSL 3.3V OWL1 TRNPT/FC1 DIT CS8404 M2 OWL2 M1 IISN THRUN 3.3V M0 SLAVE NIPPON PRECISION CIRCUITS—25 SM5849AF NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility fo r the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with expor t controls on the distribution or dissemination of the products. Customers shall not expor t, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9914BE 2000.06 NIPPON PRECISION CIRCUITS—26