E2C0018-27-Y3 ¡ Semiconductor MSC1205 ¡ Semiconductor This version: Nov. 1997 MSC1205 Previous version: Jul. 1996 32-Bit Duplex Controller/Driver with Digital Dimming Function GENERAL DESCRIPTION The MSC1205 is a Bi-CMOS display driver for a 1/2-duty vacuum fluorescent display tube. It consists of a 64-bit shift register, latch circuits, a digital diming circuit, and drivers. The MSC1205 provides an interface with a microcomputer only by three signal lines: LOAD, DATA, and CLOCK. FEATURES • Power Supply Voltage: 8 to 18V (built-in 5V regulator for logic) • Built-in 1-terminal RC oscillation circuit (with external capacitor) • Built-in digital dimming circuit 10-bit resolution Programmable in the duty range of 0/2048 (0%) to 1015.5/2048 (49.6%). • Can directly drive 32 ¥ 2 display anodes. • Built-in power-on reset circuit • Package options: 42-pin plastic DIP (DIP42-P-600-2.54) (Product name: MSC1205-RS) 44-pin plastic QFP (QFP44-P-910-0.80-2K) (Product name: MSC1205GS-2K) 1/15 ¡ Semiconductor MSC1205 BLOCK DIAGRAM SEG32 SEG31 SEG2 SEG1 GRID1 GRID2 VOLTAGE VDD VSS DRIVER REGULATOR 8 to 18V 32 bits LEVEL SHIFTER 5V BLANK 32 bits DOWN COUNTER 10 bits R (fosc) COMPARATOR bo TIMING GENERATOR (bo) 5V BL MULTIPLEXER ST 10 bits LATCH OSC OSC (SEGLD) 32 bits 32 bits L L LATCH (DIMLD) L LOAD TIMING CONTROL LOAD LATCH 64 bits Q1-Q10 Q1-Q64 (POR) DATA CLOCK D (2 bits) D Q1-Q64 (64 bits) TEST SHIFT REGISTER 2/15 ¡ Semiconductor MSC1205 INPUT AND OUTPUT CONFIGURATION • Schematic Diagrams of Logic Portion Input Circuit 1 VDD (5V Reg.) INPUT VSS VSS • Schematic Diagrams of Logic Portion Input • Schematic Diagrams of Logic Portion Input Circuit 2 Circuit 3 VDD VDD (5V Reg.) BLANK (5V Reg.) TEST VSS VSS VSS VSS • Schematic Diagrams of Driver Output Circuit VDD VDD OUTPUT VSS VSS 3/15 ¡ Semiconductor MSC1205 PIN CONFIGURATION (TOP VIEW) DATA 1 42 VSS CLOCK 2 41 TEST LOAD 3 40 OSC SEG1 4 39 BLANK SEG2 5 38 GRID2 SEG3 6 37 GRID1 SEG4 7 36 VDD SEG5 8 35 SEG32 SEG6 9 34 SEG31 SEG7 10 33 SEG30 SEG8 11 32 SEG29 SEG9 12 31 SEG28 SEG10 13 30 SEG27 SEG11 14 29 SEG26 SEG12 15 28 SEG25 SEG13 16 27 SEG24 SEG14 17 26 SEG23 SEG15 18 25 SEG22 SEG16 19 24 SEG21 SEG17 20 23 SEG20 SEG18 21 22 SEG19 42-Pin Plastic DIP 4/15 ¡ Semiconductor MSC1205 SEG2 SEG1 LOAD CLOCK DATA NC VSS TEST OSC BLANK GRID2 44 43 42 41 40 39 38 37 36 35 34 PIN CONFIGURATION (TOP VIEW) 8 26 SEG27 SEG11 9 25 SEG26 SEG12 10 24 SEG25 SEG13 11 23 SEG24 22 SEG10 SEG23 27 SEG28 21 7 SEG22 SEG9 20 28 SEG29 SEG21 6 19 SEG8 SEG20 29 SEG30 18 5 SEG19 SEG7 17 30 SEG31 NC 4 16 SEG6 SEG18 31 SEG32 15 3 SEG17 SEG5 14 32 VDD SEG16 2 13 SEG4 SEG15 33 GRID1 12 1 SEG14 SEG3 NC : No-connection pin 44-Pin Plastic QFP 5/15 ¡ Semiconductor MSC1205 PIN DESCRIPTION Symbol Type Description DATA I Serial data input pin. This pin receives display data, dimming data, enable bit and mode bit. CLOCK I Shift clock input pin with Schmitt circuit. Serial data is clocked in this pin at the rising edge of the shift clock pulse. LOAD I Load pulse input pin. The load signal is input when dimming data and segment data transfer is finished. SEG1 -SEG32 O Segment driver output pins. These pins provide large current driving (IOH = –5.5mA at VDD = 12V) and small current driving (IOH = –1.8mA at VDD = 12V). VDD — O Power supply voltage. This pin is connected to a power supply of 8 to 18V. GRID1 GRID2 O Grid driver output pin. When this pin is set to "L", the display is turned on. This pin is connected to external PNP transistor. The segment data of the 33rd bit (S33) to the 64th bit (S64) is valid in the segment data of 64 bits. BLANK I Display blank input pin with a pull-up resistor. When this pin is set to "L", the display is turned off (SEGn = "L") OSC I Oscillation input pin. This pin is connected to an external capacitor of 82pF. A standard oscillation frequency is 512kHz. TEST I Test input pin with a pull-down resistor. Normally this pin should be left open or should be connected to ground. VSS — Grid driver output pin. When this pin is set to "L", the display is turned on. This pin is connected to external PNP transistor. The segment data of the first bit (S1) to the 32nd bit (S32) is valid in the segment data of 64 bits. Ground pin. This pin is connected to ground (VSS = 0) 6/15 ¡ Semiconductor MSC1205 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit VDD Ta = 25°C –0.3 to +20 V Input Voltage VIN Ta = 25°C –0.3 to +6.0 V Storage Temperature Range TSTG — –65 to +150 °C Supply Voltage RECOMMENDED OPERATING CONDITIONS Symbol Condition Range Unit Power Supply Voltage Parameter VDD — 8 to 18 V Operating Temperature Range Top — –40 to +85 °C ELECTRICAL CHARACTERISTICS DC Characteristics (Ta = –40 to +85˚C, VDD = 8 to 18V) Parameter Symbol Condition High Level Input Voltage VIH — Low Level Input Voltage VIL — High Level Input Current IIH1 VI = 5V IIH3 Low Level Input Current Min. Max. Unit Applicable pin 3.8 5.5 V — –0.3 0.8 V — –1 1 mA DATA, LOAD CLOCK VI = 5V — 500 mA TEST IIL1 VI = 0V –1 1 mA DATA, LOAD CLOCK IIL2 VI = 0V –500 –100 mA BLANK IIL3 VI = 0V –1 1 mA TEST High Level Output Voltage (1) (Small Current Driver) VOH1 VDD = 9.5V, IOH1 = –1.3mA VDD-0.5 — V VOH2 VDD = 12V, IOH2 = –1.8mA VDD-0.5 — V SEG (2n) n = 1-16 VOH3 VDD = 15V, IOH3 = –2.3mA VDD-0.5 — V High Level Output Voltage (2) (Large Current Driver) VOH4 VDD = 9.5V, IOH4 = –4.1mA VDD-0.5 — V VOH5 VDD = 12V, IOH5 = –5.5mA VDD-0.5 — V VOH6 VDD = 15V, IOH6 = –7.0mA VDD-0.5 — V Low Level Output Voltage VOL1 VDD = 9.5V, IOL1 = 1mA — 4 V VOL2 VDD = 9.5V, IOL2 = 500mA — 2 V VOL3 VDD = 9.5V, IOL3 = 2mA — 0.3 V High Level Output Voltage (3) VOH7 VDD = 9.5V, IOH7 = –0.8mA VDD-0.5 — V GRID1, GRID2 IDD fOSC = 512kHz, no load — 20 mA — Current Consumption SEG (2n-1) n = 1-16 SEG1-SEG32 GRID1, GRID2 7/15 ¡ Semiconductor MSC1205 AC Characteristics (Ta = –40 to +85˚C, VDD = 8 to 18V) Parameter Clock Frequency Symbol Condition Min. Typ. Max. Unit fC(1/tclock) — — — 1 MHz tCW — 500 — — ns Clock Pulse Width tcr, tcf — — — 500 ns DATA Setup Time tDS — 200 — — ns DATA Hold Time tDH — 200 — — ns Clock Æ Load Time tCL — 100 — — ns Load Æ Clock Time tLC — 50 — — ns Load Pulse Width tLW — 1.3 — — ms Clock Rise/Fall Time SEGn Rise/Fall Time Large Current tr, tf CL = 20pF 0 4/120 400 ns Small Current tr, tf CL = 20pF 0 15/120 400 ns 150 250 350 Hz 307.2 512 716.8 kHz Grid Frequency fGRID Oscillation Frequency fOSC DATA CL = 82pF±5% SEGMENT DATA DIMMING DATA CLOCK LOAD 3.8V DATA tDS 0.8V tDH fC tCW tCW 3.8V CLOCK tCL tcr tLC tcf 3.8V LOAD 0.8V tr SEGn GRIDn 0.8V tLW tf 0.9VDD 0.1VDD 8/15 ¡ Semiconductor MSC1205 FUNCTIONAL DESCRIPTION DATA Input This device uses 10-bit dimming and 64-bit segment data. In order to transfer this data, the enable bit (M0) and mode bit (M1) should be set to an initial state. The data format is shown below. DATA M0 M1 D1 D2 D10 M0 M1 S1 S2 S63 S64 CLOCK Figure 1. Data Transfer Timing M0 : This bit is an enable bit. M0 = "0" : Subsequent data is disabled; preceding data is held. M0 = "1" : The beginning of data transfer. The following data is clocked in sequentially. M1 : This bit is used to select the mode. M1 = "0" : Subsequent data is handled as the segment data. M1 = "1" : Subsequent data is handled as the dimming data. D1 : LSB of dimming data. S1 : data for grid1 of SEG1. S2 : data for grid1 of SEG2. .. . S32 : data for grid1 of SEG32. S33 : data for grid2 of SEG1. .. . S64 : data for grid2 of SEG32. Notes: 1. Be sure to set the enable bit to "1" before data is transferred. Data following M0 is handled to be enable. If data is input with the enable bit not set to "1", the first "1" data coming next is handled as the enable bit. 2. If the number of the data bits applied is greater (for example, 67 bits are applied for the segment data of 64 bits), the data bits are pushed out in the same order that they are applied, and thus S1, S2, and S3 are ignored. 3. If the number of the data bits applied is smaller (for example, 62 bits are applied for the segment data of 64 bits), S63 and S64 prior to data transfer are shifted to S1 and S2 respectively. 9/15 ¡ Semiconductor MSC1205 CLOCK Input DATA is shifted at the rising edge of the clock. LOAD Input The contents of the shift register are shifted in while the LOAD input is "H" and latched at "H" to "L" transition. The LOAD signal is reproduced in the VF driver for the latch pulse for dimming data and segment data. After 10-bit dimming data and 64-bit segment data are transferred, input the LOAD signal prior to the next clock. Blank Function A low-level voltage at the BLANK pin turns the display off (segment output = "L"). When segment data transfer is finished, the display is turned on. The relationship between this data transfer and the display is shown in Figure 2. Initial Setting When powered on (i.e., when the segment data has never been transferred) the display is turned off (the segment output is "L"). When segment data transfer is finished, display is turned on. The relationship between this data transfer and the display is shown in Figure 2. VDD DATA DIMMING DATA SEGMENT DATA LOAD SEGn Display OFF Display ON Figure 2. Relationship Between Data Transfer and Display 10/15 ¡ Semiconductor MSC1205 If the segment data is transferred before the dimming data is transferred after powered on, the display is turned on at the completion of segment data transfer, with undefined dimming values. The relationship between data transfer and display is shown in Figure. 3. VDD DATA SEGMENT DATA LOAD SEGn DIMMING DATA Dimming value is undefined Display OFF Display ON Figure 3. Relationship Between Advance Transfer of Segment Data and Display Oscillator Connect an external capacitor (C), as shown in Figure 4. The oscillating frequency fOSC depends on the external capacitor used. The following equation is true between fOSC and grid frequency (fGRID): fGRID = fOSC/2048 Terminal fOSC C (82pF) Figure 4. Oscillation Equivalent Circuit 11/15 ¡ Semiconductor MSC1205 Dimming Function The duty cycle of grid output can be changed in 1/2048 step with respect to 10-bit dimming data. Table 1 shows the relationship between dimming data and duty ratio. Table 1. Dimming Data and Duty Ratio (MSB) dimming data (LSB) 00 0000 0000 0/2048 00 0000 0001 1/2048 ~ ~ ~ ~ 11 1111 0111 1015/2048 11 1111 1000 1015.5/2048 Max ~ ~ ~ ~ Æ Note: Duty ratio 11 1111 1110 1015.5/2048 Max Setting for address 3FFH is invalid. Duty ratios are programmable within the range of 0/2048 (0%) to 1015.5/2048 (49.6%). 12/15 ¡ Semiconductor MSC1205 APPLICATION CIRCUIT SEG1-SEG32 4 5 SEG1 SEG2 1 2 3 35 SEG32 DATA CLOCK LOAD CPU GRID1 37 GRID2 38 MSC1205 40 VFD OSC VSS 42 VDD 36 82pF 13/15 ¡ Semiconductor MSC1205 PACKAGE DIMENSIONS (Unit : mm) DIP42-P-600-2.54 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 6.20 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 14/15 ¡ Semiconductor MSC1205 (Unit : mm) QFP44-P-910-0.80-2K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Epoxy resin 42 alloy Solder plating 5 mm or more Package weight (g) 0.41 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 15/15