E2B0024-27-Y2 ¡ Semiconductor MSM6599B ¡ Semiconductor This version: MSM6599B Nov. 1997 Previous version: Mar. 1996 80-DOT SEGMENT DRIVER GENERAL DESCRIPTION The MSM6599B is a dot matrix LCD segment driver LSI which consists of two 80-bit latches, an 80-bit level shifter and an 80-bit 4-level driver. It latches the 4-bit parallel display data transferred from a microcomputer or LCD controller LSI, then outputs the LCD driving waveform to the LCD. FEATURES • • • • • Supply voltage : 4.5 to 5.5 V LCD driving voltage : 18 to 28 V Applicable LCD duty : 1/64 to 1/256 LCD output : 80 Because of 4-bit parallel transfers, the transfer speed is 1/4 that of conventional serial transfer, insuring low power consumption. • Applicable common driver : MSM6698 (80 outputs) • Package options: 100-pin plastic QFP (QFP100-P-1420-0.65-K) (Product name : MSM6599B GS-K) 100-pin plastic QFP(QFP100-P-1420-0.65-BK) (Product name : MSM6599B GS-BK) 1/11 ¡ Semiconductor MSM6599B BLOCK DIAGRAM O1 O2 O3 O78 O79 O80 V1 V3 80-BIT 4-LEVEL DRIVER V4 VEE VDD VEE 80-BIT LEVEL SHIFTER DF DISP OFF VDD VSS LOAD 80-BIT LATCH (II) D0 D1 D2 D3 80-BIT LATCH (I) VDD VSS CP CONTROL CIRCUIT EI EO SHL 2/11 ¡ Semiconductor MSM6599B 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 O50 O49 O48 O47 O46 O45 O44 O43 O42 O41 O40 O39 O38 O37 O36 O35 O34 O33 O32 O31 PIN CONFIGURATION (TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 O30 O29 O28 O27 O26 O25 O24 O23 O22 O21 O20 O19 O18 O17 O16 O15 O14 O13 O12 O11 O10 O9 O8 O7 O6 O5 O4 O3 O2 O1 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 EI V1 V3 V4 VEE DF LOAD VSS DISPOFF VDD SHL NC NC NC D3 D2 D1 D0 CP EO O51 O52 O53 O54 O55 O56 O57 O58 O59 O60 O61 O62 O63 O64 O65 O66 O67 O68 O69 O70 O71 O72 O73 O74 O75 O76 O77 O78 O79 O80 NC : No connection 100-Pin Plastic QFP 3/11 ¡ Semiconductor MSM6599B ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage (1) Supply Voltage (2) Input Voltage Storage Temperature Symbol VDD VDD– VEE *1 Condition Rating Unit Ta = 25°C –0.3 to +6.5 V Ta = 25°C 0 to 32 V VI Ta = 25°C –0.3 to VDD + 0.3 V TSTG — –55 to +150 °C *1 VDD ≥ V1 > V3 > V4 > VEE RECOMMENDED OPRATING CONDITIONS Parameter Supply Voltage (1) Supply Voltage (2) Operating Temperature Symbol Condition Range Unit VDD — 4.5 to 5.5 V — 18 to 28 V — –20 to +75 °C VDD – VEE *1 Top *1 VDD ≥ V1 > V3 > V4 > VEE 4/11 ¡ Semiconductor MSM6599B ELECTRICAL CHARACTERISTICS DC Characteristics (VDD = 5V ±10%, Ta = –20 to +75°C) Parameter Symbol Condition Min. Typ. Max. Unit "H" Input Voltage VIH *1 — 0.7VDD — VDD V "L" Input Voltage VIL *1 — VSS — 0.3VDD V "H" Input Current IIH *1 VI = VDD, VDD = 5.5V — — 1 mA "L" Input Current IIL *1 VI = 0V, VDD = 5.5V — — –1 mA "H" Output Voltage VOH *2 IO = –0.2mA, VDD = 4.5V VDD–0.4 — — V "L" Output Voltage VOL *2 IO = 0.2mA, VDD = 4.5V — — 0.4 V ON Resistance RON*4 — 1.5 3.0 kW — — 300 mA — — — — 100 mA — 5 — pF VDD–VEE = 25V, *3 | VN – VO | = 0.25V VDD = 4.5V IDDSBY fCP = 6.0 MHz, VDD = 5.5V VDD–VEE = 25V, No load *5 Supply Current (1) IDD1 fCP = 6.0 MHz, VDD = 5.5V VDD–VEE = 25V, No load *6 Supply Current (2) IV fCP = 6.0 MHz, VDD = 5.5V VDD–VEE = 25V, No load *7 Input Capacitance CI ƒ = 1 MHz Standby Current 1.5 1.0 mA Applicable to LOAD, CP, D0 to D3, EI, DF, DISPOFF, SHL. Applicable to EO. VN = V1 to VEE V4 = 14/16 (VDD–VEE), V3 = 2/16 (VDD–VEE), VDD = V1. Applicable to O1 to O80. Display Data 1010 fDF = 45 Hz, current from VDD to VSS when the display data is not being processed. *6 Display Data 1010 fDF = 45 Hz, current (VDD side current) from VDD to VSS and VEE, and current (VEE side current) from VDD to VEE when the display data is *1 *2 *3 *4 *5 V *7 Display Data 1010 DD being processed. VEE fDF = 45 Hz, fLOAD = 20 kHz, current on V1, V3 and V4. 5/11 ¡ Semiconductor MSM6599B Switching Characteristics (VDD = 5V ±10%. Ta = –20 to +75°C) Parameter Symbol Condition Min. Typ. Max. Unit Clock Frequency ƒCP DUTY = 50% — — 6.5 MHz Clock Pulse Width tW1 — 56 — — ns Load Pulse Width tW2 — 70 — — ns Rise/Fall Time tr, tf — — — 20 ns Data Setup Time tDSU — 50 — — ns Data Hold Time tDHD — 50 — — ns Load Setup Time tLSU — 80 — — ns Load-to-Clock Time tLC — 80 — — ns tPLH, tPHL CL=15pF — — 236 ns tESU — 50 — — ns Propagation Delay Time EI Setup Time Note: When display control by the DISPOFF pin is performed, the rise and fall time must be ≤ 1µs. tf tr tW1 CP 0.8VDD tW1 0.8VDD tDSU tW1 0.8VDD 0.2VDD 0.2VDD tDHD 0.8VDD 0.8VDD 0.8VDD 0.2VDD 0.2VDD D0 - D3 tLSU LOAD 0.8VDD t W2 0.2VDD tr 0.8VDD tLC 0.2VDD tf 0.8VDD CP LOAD 1 18 19 20 0.8VDD tPLH E0 2 0.2VDD tPHL 0.8VDD 0.2VDD tESU EI 0.2VDD 6/11 ¡ Semiconductor MSM6599B FUNCTIONAL DESCRIPTION Pin Functional Description • EI, EO These are enable pins. When a cascade connection is required, set the first MSM6599B's EI pin at "L" level and connect EO pin to the next MSM6599B's EI pin. When a single MSM6599B is used, EI should be set at "L" level. • CP Clock input pin for display data input. Data is clocked in the latch (I) at the falling edge of the clock pulse. The clock pulse from this pin is active when the enable F/F is set, and inactive when it is not set. • LOAD Input pin to latch the display data of one line stored in the latch (I). The latch (I) data is transferred to the latch (II) at the falling edge. At this time, the control circuit to save the power is reset and the display data of the next line can be stored. • DF Synchronous signal input pin for alternate signal for LCD driving . Frame inversion signal is input to this pin. • VDD, VSS Power supply pins of the MSM6599B. VDD is generally set to 4.5V to 5.5V. VSS is the GND pin, which is set to 0V. 7/11 ¡ Semiconductor MSM6599B • D0, D1, D2, D3 Display data input pins for the 80-bit latch (I). The display data is input at the falling edge of clock pulse. Table 1 shows the relationship between display data, DF, LCD driver output, and display. Table 1 Display Data DF LCD Driver Output Display L L Non-select level (V3) OFF H L Select level (V1) ON L H Non-select level (V4) OFF H H Select level (VEE) ON • SHL Input pin to select the loading direction of display data. Set this pin to "H" or "L" level during power-on. Table 2 shows the relationship between shift direction of data (D0 to D3) and driver output (O1 to O80). Table 2 SHL L H Direction of Data Loading D0 Æ O1 Æ O5 Æ O77 D1 Æ O2 Æ O6 Æ O78 D2 Æ O3 Æ O7 Æ O79 D3 Æ O4 Æ O8 Æ O80 D0 Æ O80 Æ O76 Æ O4 D1 Æ O79 Æ O75 Æ O3 D2 Æ O78 Æ O74 Æ O2 D3 Æ O77 Æ O73 Æ O1 Last Data First Data 8/11 ¡ Semiconductor MSM6599B • V1, V3, V4, VEE Bias supply voltage pins used to drive the LCD. Use an external bias voltage supply for driving the LCD • O1 - O80 Output pins for the 4-level driver that directly correspond to each bit of the 80-bit latch (II) contents. One of V1, V3, V4 and VEE is selected and output by a combination of latched content and DF signals. See the "Truth Table". Connect this output to the segment side of the LCD. • DISP OFF Input pin to control O1 to O80 outputs. The V1 level is output from O1 to O80 pins regardless of the display data during "L" level input. See the "Truth Table". Truth Table Latch Data DISPOFF Driver Output (O1 to O80) L L H V3 L H H V1 H L H V4 H H H VEE X X L V1 DF X : Don't Care NOTES ON USE Precautions when turning power ON/OFF: The LCD drivers of this IC require a high voltage. For this reason, if a high voltage is applied to the LCD drivers with the logic power supply floating, excess current flows. This may damage the IC. Be sure to follow the sequence below when turning the power ON or OFF. Power ON : Logic circuits ON Æ LCD drivers ON, or both ON at a time Power OFF : LCD drivers OFF Æ logic circuits OFF, or both OFF at a time 9/11 ¡ Semiconductor MSM6599B PACKAGE DIMENSIONS (Unit : mm) QFP100-P-1420-0.65-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.29 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 10/11 ¡ Semiconductor MSM6599B (Unit : mm) QFP100-P-1420-0.65-BK Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.29 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 11/11