E2A0011-16-X1 ¡ Semiconductor MSM6927/6947 ¡ Semiconductor This version: Jan. 1998 MSM6927/6947 Previous version: Nov. 1996 1200 bps Single Chip FSK MODEM GENERAL DESCRIPTION The MSM6927 and the MSM6947 are OKI's 1200 bps single chip modem series which transmit and receive serial, binary data over a switched telephone network using frequency shift keying(FSK). The MSM6927 is compatible with ITU-T V.23 series data sets, while the MSM6947 is compatible with Bell 202 series data sets. These devices provide all the necessary modulation, demodulation, and filtering required to implement a serial, asynchronous communication link. OKI's single chip modem series is designed for users who are not telecommunication experts and are easy to use cost effective alternative to standard discrete modem design. CMOS LSI technology provides the advantages of small size, low power, and increased reliability. The design of the integrated circuit assures compatibility with a broad base of installed low speed modems and acoustic couplers. Applications include interactive terminals, desk top computers, point of sale equipment, and credit verification systems. FEATURES • Compatible with ITU-T V.23 (MSM6927) • Compatible with BELL 202 (MSM6947) • CMOS silicon gate process • Switched capacitor and advanced CMOS analog technology • Data rate from 0 to 1200 bps • Half duplex (2-Wire) • Receive squelch delay • Selectable built-in timers and external delay timers possible • All filtering, modulation, demodulation, and DTE interface on chip • Crystal controlled oscillator on chip • TTL compatible digital interface • Low power dissipation: 90 mW Typ. • Package options: 28-pin plastic DIP (DIP28-P-600–2.54) (Product name: MSM6927RS) (Product name: MSM6947RS) 44-pin plastic QFP (QFP44-P-910-0.80–K) (Product name: MSM6927GS-K) (Product name: MSM6947GS-K) (QFP44-P-910-0.80–2K) (Product name: MSM6927GS-2K) 1/31 ¡ Semiconductor MSM6927/6947 BLOCK DIAGRAM SG1 VA SG2 VA AG SG1 SG2 VREF CDR2 VD CDR1 AG Carrier Detect CD1 Demodulator RD1 DG AIN Receive Filter SW Cont. RD2 ROM CD2 FT AO Transmit Filter Modulator DTE Interface RD XD RS1 X1 OSC X2 Clock Gen. Loop Test CS CLK TS1(MSM6927RS)/ TS (MSM6947RS) TS2(MSM6927RS)/ ATE(MSM6947RS) RS2 CC Delay LT SQ 2/31 ¡ Semiconductor MSM6927/6947 PIN CONFIGURATION (TOP VIEW) TS2 (MSM6927RS) 28 ATE (MSM6947RS) 27 TS1 (MSM6927RS) TS (MSM6947RS) 26 VD X1 1 X2 2 CLK 3 LT 4 25 AO CC 5 24 VA CS 6 23 FT RS1 7 22 SQ RS2 8 21 AIN XD 9 20 SG1 RD 10 19 AG CD1 11 18 SG2 CD2 12 17 CDR2 RD1 13 16 CDR1 RD2 14 15 DG 28-Pin Plastic DIP Note: All pin descriptions except No. 27 pin and No. 28 pin are same for both MSM6927RS and MSM6947RS. 3/31 34 AO 39 VA* TS2 (MSM6927GS-K) 38 ATE (MSM6947GS-K) 37 NC TS1 (MSM6927GS-K) 36 TS (MSM6947GS-K) 35 VD 40 NC 42 X2 41 X1 MSM6927/6947 44 LT 43 CLK ¡ Semiconductor NC 1 33 VA CC 2 32 FT CS 3 31 SQ RS1 4 30 NC NC 5 29 NC NC 6 28 NC NC 7 27 NC RS2 8 26 AIN SG2 22 CDR1 20 CDR2 21 23 AG NC 18 DG 19 NC 11 RD2 16 VA* 17 24 SG1 CD2 13 RD1 14 NC 15 25 NC CD1 12 XD 9 RD 10 44-Pin Plastic QFP Notes: All pin description except No. 36 pin and No. 28 pin are same for both MSM6927GS-K and MSM6947GS-K. *: Both No. 17 pin and No. 39 pin are set to be at VA level by setting No. 33 pin at VA level. NC: No connect pin 4/31 ¡ Semiconductor MSM6927/6947 PIN DESCRIPTIONS Power Name Pin No. RS GS-K I/O Description DG 15 19 — Ground reference of VD (digital ground) AG 19 23 — Ground reference of VA (digital ground) VA 24 33 — Supply voltage (+12 V nominal) VD 26 35 — Supply voltage (+5 V nominal) Clocks Name Pin No. RS GS-K I/O X1 1 41 — X2 2 42 — CLK 3 43 O Description Master clock timing is provided by either a series resonant crystal (3.579545 MHz ±0.01%) connected across X1 and X2, or by an external TTL/CMOS clock driving X2 with AC coupling. In this latter case, X1 is left unconnected. See Fig. 10. 873.9 Hz clock output. This clock is used to implement external delay circuits etc. 5/31 ¡ Semiconductor MSM6927/6947 Control Name Pin No. RS GS-K I/O Description Digital loop back test. During digital "High", any data sent on the XD pin will appear on the RD pin, and any data sent on the RS1 pin will immediately appear on the CS pin. Any data demodulated from the received carrier on the AIN pin will be the modulated data to implement the transmitted carrier. In this case, sending the transmitted carrier to the phone line depends on the CC, but never on RS1. During digital loop back test, the data on this pin becomes a control signal for sending the transmitted carrier to the phone line in place of RS1. LT 4 44 I CC 5 2 I RS2 8 8 I When an external circuit gives the RS/CS delay time which is not within the device as required, this pin should be connected to the external circuit output. See Fig. 11-1 or Fig. 11-2 for MSM6927, MSM6947 respectively. O The fast carrier detection output. This pin is internally connected to the input of the built-in carrier detect delay circuit. When an external delay circuit provides the delay time which is not within the device as required, the CD1 should be connected to the external circuit input. See Fig. 11-1 or Fig. 11-2 for MSM6927, MSM6947 respectively. CD1 11 12 CD2 12 13 I/O RD1 13 14 O RD2 14 16 I CDR1 16 20 O CDR2 17 21 I SQ 22 31 I FT 23 32 I When an external circuit gives the carrier detect delay time which is not within the device as required, this pin becomes the input pin for the external circuit output signal. In other cases (when using the delay time within the device, the data on the TS1 (TS) or TS2 is not digital "High"), this pin becomes the Carrier detect signal output. The RD1 data is demodulated data from the received carrier and the RD2 is the input of the following logic circuits referred to in Fig. 12-1and Fig. 12-2. for MSM6927 and MSM6947, respectively Usually, the RD1 data is input directly to RD2. In some cases, as input data to RD2, the data that is controlled by NCU (Network control unit) etc. may be required in stead of the RD1 data. These two pins are the output (CRD1) and inverting input (CDR2) of the buffer operational amplifier of which the noninverting input is connected to the built-in voltage reference, stabilized to variations in the supply voltage and temperature. See Fig. 13. An adequate carrier-detect level can be set by selecting the ratio of R8 to R9. Therefore, the loss in the received carrier level by phone-line transformer can be compensated by adjusting the ratio of R8 to R9. R8 + R9 should be greater than 50 kW. When the data rate is 1200 bps and in half duplex mode on two-wire facilities, the delay function called as receiver-squelch is required. In case of four wire facilities, this function is not usually required. When a digital "High" is input to the SQ pin, this function is omitted. This pin may be used for device tests only. During digital "High", the AO pin will be connected to receiving filter output instead of transmitting filter output. 6/31 ¡ Semiconductor MSM6927/6947 Both MSM6927RS (or GS-K) and MSM6947RS (or GS-K) have 28 (or 44) pins. The pin descriptions for these 28 (or 44) pins are same except those for No. 27 (or No. 36) pin and No. 28 (or No. 38). The pin descriptions for No. 27 (or No. 36) pin and No. 28 (or No. 38) pin are described as follows. MSM6927 Name Pin No. RS GS-K I/O TS1 27 36 I TS2 28 38 I Description RS/CS delay and carrier detect delay options referred to chapter about timing characteristics are selected by TS1 and TS2 inputs. Be careful that each delay can not be individually selected. If another delay time than the ones within the device are required as an option, input a digital "High" to the TS1 and TS2 pin and implement the external delay circuits to obtain the desired delay characteristics. In this case, the CD2 pin becomes not only the input for the external circuit output signal, but also the Carrier detect output. See Fig. 11-1. MSM6947 Name Pin No. RS GS-K I/O Description TS 27 36 I When a digital "Low" is input to the TS pin, the built-in RS/CS, carrier detect and receiver-squelch delay are provided. If another delay time is required, it can be implemented by inputting a digital "High" to this pin and incorporates the external delay circuits. In this case, the CD2 pin becomes not only the input for the external circuit output signal, but also the Carrier detect output. See Fig. 11-2. ATE 28 38 I Answer tone enable input. When a digital "Low" is input to this pin and the RS1 pin is in the digital "Low" level, the Answer Tone (to 2025 Hz) is sent over the phone line via the AO pin. 7/31 ¡ Semiconductor MSM6927/6947 Input/Output Name CS Pin No. RS GS-K 6 3 I/O O Description Clear to send signal output. The digital "High" level indicates the "OFF" state and digital "Low" indicates the "ON" state. This output goes "Low" at the end of a delay (RS/CS delay) initiated when RS1 (Request to send) goes "Low". Request to send signal input. The digital "High" level indicates the "OFF" state. The digital "Low" level indicates the "ON" state and instructs the modem to enter the transmit mode. This input must remain "Low" for the duration of data transmission. "High" turns the transmitter off. This is digital data to be modulated and transmitted via AO. Digital "High" will be transmitted as "Mark". Digital "Low" will be transmitted as "Space". No signal appears at AO unless RS1 is "Low". Digital data demodulated from AIN is serially available at this output. Digital "High" indicates "Mark" and digital "Low" indicates "Space". For example, under the following condition, this output is forced to be "Mark" state because the data may be invalid. • When CD2 (Carrier detect) is in the "OFF" state. • When SQ is in digital "Low" (two-wire facilities) and RS1 is in the "ON" state. • During the receive data squelch delay at half duplex operation on two wire facilities. RS1 7 4 I XD 9 9 I RD 10 10 O SG2 18 22 O SG1 20 24 O AIN 21 26 I This is the input for the analog signal from the phone line. The modem extracts the information in this modulated carrier and converts it into a serial data stream for presentation at RD output. AO 25 34 O This analog output is the modulated carrier to be conditioned and sent over the phone line. The SG1 and ST2 are built-in analog signal grounds. SG2 is used only for Carrier detect function. The DC voltage of SG1 is approximately 6 V, so the analog line interface must be implemented by AC coupling. See Fig. 9. To make impedance lower and ensure the device performance, it is necessary to put bypass capacitors on SG1 and SG2 in close physical proximity to the device. 8/31 ¡ Semiconductor MSM6927/6947 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition VD Analog Input Voltage *1 VIA Digital Input Voltage *2 VID Unit –0.3 to 15 VA Power Supply Voltage Rating Ta = 25°C With respect to AG or DG –0.3 to 7 –0.3 to VA + 0.3 V –0.3 to VD + 0.3 Operating Temperature Top — 0 to +70 Storage Temperature TSTG — –55 to 150 *1 *2 CDR2, AIN *3 X1, LT, CC, RS1, RS2, XD, CD2, RD2, SQ, FT, TS1 (TS), TS2 (ATE) *3 CD2 is I/O terminal °C 9/31 ¡ Semiconductor MSM6927/6947 RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Symbol Condition Min. Typ. Max. VA With respect to AG 10.8 12.0 13.2 VD With respect to DG 4.75 5.00 5.25 Unit V AG, DG — — 0 — Operating Temperature Top — 0 — 70 °C CRYSTAL — — — 3.579545 — MHz R1 — Transformer impedance = 600 W — 600 — W R2 — — 51 — R3 — — 51 — R4 — — 51 — R5 — — 51 — R6 — — 51 — R7 — — 51 — R8 — — 33 — R9 — 51 — C0, C1 — — — 0.047 — C2 — — 2.2 — C3 — C4 — C5 — — C6 — — 22 — — 0.01 — — — 10 — — 10 — kW mF Application circuits using above conditions are provided in Fig. 8. 10/31 ¡ Semiconductor MSM6927/6947 ELECTRICAL CHARACTERISTICS DC and Digital Interface Characteristics (VA = 12 V ±10%, VD = 5 V ±5%, Ta = 0 to 70°C) Parameter Power Supply Current Input Leakage Currnet *1 Input Voltage *1 Output Voltage *2 Symbol Condition Min. Typ. Max. IA — 7.5 15.0 ID Ordinary operation — 1.0 2.0 IIL VI = 0 V –10 — 10 IIH VI = VD –10 — 10 VIL — 0 — 0.8 VIH — 2.2 — VD VOL IOL = 1.6 mA 0 — 0.4 VOH IOH = 400 mA 0.8 ¥ VD — VD Unit mA mA V *3 *1 LT, CC, RS1, RS2, XD, CD2, RD2, SQ, FT, TS1 (TS), TS2 (ATE) *3 *2 CLK, CS, RD, CD1, CD2, RD1 *3 CD2 is I/O terminal. 11/31 ¡ Semiconductor MSM6927/6947 Analog Interface Characteristics 1. MSM6927 Transmit carrier out (AO) (VA = 12 V ±10%, VD = 5 V ±5%, Ta = 0 to 70°C) Parameter Carrier Frequency Symbol Mark 1 fM Space 0 fS Condition Min. Typ. Max. 1290 1300 1310 2090 2100 2100 — — 200 W fCRYSTAL = 3.579545 MHz Unit Hz Output Resistance ROXA Load Resistance RLXA — 50 — — kW Load Capacitance CLXA — — — 100 pF Transmit Level VOXA — 4 6 8 *1 dBm VA –1 2 VA 2 VA +1 2 V — Output Offset Voltage VOSX — Out-of-Band Energy (Referred to Carrier Level) EOX C1 = 0.047 mF Symbol Condition Min. Typ. Max. Unit RIRA — 100 — — kW — –48 Refer to Fig. 1 dB Receive carrier input (AIN) Parameter Input Resistance Receive Signal Level Range Carrier Detect Level Carrier Detect Hysteresis VIRA ON VCD ON OFF VCD OFF HYS — –6 R8 = 33 kW *2 R9 = 51 kW — — –43 –48 — — VCD ON – VCD OFF 2 — — dB *1 dBm Receive filter Parameter Group Delay Distortion Symbol Condition Min. Typ. Max. Unit DDL 1100 to 2300 Hz — 210 — ms Notes: *1 0 dBm = 0.775 Vrms *2 The resistor values are typical 12/31 ¡ Semiconductor MSM6927/6947 0 2 4 6 8 10 12 14 16 kHz 0 –20 –40 –60 dB Figure 1 MSM6927 Out-of-Band Energy Referred to Carrier Level (C1 = 0.047 mF) 13/31 ¡ Semiconductor MSM6927/6947 –20 –2 –10 –30 –3 –40 GAIN (dB) –1 –50 –20 GAIN (dB) 0 –60 –70 –80 –30 1k 10 k FREQ (Hz) Figure 2 MSM6927 Transmit Filter 0 1k 10 k FREQ (Hz) –10 GAIN (dB) –20 –30 –40 –50 –60 Figure 3 MSM6927 Receive Filter 14/31 ¡ Semiconductor MSM6927/6947 2. MSM6947 Transmit carrier out (AO) (VA = 12 V ±10%, VD = 5 V ±5%, Ta = 0 to 70°C) Parameter Carrier Frequency Symbol Mark 1 Space 0 Condition fM Min. Typ. Max. 1190 1200 1210 Unit fS fCRYSTAL = 3.579545 MHz 2190 2200 2210 fA ATE = "0" 2019 2025 2031 Output Resistance ROXA — — — 200 W Load Resistance RLXA — 50 — — kW Load Capacitance CLXA — — — 100 pF Transmit Level VOXA — 4 6 8 *1 dBm VA –1 2 VA 2 VA +1 2 V Answer Tone Frequency Hz Output Offset Voltage VOSX — Out-of-Band Energy (Referred to Carrier Level) EOX C1 = 0.047 mF Symbol Condition Min. Typ. Max. Unit Input Resistance RIRA — 100 — — kW Receive Signal Level Range VIRA — –48 — –6 dB Refer to Fig. 4 Receive carrier input (AIN) Parameter Carrier Detect Level Carrier Detect Hysteresis ON VCD ON OFF VCD OFF HYS R8 = 33 kW *2 R9 = 51 kW — — –43 –48 — — VCD ON – VCD OFF 0.5 — — dB *1 dBm Receive Filter Parameter Group Delay Distortion Symbol Condition Min. Typ. Max. Unit DDL 1100 to 2300 Hz — 210 — ms Notes: *1 0 dBm = 0.775 Vrms *2 The resistor values are typical 15/31 ¡ Semiconductor MSM6927/6947 0 2 3.4 4 6 8 10 12 14 16 200 kHz 0 –20 –25 dB/ OC –40 –60 15 TAV E –55 dB Figure 4 MSM6947 Out-of-Band Energy Referred to Carrier Level (C1 = 0.047 mF) 16/31 ¡ Semiconductor MSM6927/6947 0 –1 –20 –2 –30 –10 GAIN (dB) –50 –20 GAIN (dB) –40 –3 –60 –70 –80 –30 1k 10 k FREQ (Hz) Figure 5 MSM6947 Transmit Filter 0 1k 10 k FREQ (Hz) –10 GAIN (dB) –20 –30 –40 –50 –60 Figure 6 MSM6947 Receive Filter 17/31 ¡ Semiconductor MSM6927/6947 Demodulated Bit Characteristics (VA = 12 V ±10%, VD = 5 V ±5%, Ta = 0 to 70°C) Parameter Peak Intersymbol Distortion Bit Error Rate Symbol Condition Min. Typ. Max. Unit ID Back-to-back over input signal range –6 to –40 dBm. 511-bit test pattern. — 9 — % — 10–3 — BER Back-to-backwith 0.3 to 3.4 kHz 8 dB flat noise. Receive signal S/N level –25 dBm. 11 dB 511-bit test pattern — 10–5 — Timing Characteristics 1. MSM6927 (VA = 12 V ±10%, VD = 5 V ±5%, Ta = 0 to 70°C) Parameter Symbol TRC ON RS/CS Delay Time TRC OFF CD/ON Delay Time CD/OFF Delay Time Soft Turn-OFF Time Receive Data Squelch Delay Time Condition RS1 = "0" Æ CS = "0" RS1 = "1" Æ CS = "1" TCD ON — TCD OF — TST TSQ TS2 TS1 Min. Typ. Max. 0 0 195 200 205 0 1 25 30 35 1 0 65 70 75 1 1 * * 0 — 0.5 0 0 10 — 25 0 1 10 — 25 1 0 10 — 25 1 1 0 0 5 — 15 0 1 5 — 15 1 0 5 — 15 1 1 Unit External delay timer ms External delay timer External delay timer — * * — 10 — SQ = "0" 0 0 145 150 155 RS1 = "1" 0 1 145 150 155 Æ RD = "1" 1 0 35 40 45 Hold 1 1 External delay timer Refer to Fig. 7 Notes: *: Irrespective of I/O condition 18/31 ¡ Semiconductor MSM6927/6947 2. MSM6947 (VA = 12 V ±10%, VD = 5 V ±5%, Ta = 0 to 70°C) Parameter Symbol Condition TS Min. Typ. Max. TRC ON RS1 = "0" Æ CS = "0" 0 175 180 185 TRC OFF RS1 = "1" Æ CS = "1" CD/ON Delay Time TCD ON — CD/OFF Delay Time TCD OF — Soft Turn-OFF Time TST RS/CS Delay Time — SQ = "0" Receive Data Squelch Delay Time TSQ RS1 = "1" Æ RD = "1" Hold 1 External delay timer * 0 — 0.5 0 15 — 35 1 0 1 ms External delay timer 10 — 20 External delay timer * — 10 — 0 — 156 — 1 Unit External delay timer Refer to Fig. 8 Notes: *: Irrespective of I/O condition +: Reserved 19/31 ¡ Semiconductor MSM6927/6947 TIMING DIAGRAM RS1 CS TRCON TRCOFF AO TST "Mark" hold TSQ AIN TCDON TCDOFF CD2 Figure 7 MSM6927/6947 Timing Diagram 20/31 ¡ Semiconductor MSM6927/6947 Notes: 1. 2. 3. 4. CD XD RD CS RS Test Data 2-Wire 4-Wire VD Crystal 1 2 VD 3 4 5 Control 6 7 8 9 10 11 12 13 14 X1 X2 CLK LT CC CS RS1 RS2 XD RD CD1 CD2 RD1 RD2 TS2 28 TS1 27 VD 26 AO 25 VA 24 FT 23 + SQ 22 – AIN 21 SG1 20 C3 AG 19 C4 SG2 18 R8 CDR2 17 R9 CDR1 16 DG 15 DG AG C5 VA VD DG or VD + – C6 R7 R6 R4 C0 – + R3 – + R5 R2 R1 C2 1. MSM6927RS C1 Phone Line APPLICATION CIRCUIT The crystal should be wired in close physical proximity to the device. High level signals should not be routed next to low level signals. Bypass capacitors on VA, SG1, and SG2 should be as close to the device as possible. AG and DG should be connected as close to the system ground as possible. Figure 8-1 Application Circuit Using MSM6927RS 21/31 ¡ Semiconductor MSM6927/6947 C1 R6 C6 + – VD DG or VD Notes: 1. 2. 3. 4. CD XD RD CS RS Test Data VD Crystal 1 2 VD 3 4 5 Control 6 7 8 9 10 11 12 13 14 X1 X2 CLK LT CC CS RS1 RS2 XD RD CD1 CD2 RD1 RD2 ATE 28 TS 27 VD 26 AO 25 VA 24 FT 23 + SQ 22 – AIN 21 SG1 20 C3 AG 19 C4 SG2 18 R8 CDR2 17 R9 CDR1 16 DG 15 DG AG C5 VA ANS. Tone 2-Wire R7 Data VD 4-Wire R4 C0 – + R3 – + R5 R2 R1 C2 Phone Line 2. MSM6947RS The crystal should be wired in close physical proximity to the device. High level signals should not be routed next to low level signals. Bypass capacitors on VA, SG1, and SG2 should be as close to the device as possible. AG and DG should be connected as close to the system ground as possible. Figure 8-2 Application Circuit Using MSM6947RS 22/31 ¡ Semiconductor MSM6927/6947 +6 dBm R5 R4 AO 25 – + SG1 20 C3 AIN 21 AG 19 0 dBm R2 R3 R7 –6 dBm R1 C2 – + 600 W : 600 W Phone Line C1 R6 C0 –6 dBm 0 dBm Figure 9 MSM6927RS/MSM6947RS Application C0, C1 0.047 mF R2 C2 2.2 mF C3 1 mF R1 600 W 51 kW R6 R3 51 kW R7 51 kW R4 51 kW R8 (33 kW) Carrier detect level R5 (51 kW) Transmit signal level R9 51 kW (51 kW) Receive signal level Note: The signal level on the AIN pin should not exceed –6 dBm. VD External Oscillator *1 200 pF X2 GATE *2 X1 3.58 MHz *1 TTL or Hi-Speed CMOS GATE *2 Left unconnected External Oscillator Connection Figure 10 23/31 ¡ Semiconductor MSM6927/6947 RS RS1 RS2 *1 R CK 4020 R *1 CK 4020 (A) *2 R *1 CK 4020 *1 CK 4020 TS1 VD TS2 (B) Q Q R VD CK CD1 D *2 (C) CD2 CD 873.9 Hz CLK (D) (A) RS/CS delay, (B) Receive-squelch delay, (C) CD/ON delay, (D) CD/OFF delay Note: Supply voltage equals VD for all gates. *1: The desired delay can be realized by selecting the appropriate bits from 4020's outputs. The number of the bits is not always 3. Each delay can be set differently from built-in delays. *2: In case that the Receiver-squelch delay is unnecessary, circuit (B) and this OR gate should be omitted and the output of the NOR gate should be connected to CD2 directly. Figure 11-1 MSM6927 External Delay Connection 24/31 ¡ Semiconductor MSM6927/6947 RS RS1 RS2 *1 R CK 4020 R *1 CK 4020 (A) *2 R *1 CK 4020 *1 CK 4020 TS1 VD TS2 (B) Q Q R VD CK CD1 D *2 (C) CD2 CD 873.9 Hz CLK (D) (A) RS/CS delay, (B) Receive-squelch delay, (C) CD/ON delay, (D) CD/OFF delay Note: Supply voltage equals VD for all gates. *1: The desired delay can be realized by selecting the appropriate bits from 4020's outputs. The number of the bits is not always 3. Each delay can be set differently from built-in delays. *2: In case that the Receiver-squelch delay is unnecessary, circuit (B) and this OR gate should be omitted and the output of the NOR gate should be connected to CD2 directly. Figure 11-2 MSM6947 External Delay Connection 25/31 ¡ Semiconductor TS1 MSM6927/6947 SW Control TS2 LT RS1 CS RS2 RS/CS Delay CC XD RD Modulator Transmit Filter AO DeModulator Receive Filter AIN CD2 CD1 CD ON CD OFF Delay RD Squelch Delay Carrier Detect SQ RD2 RD1 Squelch Figure 12-1 MSM6927 Equivalent Logic Interface of the Integrated Modem 26/31 ¡ Semiconductor TS1 MSM6927/6947 SW Control TS2 LT RS1 CS RS2 RS/CS Delay CC XD RD Modulator Transmit Filter AO DeModulator Receive Filter AIN CD2 CD1 CD ON CD OFF Delay RD Squelch Delay Carrier Detect SQ RD2 RD1 Squelch Figure 12-2 MSM6947 Equivalent Logic Interface of the Integrated Modem 27/31 ¡ Semiconductor Carrier MSM6927/6947 COMP Carrier Detect AC/DC Converter CD1 SG2 + – CDR1 VREF R9 CDR2 R8 SG2 (R8 + R9) ≥ 50 kW Figure 13 External Resistor Connection for the Setting of Carrier Detect Level 28/31 ¡ Semiconductor MSM6927/6947 PACKAGE DIMENSIONS (Unit : mm) DIP28-P-600-2.54 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 4.30 TYP. 29/31 ¡ Semiconductor MSM6927/6947 (Unit : mm) QFP44-P-910-0.80-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.35 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 30/31 ¡ Semiconductor MSM6927/6947 (Unit : mm) QFP44-P-910-0.80-2K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Epoxy resin 42 alloy Solder plating 5 mm or more Package weight (g) 0.41 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 31/31