POINN TIC226M

TIC226 SERIES
SILICON TRIACS
Copyright © 1997, Power Innovations Limited, UK
●
8 A RMS, 70 A Peak
●
Glass Passivated Wafer
●
400 V to 800 V Off-State Voltage
●
Max IGT of 50 mA (Quadrants 1 - 3)
APRIL 1971 - REVISED MARCH 1997
TO-220 PACKAGE
(TOP VIEW)
MT1
1
MT2
2
G
3
Pin 2 is in electrical contact with the mounting base.
MDC2ACA
absolute maximum ratings over operating case temperature (unless otherwise noted)
RATING
SYMBOL
VALUE
TIC226D
TIC226M
Repetitive peak off-state voltage (see Note 1)
TIC226S
UNIT
400
600
VDRM
V
700
TIC226N
800
IT(RMS)
8
A
Peak on-state surge current full-sine-wave (see Note 3)
ITSM
70
A
Peak on-state surge current half-sine-wave (see Note 4)
ITSM
80
A
Peak gate current
IGM
±1
A
W
Full-cycle RMS on-state current at (or below) 85°C case temperature (see Note 2)
Peak gate power dissipation at (or below) 85°C case temperature (pulse width ≤ 200 µs)
PGM
2.2
PG(AV)
0.9
W
Operating case temperature range
TC
-40 to +110
°C
Storage temperature range
Tstg
-40 to +125
°C
TL
230
°C
Average gate power dissipation at (or below) 85°C case temperature (see Note 5)
Lead temperature 1.6 mm from case for 10 seconds
NOTES: 1. These values apply bidirectionally for any value of resistance between the gate and Main Terminal 1.
2. This value applies for 50-Hz full-sine-wave operation with resistive load. Above 85°C derate linearly to 110°C case temperature at
the rate of 320 mA/°C.
3. This value applies for one 50-Hz full-sine-wave when the device is operating at (or below) the rated value of on-state current.
Surge may be repeated after the device has returned to original thermal equilibrium. During the surge, gate control may be lost.
4. This value applies for one 50-Hz half-sine-wave when the device is operating at (or below) the rated value of on-state current.
Surge may be repeated after the device has returned to original thermal equilibrium. During the surge, gate control may be lost.
5. This value applies for a maximum averaging time of 20 ms.
electrical characteristics at 25°C case temperature (unless otherwise noted)
PARAMETER
IDRM
IGTM
VGTM
MIN
TEST CONDITIONS
Repetitive peak
VD = rated VDRM
off-state current
IG = 0
TYP
TC = 110°C
MAX
UNIT
±2
mA
Vsupply = +12 V†
RL = 10 Ω
tp(g) > 20 µs
2
50
Peak gate trigger
Vsupply = +12 V†
RL = 10 Ω
tp(g) > 20 µs
-12
-50
current
Vsupply = -12 V†
RL = 10 Ω
tp(g) > 20 µs
-9
-50
Vsupply = -12 V†
RL = 10 Ω
tp(g) > 20 µs
20
Vsupply = +12 V†
RL = 10 Ω
tp(g) > 20 µs
0.7
2
Peak gate trigger
Vsupply = +12 V†
RL = 10 Ω
tp(g) > 20 µs
-0.8
-2
voltage
Vsupply = -12 V†
RL = 10 Ω
tp(g) > 20 µs
-0.8
-2
Vsupply = -12 V†
RL = 10 Ω
tp(g) > 20 µs
0.9
2
mA
V
† All voltages are with respect to Main Terminal 1.
PRODUCT
INFORMATION
Information is current as of publication date. Products conform to specifications in accordance
with the terms of Power Innovations standard warranty. Production processing does not
necessarily include testing of all parameters.
1
TIC226 SERIES
SILICON TRIACS
APRIL 1971 - REVISED MARCH 1997
electrical characteristics at 25°C case temperature (unless otherwise noted) (continued)
PARAMETER
VTM
Peak on-state voltage
IH
Holding current
IL
Latching current
dv/dt(c)
Critical rise of commutation voltage
MAX
UNIT
V
IG = 50 mA
(see Note 6)
±1.6
±2.1
Vsupply = +12 V†
IG = 0
Init’ ITM = 100 mA
5
30
Vsupply = -12 V†
IG = 0
Init’ ITM = -100 mA
-9
-30
Vsupply = +12 V†
off-state voltage
TYP
ITM = ±12 A
mA
50
(see Note 7)
Vsupply = -12 V†
Critical rate of rise of
dv/dt
MIN
TEST CONDITIONS
mA
-50
VDRM = Rated VDRM
IG = 0
TC = 110°C
VDRM = Rated VDRM
ITRM = ±12 A
TC = 85°C
±100
V/µs
±5
V/µs
† All voltages are with respect to Main Terminal 1.
NOTES: 6. This parameter must be measured using pulse techniques, tp = ≤ 1 ms, duty cycle ≤ 2 %. Voltage-sensing contacts separate from
the current carrying contacts are located within 3.2 mm from the device body.
7. The triacs are triggered by a 15-V (open-circuit amplitude) pulse supplied by a generator with the following characteristics:
RG = 100 Ω, tp(g) = 20 µs, tr = ≤ 15 ns, f = 1 kHz.
thermal characteristics
MAX
UNIT
RθJC
Junction to case thermal resistance
PARAMETER
MIN
TYP
1.8
°C/W
RθJA
Junction to free air thermal resistance
62.5
°C/W
TYPICAL CHARACTERISTICS
GATE TRIGGER VOLTAGE
vs
GATE TRIGGER CURRENT
vs
CASE TEMPERATURE
100
Vsupply IGTM
VAA = ± 12 V
+
+
-
RL = 10 Ω
tp(g) = 20 µs
+
+
10
1
0·1
-60
-40
-20
20
40
60
80
100
120
VAA = ± 12 V
Vsupply IGTM
+
+
-
RL = 10 Ω
tp(g) = 20 µs
+
+
1
0·1
-60
-40
-20
0
20
40
60
80
TC - Case Temperature - °C
TC - Case Temperature - °C
Figure 1.
Figure 2.
PRODUCT
2
0
TC01AB
10
VGT - Gate Trigger Voltage - V
IGT - Gate Trigger Current - mA
1000
CASE TEMPERATURE
TC01AA
INFORMATION
100
120
TIC226 SERIES
SILICON TRIACS
APRIL 1971 - REVISED MARCH 1997
TYPICAL CHARACTERISTICS
HOLDING CURRENT
vs
CASE TEMPERATURE
1000
TC01AD
VGF - Gate Forward Voltage - V
IG = 0
Initiating ITM = 100 mA
100
10
1
0·1
-60
-40
TC01AC
10
VAA = ± 12 V
Vsupply
+
IH - Holding Current - mA
GATE FORWARD VOLTAGE
vs
GATE FORWARD CURRENT
-20
0
20
40
60
80
100
1
0·1
QUADRANT 1
0·01
0·0001
0·001
120
TC - Case Temperature - °C
1
LATCHING CURRENT
vs
SURGE ON-STATE CURRENT
vs
CYCLES OF CURRENT DURATION
Vsupply IGTM
+
+
-
TC01AE
10
0
TC ≤ 85 °C
VAA = ± 12 V
+
+
100
-20
TI01AA
100
ITSM - Peak Full-Sine-Wave Current - A
IL - Latching Current - mA
0·1
Figure 4.
CASE TEMPERATURE
-40
0·01
IGF - Gate Forward Current - A
Figure 3.
1000
1
-60
IA = 0
TC = 25 °C
20
40
60
80
100
120
No Prior Device Conduction
Gate Control Guaranteed
10
1
1
10
100
TC - Case Temperature - °C
Consecutive 50-Hz Half-Sine-Wave Cycles
Figure 5.
Figure 6.
PRODUCT
1000
INFORMATION
3
TIC226 SERIES
SILICON TRIACS
APRIL 1971 - REVISED MARCH 1997
TYPICAL CHARACTERISTICS
MAX RMS ON-STATE CURRENT
vs
CASE TEMPERATURE
RMS ON-STATE CURRENT
TI01AB
P(av) - Maximum Average Power Dissipated - W
10
IT(RMS) - Maximum On-State Current - A
MAX AVERAGE POWER DISSIPATED
vs
9
8
7
6
5
4
3
2
1
32
TI01AC
TJ = 110 °C
28
Conduction Angle = 360 °
Above 8 A rms
See ITSM Figure
24
20
16
12
8
4
0
0
0
25
50
75
100
125
150
0
2
4
6
8
10
12
TC - Case Temperature - °C
IT(RMS) - RMS On-State Current - A
Figure 7.
Figure 8.
14
16
PARAMETER MEASUREMENT INFORMATION
VAC
VAC
L1
ITRM
IMT2
IMT2
C1
50 Hz
VMT2
VDRM
DUT
RG
See
Note A
R1
VMT2
IG
10%
dv/dt
63%
IG
NOTE A: The gate-current pulse is furnished by a trigger circuit which presents essentially an open circuit between pulses. The pulse is timed
so that the off-state-voltage duration is approximately 800 µs.
Figure 9.
PRODUCT
4
INFORMATION
PMC2AA
TIC226 SERIES
SILICON TRIACS
APRIL 1971 - REVISED MARCH 1997
MECHANICAL DATA
TO-220
3-pin plastic flange-mount package
This single-in-line package consists of a circuit mounted on a lead frame and encapsulated within a plastic
compound. The compound will withstand soldering temperature with no deformation, and circuit performance
characteristics will remain stable when operated in high humidity conditions. Leads require no additional
cleaning or processing when used in soldered assembly.
TO220
4,70
4,20
ø
10,4
10,0
3,96
3,71
1,32
1,23
2,95
2,54
see Note B
6,6
6,0
15,90
14,55
see Note C
6,1
3,5
1,70
1,07
0,97
0,61
1
2
14,1
12,7
3
2,74
2,34
5,28
4,88
VERSION 1
0,64
0,41
2,90
2,40
VERSION 2
ALL LINEAR DIMENSIONS IN MILLIMETERS
NOTES: A. The centre pin is in electrical contact with the mounting tab.
B. Mounting tab corner profile according to package version.
C. Typical fixing hole centre stand off height according to package version.
Version 1, 18.0 mm. Version 2, 17.6 mm.
PRODUCT
MDXXBE
INFORMATION
5
TIC226 SERIES
SILICON TRIACS
APRIL 1971 - REVISED MARCH 1997
IMPORTANT NOTICE
Power Innovations Limited (PI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to verify, before placing orders, that the
information being relied on is current.
PI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with PI's standard warranty. Testing and other quality control techniques are utilized to the extent PI
deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except as mandated by government requirements.
PI accepts no liability for applications assistance, customer product design, software performance, or infringement
of patents or services described herein. Nor is any license, either express or implied, granted under any patent
right, copyright, design right, or other intellectual property right of PI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.
PI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE
SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS.
Copyright © 1997, Power Innovations Limited
PRODUCT
6
INFORMATION