TISP61089A DUAL FORWARD-CONDUCTING P-GATE THYRISTORS PROGRAMMABLE OVERVOLTAGE PROTECTORS Copyright © 1999, Power Innovations Limited, UK JUNE 1999 PROGRAMMABLE SLIC OVERVOLTAGE PROTECTION FOR LSSGR ‘1089 ● ● Dual Voltage-Programmable Protectors - Wide 0 to -110 V Programming Range - Low 5 mA max. Gate Triggering Current - High 150 mA min. Holding Current 1 8 K1 (Tip) 2 7 A (Ground) NC 3 6 A (Ground) (Ring) K2 4 5 K2 (Ring) (Tip) 2/10 µs 10/1000 µs ‘1089 TEST CLAUSE ITSP AND TEST # A 4.5.8 Second-Level 1 120 4.5.7 First-Level 3 30 60 Hz POWER ‘1089 TEST CLAUSE ITSM FAULT TIME AND TEST # A K1 (Gate) G Rated for LSSGR ‘1089 Conditions WAVE SHAPE ● D PACKAGE (TOP VIEW) MD6XAN NC - No internal connection Terminal typical application names shown in parenthesis P PACKAGE (TOP VIEW) 100 ms 4.5.13 Second-Level 2 10 1s 4.5.13 Second-Level 2 4.4 (Tip) 5s 4.5.13 Second-Level 2 2.1 (Gate) G 300 s 4.5.13 Second-Level 1 0.84 900 s 4.5.13 Second-Level 1 0.83 2/10 Protection Voltage Specified ELEMENT FIRST-LEVEL SECOND-LEVEL V @ 56 A V @ 100 A 6 8 -57 -60 Diode Crowbar VGG = -48 V 1 8 K1 (Tip) 2 7 A (Ground) NC 3 6 A (Ground) (Ring) K2 4 5 K2 (Ring) MD6XAV NC - No internal connection Terminal typical application names shown in parenthesis device symbol K1 ● Also Rated for ITU-T 10/700 impulses ● Surface Mount and Through-Hole Options - TISP61089AP for Plastic DIP - TISP61089AD for Small-Outline - TISP61089ADR for Small-Outline Taped and Reeled K1 description G A K2 SD6XAE The TISP61089A is a dual forward-conducting Terminals K1, K2 and A correspond to the alternative buffered p-gate overvoltage protector. It is line designators of T, R and G or A, B and C. The negative protection voltage is controlled by the voltage, designed to protect monolithic SLICs (Subscriber VGG, applied to the G terminal. Line Interface Circuits) against overvoltages on the telephone line caused by lightning, a.c. power contact and induction. The TISP61089A limits voltages that exceed the SLIC supply rail voltage. The TISP61089A parameters are specified to allow equipment compliance with Bellcore GR-1089-CORE, Issue 1. The SLIC line driver section is typically powered from 0 V (ground) and a negative voltage in the region of -10 V to -100 V. The protector gate is connected to this negative supply. This references the protection (clipping) voltage to the negative supply voltage. As the protection voltage will then track the negative supply voltage the overvoltage stress on the SLIC is minimised. PRODUCT INFORMATION Information is current as of publication date. Products conform to specifications in accordance with the terms of Power Innovations standard warranty. Production processing does not necessarily include testing of all parameters. 1 TISP61089A DUAL FORWARD-CONDUCTING P-GATE THYRISTORS PROGRAMMABLE OVERVOLTAGE PROTECTORS JUNE 1999 Positive overvoltages are clipped to ground by diode forward conduction. Negative overvoltages are initially clipped close to the SLIC negative supply rail value. If sufficient current is available from the overvoltage, then the protector will crowbar into a low voltage on-state condition. As the overvoltage subsides the high holding current of the crowbar prevents d.c. latchup. The TISP61089A is intended to be used with a series combination of a 25 Ω or higher resistance and a suitable overcurrent protector. Power fault compliance requires the series overcurrent element to open-circuit or become high impedance (see Applications Information). For equipment compliant to ITU-T recommendations K20 or K21 only, the series resistor value is set by the power cross requirements. For K20 and K21, a minimum series resistor value of 10 Ω is recommended. These monolithic protection devices are fabricated in ion-implanted planar vertical power structures for high reliability and in normal system operation they are virtually transparent. The TISP61089A buffered gate design reduces the loading on the SLIC supply during overvoltages caused by power cross and induction. The TISP61089A is available in 8-pin plastic small-outline surface mount package and 8-pin plastic dual-inline package. absolute maximum ratings RATING SYMBOL VALUE UNIT Repetitive peak off-state voltage, IG = 0, -40°C ≤ TJ ≤ 85°C VDRM -120 V Repetitive peak gate-cathode voltage, VKA = 0, -40°C ≤ TJ ≤ 85°C VGKRM -120 V Non-repetitive peak on-state pulse current (see Notes 1 and 2) 10/1000 µs (Bellcore GR-1089-CORE, Issue 1, November 1994, Section 4) 5/320 µs (ITU-T recommendation K20 & K21, open-circuit voltage wave shape 10/700) 30 40 ITSP A 1.2/50 µs (Bellcore GR-1089-CORE, Issue 1, November 1994, Section 4, Alternative) 100 2/10 µs (Bellcore GR-1089-CORE, Issue 1, November 1994, Section 4) 120 Non-repetitive peak on-state current, 60 Hz (see Notes 1 and 2) 0.1 s 10 1s 4.4 ITSM 5s A 2.1 300 s 0.84 900 s 0.83 Non-repetitive peak gate current, 1/2 µs pulse, cathodes commoned (see Notes 1 and 2) IGSM 40 A Operating free-air temperature range TA -40 to +85 °C Junction temperature TJ -40 to +150 °C Tstg -40 to +150 °C Storage temperature range NOTES: 1. Initially the protector must be in thermal equilibrium with -40°C ≤ TJ ≤ 85°C. The surge may be repeated after the device returns to its initial conditions. 2. The rated current values may be applied either to the Ring to Ground or to the Tip to Ground terminal pairs. Additionally, both terminal pairs may have their rated current values applied simultaneously (in this case the Ground terminal current will be twice the rated current value of an individual terminal pair). Above 85°C, derate linearly to zero at 150°C lead temperature. recommended operating conditions MIN CG RS Gate decoupling capacitor 40 TISP61089A series resistor for first-level surge survival 25 PRODUCT 2 100 TISP61089A series resistor for first-level and second-level surge survival INFORMATION TYP 220 MAX UNIT nF Ω TISP61089A DUAL FORWARD-CONDUCTING P-GATE THYRISTORS PROGRAMMABLE OVERVOLTAGE PROTECTORS JUNE 1999 electrical characteristics, TJ = 25°C (unless otherwise noted) PARAMETER ID V(BO) VF VFRM IH TEST CONDITIONS Off-state current VD = VDRM, IG = 0 Breakover voltage Forward voltage MIN TJ = 85°C 2/10 µs, IT = -56 A, RS = 45 Ω, VGG = -48 V, CG = 220 nF -57 2/10 µs, IT = -100 A, RS = 50 Ω, VGG = -48 V, CG = 220 nF -60 1.2/50 µs, IT = -53 A, RS = 47 Ω, VGG = -48 V, CG = 220 nF -60 1.2/50 µs, IT = -96 A, RS = 52 Ω, VGG = -48 V, CG = 220 nF -64 IF = 5 A, tw = 200 µs 6 Peak forward recovery 2/10 µs, IF = 100 A, RS = 50 Ω, VGG = -48 V, CG = 220 nF 8 voltage 1.2/50 µs, IF = 53 A, RS = 47 Ω, VGG = -48 V, CG = 220 nF 8 1.2/50 µs, IF = 96 A, RS = 52 Ω, VGG = -48 V, CG = 220 nF 12 Holding current IT = -1 A, di/dt = 1A/ms, VGG = -48 V -50 µA V V mA TJ = 85°C -50 µA 5 mA Gate trigger current IT = 3 A, tp(g) ≥ 20 µs, VGG = -48 V VGT Gate trigger voltage IT = 3 A, tp(g) ≥ 20 µs, VGG = -48 V QGS Gate switching charge 1.2/50 µs, IT = 53 A, RS = 47 Ω, VGG = -48 V CG = 220 nF 2.5 f = 1 MHz, Vd = 1 V, IG = 0, (see Note 3) V -5 IGT NOTE µA -150 VGG = VGK = VGKRM, VKA = 0 state capacitance UNIT -5 TJ = 25°C Gate reverse current Anode-cathode off- MAX 3 2/10 µs, IF = 56 A, RS = 45 Ω, VGG = -48 V, CG = 220 nF IGKS CAK TYP TJ = 25°C 0.1 µA V µC VD = -3 V 100 pF VD = -48 V 50 pF 3: These capacitance measurements employ a three terminal capacitance bridge incorporating a guard circuit. The unmeasured device terminals are a.c. connected to the guard terminal of the bridge. thermal characteristics PARAMETER TEST CONDITIONS TA = 25 °C, EIA/JESD51-3 RθJA Junction to free air thermal resistance PRODUCT PCB, EIA/JESD51-2 environment, PTOT = 1.7 W MIN TYP MAX D Package 120 P Package 100 UNIT °C/W INFORMATION 3 TISP61089A DUAL FORWARD-CONDUCTING P-GATE THYRISTORS PROGRAMMABLE OVERVOLTAGE PROTECTORS JUNE 1999 PARAMETER MEASUREMENT INFORMATION +i Quadrant I IFSP (= |ITSP|) Forward Conduction Characteristic IFSM (= |ITSM|) IF VF VGK(BO) VGG -v VD ID I(BO) IH IS VT VS V(BO) +v IT ITSM Quadrant III ITSP Switching Characteristic -i Figure 1. VOLTAGE-CURRENT CHARACTERISTIC PRODUCT 4 INFORMATION PM6XAAA TISP61089A DUAL FORWARD-CONDUCTING P-GATE THYRISTORS PROGRAMMABLE OVERVOLTAGE PROTECTORS JUNE 1999 THERMAL INFORMATION ITSM(t) - Non-Repetitive Peak On-State Current - A NON-REPETITIVE PEAK ON-STATE CURRENT vs CURRENT DURATION TI6HAC 10 9 8 7 6 VGEN = 600 Vrms, 50/60 Hz RGEN = 1.4*VGEN/ITSM(t) EIA/JESD51-2 ENVIRONMENT EIA/JESD51-3 PCB TA = 25 °C 5 4 GROUND RETURN = 2xITSM(t) 3 2 1.5 1 0.9 0.8 0.7 0·1 1 10 100 t - Current Duration - s 1000 Figure 2. NON-REPETITIVE PEAK ON-STATE CURRENT AGAINST DURATION APPLICATIONS INFORMATION gated protectors This section covers three topics. Firstly, it is explained why gated protectors are needed. Second, the voltage limiting action of the protector is described. Third, an example application circuit is described. purpose of gated protectors Fixed voltage thyristor overvoltage protectors have been used since the early 1980s to protect monolithic SLICs (Subscriber Line Interface Circuits) against overvoltages on the telephone line caused by lightning, a.c. power contact and induction. As the SLIC was usually powered from a fixed voltage negative supply rail, the limiting voltage of the protector could also be a fixed value. The TISP1072F3 is a typical example of a fixed voltage SLIC protector. SLICs have become more sophisticated. To minimise power consumption, some designs automatically adjust the supply voltage, VBAT, to a value that is just sufficient to drive the required line current. For short lines the supply voltage would be set low, but for long lines, a higher supply voltage would be generated to drive sufficient line current. The optimum protection for this type of SLIC would be given by a protection voltage which tracks the SLIC supply voltage. This can be achieved by connecting the protection thyristor gate to the SLIC supply, Figure 3. This gated (programmable) protection arrangement minimises the voltage stress on the SLIC, no matter what value of supply voltage. PRODUCT INFORMATION 5 TISP61089A DUAL FORWARD-CONDUCTING P-GATE THYRISTORS PROGRAMMABLE OVERVOLTAGE PROTECTORS JUNE 1999 TIP WIRE 600 Ω SLIC TISP61089A Th4 R1 50 Ω GENERATOR SOURCE RESISTANCE R2 50 Ω 600 Ω SWITCHING MODE POWER SUPPLY Tx Th5 RING WIRE A.C. GENERATOR 0 - 600 Vrms IG C1 220 nF C2 ISLIC VBAT IBAT D1 AI6XAGA Figure 3. TISP61089A BUFFERED GATE PROTECTOR (SECTION 4.5.12 TESTING CONDITION) operation of gated protectors Figures 4. and 5. show how the TISP61089A limits negative and positive overvoltages. Positive overvoltages (Figure 5) are clipped by the antiparallel diodes in the TISP61089A and the resulting current is diverted to ground. Negative overvoltages (Figure 4.) are initially clipped close to the SLIC negative supply rail value (VBAT). If sufficient current is available from the overvoltage, then the protector (Th5) will crowbar into a low voltage on-state condition. As the overvoltage subsides the high holding current of the crowbar prevents d.c. latchup. The protection voltage will be the sum of the gate supply (V BAT) and the peak gate-cathode voltage (VGK(BO)). The protection voltage will be increased if there is a long connection between the gate decoupling capacitor, C1, and the gate terminal. During the initial rise of a fast impulse, the gate current (IG) is the same as the cathode current (IK). Rates of 70 A/µs can cause inductive voltages of 0.7 V in 2.5 cm of printed wiring track. To minimise this inductive voltage increase of protection voltage, the length of the capacitor to gate terminal tracking should be minimised. Inductive voltages in the protector cathode wiring will also increase the protection voltage. These voltages can be minimised by routing the SLIC connection through the protector as shown in Figure 3. SLIC PROTECTOR IK AI6XAHA IF Th5 TISP 61089A C1 220 nF 6 SLIC Th5 TISP 61089A IG VBAT C1 220 nF VBAT AI6XAIA Figure 4. NEGATIVE OVERVOLTAGE CONDITION PRODUCT SLIC PROTECTOR SLIC INFORMATION Figure 5. POSITIVE OVERVOLTAGE CONDITION TISP61089A DUAL FORWARD-CONDUCTING P-GATE THYRISTORS PROGRAMMABLE OVERVOLTAGE PROTECTORS JUNE 1999 In Figure 6, the positive gate charge (QGS) is about 0.1 µC which, with the 0.1 µF gate decoupling capacitor used, increased the gate supply by about 1 V (= QGS/C1). This change is just visible on the -72 V gate voltage, VBAT. This increase does not directly add to the protection voltage as the supply voltage change reaches a maximum at 0.4 µs when the gate current reverses polarity; whereas the protection voltage peaks at 0.3 µs. In Figure 6, the peak clamping voltage (V (BO)) is -77.5 V, an increase of 5.5 V on the nominal gate supply voltage. This 5.5 V increase is the sum of the supply rail increase at that time, (0.5 V), and the protection circuits cathode diode to supply rail breakover voltage (5 V). In practice, use of the recommended 220 nF gate decoupling capacitor would give a supply rail increase of 0.25 V and a V(BO) value of about -77.25 V. 0 Voltage - V -20 VK -40 VBAT -60 -80 0.0 0.5 1.0 1.5 Time - µs 1 QGS IG Current - A 0 -1 -2 IK -3 -4 -5 0.0 0.5 1.0 1.5 Time - µs Figure 6. PROTECTOR FAST IMPULSE CLAMPING AND SWITCHING WAVEFORMS application circuit Figure 7 shows a typical TISP61089A SLIC card protection circuit. The incoming line conductors, Ring (R) and Tip (T), connect to the relay matrix via the series overcurrent protection. Fusible resistors, fuses and positive temperature coefficient (PTC) resistors can be used for overcurrent protection. Resistors will reduce the prospective current from the surge generator for both the TISP61089A and the ring/test protector. The TISP7xxxF3 protector has the same protection voltage for any terminal pair. This protector is used when the ring generator configuration may be ground or battery-backed. For dedicated ground-backed ringing generators, the TISP3xxxF3 gives better protection as its inter-conductor protection voltage is twice the conductor to ground value. PRODUCT INFORMATION 7 TISP61089A DUAL FORWARD-CONDUCTING P-GATE THYRISTORS PROGRAMMABLE OVERVOLTAGE PROTECTORS JUNE 1999 OVERCURRENT PROTECTION TIP WIRE RING/TEST PROTECTION TEST RELAY RING RELAY Th1 R1a SLIC RELAY S3a S1a SLIC PROTECTOR SLIC Th4 S2a Th3 RING WIRE R1b Th5 Th2 TISP 3xxxF3 OR 7xxxF3 S3b S1b S2b TISP 61089A C1 220 nF TEST EQUIPMENT RING GENERATOR VBAT AI6XAJA Figure 7. TYPICAL APPLICATION CIRCUIT Relay contacts 3a and 3b connect the line conductors to the SLIC via the TISP61089A protector. The protector gate reference voltage comes from the SLIC negative supply (VBAT). A 220 nF gate capacitor sources the high gate current pulses caused by fast rising impulses. LSSGR 1089 GR-1089-CORE, “1089”, covers electromagnetic compatibility and electrical safety generic criteria for US network telecommunication equipment. It is a module in Volume 3 of LSSGR (LATA (Local Access Transport Area) Switching Systems Generic Requirements, FR-NWT-000064). In 1089 surge and power fault immunity tests are done at two levels. After first-level testing the equipment shall not be damaged and shall continue to operate correctly. Under second level testing the equipment shall not become a safety hazard. The equipment is permitted to fail as a result of second-level testing. When the equipment is to be located on customer premises, second-level testing includes a wiring simulator test, which requires the equipment to reduce the power fault current below certain values. The following clauses reference the 1089 section and calculate the protector stress levels. The TISP61089A is specified for use with a 40 Ω series resistor. This resistor value will ensure that the TISP61089A survives second level surge testing. Values down to 25 Ω may be used if some second level surge failure is acceptable. All the tabulated values are for a series resistance of 40 Ω. Peak current values for a 25 Ω series resistor are covered in the clause text. The values of protector current are calculated from the open circuit generator voltage divided by the sum of the total circuit resistance. The total circuit resistance is the sum of the generator fictive source resistance and the TISP61089A series resistor value. Most generators have multiple outputs and each output connects to an individual line conductor. For those generators that have a single output, each conductor will have an effective generator fictive source resistance of n times the generator fictive source resistance, where n is the number of conductors simultaneously tested. PRODUCT 8 INFORMATION TISP61089A DUAL FORWARD-CONDUCTING P-GATE THYRISTORS PROGRAMMABLE OVERVOLTAGE PROTECTORS JUNE 1999 section 4.5.7 - first-level surge testing The two most significant test wave shapes in this section are the high energy 10/1000 and the high current 2/10. As shown in table 1, the peak currents for these surges are 2x20 A and 2x56 A respectively. The protector must survive the 2x20 A 10/1000 surge and the TISP61089A will do this as its rating is 2x30 A. When both conductors are surged simultaneously the return (anode) current will be 40 A, again the TISP61089A will survive this as its rating for this condition will be 60 A. Similarly the TISP61089A will survive the 2x56 A 2/10 as its rating is 2x120 A. table 1. first-level surge currents OPEN-CIRCUIT VOLTAGE V SHORT-CIRCUIT CURRENT A GENERATOR FICTIVE SOURCE RESISTANCE Ω TOTAL CIRCUIT RESISTANCE Ω IT 2/10 2500 500 5 45 2x56 1.2/50, 8/20 (See Text) 2500 360 4+3 47 2x53 10/360 1000 100 10 50 2x20 10/1000 600 100 6 46 2x13 10/1000 1000 100 10 50 2x20 WAVE SHAPE A The highest protection voltage will be for the 56 A 2/10 wave shape. Under this condition the average rate of current rise will be 56/2 = 28 A/µs. The value of diode and thyristor voltage under this condition is specified in the electrical characteristics. Compared to TR-NWT-001089, Issue 1, October 1991, GR-1089-CORE, Issue 1, November 1994, adds the alternative of using the IEEE C62.41 1.2/50-8/20 combination wave generator for the 2/10 test. This generator usually has a single output and a fictive resistance of 2 Ω. The 2/10 generator has a fictive output resistance 5 Ω, (2500/500), and GR-1089-CORE compensates for this by adding an extra 3 Ω in the output of the 1.2/508/20 generator. In practice, the extra 3 Ω causes the prospective short-circuit current wave shape to be similar to the 1.2/50 open-circuit voltage wave shape. The TISP61089A will survive the 2x53 A 1.2/50 as its rating is 2x100 A. Using a 25 Ω series resistor will result in table 1. IT column values of 2x83, 2x78, 2x29, 2x19 and 2x29. The TISP61089A will survive these peak current values as they are lower than the TISP61089A ratings. section 4.5.8 - second-level surge testing This is a 2/10 wave shape test. As shown in table 2, the peak current for this surge is 2x100 A. The TISP61089A will survive the 2x100 A 2/10 surge as its rating is 2x120 A. Under this condition the average rate of current rise will be 100/2 = 50 A/µs. The value of diode and thyristor voltage under this condition is specified in the electrical characteristics. Compared to TR-NWT-001089, Issue 1, October 1991, GR-1089-CORE, Issue 1, November 1994, adds the alternative of using the IEEE C62.41 1.2/50-8/20 combination wave generator for the 2/10 test. The 2/10 generator has a fictive output resistance 10 Ω, (5000/500), and GR-1089-CORE compensates for this by adding an extra 8 Ω in the output of the 1.2/50-8/20 generator. In practice, the extra 8 Ω causes the PRODUCT INFORMATION 9 TISP61089A DUAL FORWARD-CONDUCTING P-GATE THYRISTORS PROGRAMMABLE OVERVOLTAGE PROTECTORS JUNE 1999 table 2. second-level surge current OPEN-CIRCUIT VOLTAGE V SHORT-CIRCUIT CURRENT A GENERATOR FICTIVE SOURCE RESISTANCE Ω TOTAL CIRCUIT RESISTANCE Ω 2/10 5000 500 10 50 2x100 1.2/50, 8/20 (See Text) 5000 420 4 + 8/conductor 52 2x96 WAVE SHAPE IT A prospective short-circuit current wave shape to be similar to the 1.2/50 open-circuit voltage wave shape. The TISP61089A will survive the 2x96 A 1.2/50 as its rating is 2x100 A. Using a 25 Ω series resistor will result in table 2. IT column values of 2x143 and 2x135. The TISP61089A may fail at these peak current values as they are higher than the TISP61089A ratings. section 4.5.9 - Intra-building surge testing These tests use a 2/10 wave shape. As shown in table 3, the peak currents for this test are 2x27 A and 17 A. The TISP61089A can survive both these levels as its rating is 2x120 A. table 3. intra-building surge currents WAVE SHAPE 2/10 1.2/50, 8/20 (See Text) OPEN-CIRCUIT VOLTAGE V SHORT-CIRCUIT CURRENT A GENERATOR FICTIVE SOURCE RESISTANCE Ω TOTAL CIRCUIT RESISTANCE Ω IT 1500 100 15 55 2x27 800 100 8 48 17 1500 94 4 + 12/conductor 56 2x27 800 100 2+6 48 17 A Compared to TR-NWT-001089, Issue 1, October 1991, GR-1089-CORE, Issue 1, November 1994, the 2/10 alternative of using a CCITT Recommendation K.22 1.2/50-8/20 combination wave generator has been changed to an IEEE C62.41 1.2/50-8/20 generator. This generator usually has a single output and a fictive resistance of 2 Ω. The 2/10 generator has fictive output resistances of 15 Ω and 8 Ω. GR-1089-CORE compensates for this by adding an extra resistances of 12 Ω and 6 Ω in the output of the 1.2/50-8/20 generator. In practice, this extra resistance causes the prospective short-circuit current wave shape to be similar to the 1.2/50 open-circuit voltage wave shape. The TISP61089A will survive the 2x27 A 1.2/50 as its rating is 2x100 A. Using a 25 Ω series resistor will result in table 3. IT column values of 2x38, 24, 2x37 and 24. The TISP61089A will survive these peak current values as they are lower than the TISP61089A ratings. PRODUCT 10 INFORMATION TISP61089A DUAL FORWARD-CONDUCTING P-GATE THYRISTORS PROGRAMMABLE OVERVOLTAGE PROTECTORS JUNE 1999 section 4.5.12 - first-level power fault testing The most significant tests are a long duration (900 s) medium current test and a higher current tests of 60 one second power applications. As shown in table 4, the peak currents for these tests are 2x0.37 A and 2x1.3 A respectively. The TISP61089A will survive both these conditions as its ratings are 2x0.83 A and 2x4.1 A for these time periods table 4. first-level power fault currents A.C. DURATION s OPEN-CIRCUIT RMS VOLTAGE V SHORT-CIRCUIT RMS CURRENT A SOURCE RESISTANCE Ω TOTAL CIRCUIT RESISTANCE Ω ITRMS ITM A A 1 200 0.33 600 640 2x0.31 2x0.44 1 400 0.67 600 640 2x0.63 2x0.88 1 600 1 600 640 2x0.94 2x1.3 1 1000 1 1000 1040 2x0.96 2x1.3 900 50 0.33 150 190 2x0.26 2x0.37 900 100 0.17 590 630 2x0.16 2x0.22 Using a 25 Ω series resistor will result in table 4. ITM column values of 2x0.45, 2x0.9, 2x1.4, 2x1.4, 2x0.4 and 2x0.23. The TISP61089A will survive these peak current values as they are lower than the TISP61089A ratings. section 4.5.13 - second-level power fault testing The two most significant tests are a long duration (900 s) medium current test and a higher current 5 s test. As shown in table 5, the peak currents for these tests are 2x17 A and 2x7.7 A respectively. For the TISP61089A to survive this test, the series current limiting element must operate within 0.01 s and 0.35 s respectively. table 5. second-level power fault currents A.C. DURATION s OPEN-CIRCUIT RMS VOLTAGE V SHORT-CIRCUIT CURRENT A SOURCE RESISTANCE Ω TOTAL CIRCUIT RESISTANCE Ω ITRMS ITM A A 5 600 60 10 50 2x12 2x17 5 600 7 86 126 2x4.8 2x6.8 900 120 25 5 45 2x2.7 2x3.8 900 277 25 11 51 2x5.4 2x7.7 900 100 0.37 273 313 2x0.32 2x0.45 900 300 1.1 273 313 2x0.96 2x1.4 900 600 2.2 273 313 2x1.9 2x2.7 PRODUCT INFORMATION 11 TISP61089A DUAL FORWARD-CONDUCTING P-GATE THYRISTORS PROGRAMMABLE OVERVOLTAGE PROTECTORS JUNE 1999 Using a 25 Ω series resistor will result in table 5. ITM column values of 2x24, 2x7.7, 2x5.7, 2x11, 2x0.47, 2x1.4 and 2x2.9. The TISP61089A will probably fail for a peak current level of 2x24 A and the series current limiting element must operate in under 0.1 s to prevent exceeding the TISP61089A package limit. For 2x7.7 A, the series current limiting element must operate within 0.35 s for TISP61089A survival. section 4.5.15 - second-level power fault testing with wiring simulator The purpose of this test is to ensure that the telephone cable does not become a hazard due to excessive current. A series fuse, type MDQ 1-6/10A, simulates the safe current levels of a telephone cable. If this fuse opens the equipment fails the test. For the equipment to pass, the equipment series overcurrent element must reduce the current to below the MDQ 1-6/10A fusing level to prevent the simulator operating. The a.c. test voltage can range from zero to 600 V, which gives a maximum conductor current of 10 A. Table 6 shows the simulator fusing times for three current levels. table 6. second-level power fault currents with MDQ 1-6/10A fuse A.C. DURATION s OPEN-CIRCUIT RMS VOLTAGE V SHORTCIRCUIT CURRENT A SOURCE RESISTANCE Ω TOTAL CIRCUIT RESISTANCE Ω 1000 100 5 20 1000 300 15 1000 600 30 TIME TO OPEN s ITRMS ITM A A 60 1.7 2.4 ∞ 20 60 5.0 7.1 30 20 60 10 14 0.7 Using a 25 Ω series resistor will result in table 6. ITM column values of 2x3.1, 2x9.4 and 2x19. Simulator operating times will be ∞, 12 s and 0.4 s respectively For the equipment to pass this test, the TISP61089A series current limiting element must operate before the MDQ 1-6/10A fusing times shown in table 7. table 7. operating times of MDQ 1-6/10A fuse TIME TO OPERATE s IRMS 0.2 17 0.5 12 1 9 5 7 10 6.8 1000 2.5 A overcurrent protection To meet ‘1089, the overcurrent protection must be coordinated with the requirements of sections 4.5.7, 4.5.8, 4.5.9, 4.5.12, 4.5.13, 4.5.15 and the TISP61089A. The overcurrent protection must not fail in the first level tests of sections 4.5.7, 4.5.9 and 4.5.12. Recoverable overcurrent protectors (e.g. Positive Temperature Coefficient Resistors) may operate during first level testing, but normal equipment working must be restored PRODUCT 12 INFORMATION TISP61089A DUAL FORWARD-CONDUCTING P-GATE THYRISTORS PROGRAMMABLE OVERVOLTAGE PROTECTORS JUNE 1999 after the test has ended. The test current levels and their duration are shown in Figure 8. First level tests have a high source resistance and the current levels are not strongly dependent on the TISP61089A series resistor value. Second level tests have a low source resistance and the current levels are dependent on the TISP61089A series resistor value. The two stepped lines at the top of Figure 8 are for the 25 Ω and 40 Ω series resistor cases. If the full current-time durations occur the equipment will fail the wiring simulator test. The MDQ 1-6/ 10A fusing characteristic is also shown in Figure 8. The TISP61089A series overcurrent protection must operate before the MDQ 1-6/10A fuses, so this represents another boundary condition in the selection of the overcurrent protector. MAXIMUM RMS CURRENT vs TIME AI6XAK 30 Maximum RMS Current - A 20 Second Level Tests - 25 Ω 10 7 5 Second Level Tests - 40 Ω 3 2 MDQ 1-6/10A Fuse 1 0.7 0.5 0.3 First Level Tests - 25 & 40 Ω 0.2 0.1 0.01 0.1 1 10 100 1000 Time - s Figure 8. ‘1089 MAXIMUM TEST CURRENT LEVEL Figure 9 summarises these boundary conditions. The highest current levels that can flow are influenced by the TISP61089A series resistance. After one second the maximum current-time boundary becomes set by the MDQ 1-6/10A fusing characteristic. Fusible overcurrent protectors cannot operate at first level current levels. Figure 9 shows two other curves. The lower one is the TISP61089A rated current. The overcurrent protector should not allow current-time durations greater than this otherwise the TISP61089A may fail. If second level failure is acceptable then the overcurrent protector must operate before the TISP61089A package limit is reached. The TISP61089A a.c. ratings are worse case values when the device is mounted on the EIA/JESD51-3 PCB used for measuring thermal resistance. Typical PCBs would give a 25% increase in the rated currents for periods above 0.1 s. PRODUCT INFORMATION 13 TISP61089A DUAL FORWARD-CONDUCTING P-GATE THYRISTORS PROGRAMMABLE OVERVOLTAGE PROTECTORS JUNE 1999 OVERCURRENT PROTECTOR OPERATION LIMITS vs TIME 30 Second Level Tests - 25 Ω 20 Maximum RMS Current - A AI6XALA 10 7 5 MDQ 1-6/10A Fuse 3 Second Level Tests - 40 Ω 2 TISP61089A Package Limit 1 0.7 0.5 TISP61089A Survival 0.3 First Level Tests - 25 & 40 Ω 0.2 0.1 0.01 0.1 1 Time - s 10 100 Figure 9. OVERCURRENT PROTECTOR REQUIREMENTS PRODUCT 14 INFORMATION 1000 TISP61089A DUAL FORWARD-CONDUCTING P-GATE THYRISTORS PROGRAMMABLE OVERVOLTAGE PROTECTORS JUNE 1999 MECHANICAL DATA D008 plastic small-outline package This small-outline package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. The compound will withstand soldering temperature with no deformation, and circuit performance characteristics will remain stable when operated in high humidity conditions. Leads require no additional cleaning or processing when used in soldered assembly. D008 Designation per JEDEC Std 30: PDSO-G8 5,00 (0.197) 4,80 (0.189) 8 7 6 5 1 2 3 4 6,20 (0.244) 5,80 (0.228) 4,00 (0.157) 3,81 (0.150) 7° NOM 3 Places 1,75 (0.069) 1,35 (0.053) 0,50 (0.020) x 45°NOM 0,25 (0.010) 0,203 (0.008) 0,102 (0.004) 0,79 (0.031) 0,28 (0.011) 7° NOM 4 Places 0,51 (0.020) 0,36 (0.014) 8 Places Pin Spacing 1,27 (0.050) (see Note A) 6 Places 5,21 (0.205) 4,60 (0.181) 0,229 (0.0090) 0,190 (0.0075) 4° ± 4° 1,12 (0.044) 0,51 (0.020) ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES NOTES: A. B. C. D. Leads are within 0,25 (0.010) radius of true position at maximum material condition. Body dimensions do not include mold flash or protrusion. Mold flash or protrusion shall not exceed 0,15 (0.006). Lead tips to be planar within ±0,051 (0.002). PRODUCT MDXXAA INFORMATION 15 TISP61089A DUAL FORWARD-CONDUCTING P-GATE THYRISTORS PROGRAMMABLE OVERVOLTAGE PROTECTORS JUNE 1999 MECHANICAL DATA P008 plastic dual-in-line package This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. The compound will withstand soldering temperature with no deformation, and circuit performance characteristics will remain stable when operated in high humidity conditions The package is intended for insertion in mounting-hole rows on 7,62 (0.300) centres. Once the leads are compressed and inserted, sufficient tension is provided to secure the package in the board during soldering. Leads require no additional cleaning or processing when used in soldered assembly. P008 Designation per JEDEC Std 30: PDIP-T8 10,2 (0.400) MAX 8 7 6 5 Index Dot C L 1 2 3 C L 7,87 (0.310) 7,37 (0.290) T.P. 4 6,60 (0.260) 6,10 (0.240) 1,78 (0.070) MAX 4 Places 5,08 (0.200) MAX Seating Plane 0,51 (0.020) MIN 3,17 (0.125) MIN 2,54 (0.100) T.P. 6 Places (see Note A) 0,533 (0.021) 0,381 (0.015) 8 Places 105° 90° 8 Places 0,36 (0.014) 0,20 (0.008) 8 Places ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES NOTE A: Each pin centerline is located within 0,25 (0.010) of its true longitudinal position PRODUCT 16 INFORMATION MDXXABA TISP61089A DUAL FORWARD-CONDUCTING P-GATE THYRISTORS PROGRAMMABLE OVERVOLTAGE PROTECTORS JUNE 1999 IMPORTANT NOTICE Power Innovations Limited (PI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to verify, before placing orders, that the information being relied on is current. PI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with PI's standard warranty. Testing and other quality control techniques are utilized to the extent PI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. PI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor is any license, either express or implied, granted under any patent right, copyright, design right, or other intellectual property right of PI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. PI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORISED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS. Copyright © 1999, Power Innovations Limited PRODUCT INFORMATION 17