SN54HCT126, SN74HCT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS070A – NOVEMBER 1988 – REVISED NOVEMBER 1990 D SN54HCT126 . . . J PACKAGE SN74HCT126 . . . D OR N PACKAGE (TOP VIEW) High-Current 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Inputs Are TTL-Voltage Compatible Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs D D 1OE 1A 1Y 2OE 2A 2Y GND description These bus buffers feature independent line drivers with 3-state outputs. Each output is disabled when the associated OE is low. A H H H H L L L X Z H = high level, L = low level, X = irrelevant 1A 2OE 2A 3OE 3A 4OE 4A 1 12 4 11 5 10 6 9 7 8 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3OE NC – No internal connection logic symbol† 1OE 13 3 2Y GND NC 3Y 3A OE 2 VCC 4OE 4A 4Y 3OE 3A 3Y 1A 1OE NC VCC 4OE 1Y NC 2OE NC 2A FUNCTION TABLE OUTPUT Y 14 SN54HCT126 . . . FK PACKAGE (TOP VIEW) The SN54HCT126 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74HCT126 is characterized for operation from –40°C to 85°C. INPUTS 1 logic diagram, each buffer (positive logic) EN 3 2 4 6 5 10 8 9 13 12 11 OE 1Y A Y 2Y 3Y 4Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. Copyright 1990, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54HCT126, SN74HCT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS070A – NOVEMBER 1988 – REVISED NOVEMBER 1990 absolute maximum ratings over operating free-air temperature range† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package . . . . . . . . . . . . . . . . . . . . . . . . 300°C Lead temperature 1,6 mm (1/16 in) from case for 10 s: DW or N package . . . . . . . . . . . . . . . . . . . . . . . 260°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN54HCT126 SN74HCT126 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0 0.8 0 0.8 V Input voltage 0 0 Output voltage 0 0 VCC VCC V VO tt VCC VCC 0 500 0 500 ns TA Operating free-air temperature –55 125 –40 85 °C High-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 2 Input transition (rise and fall) time 2 V V V electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VOH VI = VIH or VIL, IOH = –20 µA VI = VIH or VIL, IOH = –6 mA 4 5V 4.5 VOL VI = VIH or VIL, IOL = 20 µA VI = VIH or VIL, IOL = 6 mA 45V 4.5 II IOZ VI = VCC or 0 VO = VCC or 0, VI = VIH or VIL ICC VI = VCC or 0, IO = 0 One input at 0.5 V or 2.4 V, Other inputs at 0 or VCC 5.5 V ∆ICC‡ Ci MIN TA = 25°C TYP MAX SN54HCT126 MIN MAX SN74HCT126 MIN 4.4 4.499 4.4 4.4 3.98 4.3 3.7 3.84 MAX V 0.001 0.1 0.1 0.1 0.17 0.26 0.4 0.33 5.5 V ±0.1 ±100 ±1000 ±1000 nA 5.5 V ±0.01 ±0.5 ±10 ±5 µA 8 160 80 µA 1.4 2.4 3 2.9 mA 3 10 10* 10 pF 5.5 V 4.5 V to 5.5 V * On products compliant to MIL-STD-883C, Class B, this parameter is not production tested. ‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 2 UNIT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V SN54HCT126, SN74HCT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS070A – NOVEMBER 1988 – REVISED NOVEMBER 1990 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tpd d A Y ten OE Y tdis di OE Y tt Any VCC MIN TA = 25°C TYP MAX SN54HCT126 MIN MAX SN74HCT126 MIN MAX 4.5 V 15 26 39 33 5.5 V 12 23 35 30 4.5 V 19 26 39 33 5.5 V 15 23 35 30 4.5 V 18 26 39 33 5.5 V 15 23 35 30 4.5 V 8 15 22 19 5.5 V 7 14 21 17 UNIT ns ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tpd d A Y ten OE Y tt Any VCC MIN TA = 25°C TYP MAX SN54HCT126 MIN MAX SN74HCT126 MIN MAX 4.5 V 21 36 58 46 5.5 V 17 32 48 42 4.5 V 25 36 58 46 5.5 V 21 32 48 42 4.5 V 17 42 63 53 5.5 V 14 38 57 48 UNIT ns ns ns operating characteristics, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load TYP 35 UNIT pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54HCT126, SN74HCT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS070A – NOVEMBER 1988 – REVISED NOVEMBER 1990 PARAMETER MEASUREMENT INFORMATION VCC PARAMETER ten S1 RL From Output Under Test CL (see Note A) tdis tPZH 1 kΩ tPZL tPHZ CL S1 S2 50 pF or 150 pF Open Closed Closed Open Open Closed Closed Open Open Open RL 1 kΩ 50 pF tPLZ S2 tpd or tt –– 50 pF or 150 pF LOAD CIRCUIT 3V Input (See Note B) 1.3 V 1.3 V 0V tPZL 3V Input 1.3 V 1.3 V 0V tPLH tPHL Output (See Note C) tPLZ ≈ VCC 1.3 V VOL 10% tPZH VOH Output 1.3 V 1.3 V tr tf VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES Output (See Note C) VOH 1.3 V 90% ≈0V tPHZ VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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