SN54BCT652, SN74BCT652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS038A – AUGUST 1989 – REVISED NOVEMBER 1993 • • • • SN54BCT652 . . . JT OR W PACKAGE SN74BCT652 . . . DW OR NT PACKAGE (TOP VIEW) CLKAB SAB OEAB A1 A2 A3 A4 A5 A6 A7 A8 GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC CLKBA SBA OEBA B1 B2 B3 B4 B5 B6 B7 B8 SN54BCT652 . . . FK PACKAGE (TOP VIEW) description These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. 3 2 1 28 27 26 5 25 6 24 7 23 8 22 9 21 10 20 19 11 12 13 14 15 16 17 18 A7 A8 GND NC B8 B7 Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A low input selects real-time data, and a high input selects stored data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ′BCT652. 4 A1 A2 A3 NC A4 A5 A6 OEBA B1 B2 NC B3 B4 B5 B6 • State-of-the-Art BiCMOS Design Significantly Reduces ICCZ ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Independent Registers and Enables for A and B Buses Multiplexed Real-Time and Stored Data Power-Up High-Impedance Mode Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK) and Flatpacks (W), and Standard Plastic and Ceramic 300-mil DIPs (JT, NT) OEAB SAB CLKAB NC VCC CLKBA SBA • NC – No internal connection Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs regardless of the select- or enable-control pins. When SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration each output reinforces its input. Therefore, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remain at its last state. The SN54BCT652 is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74BCT652 is characterized for operation from 0°C to 70°C. Copyright 1993, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–1 SN54BCT652, SN74BCT652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS 3 21 OEAB OEBA L L 1 23 2 CLKAB CLKBA SAB X X X BUS B BUS A BUS A BUS B SCBS038A – AUGUST 1989 – REVISED NOVEMBER 1993 22 SBA L 3 21 OEAB OEBA H H 21 OEBA H X H 1 23 2 CLKAB CLKBA SAB ↑ X ↑ X ↑ ↑ X X X 22 SBA X X X STORAGE FROM A, B, OR A AND B 3 OEAB H L H 22 SBA X BUS B 21 OEBA L L H 1 CLKAB 23 CLKBA 2 SAB 22 SBA L X L L L X H X H H H X TRANSFER STORED DATA TO A AND/OR B Figure 1. Bus-Management Functions Pin numbers shown are for the DW, JT, NT, and W packages. 2–2 2 SAB L BUS A BUS A 3 OEAB X L L 23 CLKBA X REAL-TIME TRANSFER BUS A TO BUS B BUS B REAL-TIME TRANSFER BUS B TO BUS A 1 CLKAB X POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54BCT652, SN74BCT652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS038A – AUGUST 1989 – REVISED NOVEMBER 1993 FUNCTION TABLE DATA I/O† INPUTS OEAB OEBA CLKAB CLKBA L H H or L L H ↑ X H ↑ H H ↑ L X H or L L L ↑ ↑ X L L X X X L L X H or L X H H X X L H H H or L X H H L H or L OPERATION OR FUNCTION SAB SBA A1 THRU A8 B1 THRU B8 H or L X X Input Input Isolation ↑ X X Input Input Store A and B data H or L X Input Unspecified‡ Store A, hold B ↑ X X‡ X Store A in both registers X Input Unspecified‡ Output ↑ Input Hold A, store B Output Input Store B in both registers L Output Input Real-time B data to A bus H Output Input Stored B data to A bus X Input Output Real-time A data to B bus X Input Output Stored A data to B bus Output Stored A data to B bus and stored B data to A bus H or L H X X‡ H Output † The data output functions may be enabled or disabled by a variety of level combinations at the OEAB or OEBA inputs. Data input functions are always enabled; i.e., data at the bus pins is stored on every low-to-high transition on the clock inputs. ‡ Select control = L; clocks can occur simultaneously. Select control = H; clocks must be staggered in order to load both registers. logic symbol§ OEBA OEAB CLKBA SBA CLKAB SAB A1 21 3 23 22 1 EN1 [BA] EN2 [AB] C4 G5 2 C6 G7 4 ≥1 1 7 1 A3 A4 A5 A6 A7 A8 20 B1 5 1 6D A2 4D 5 ≥1 2 7 5 19 6 18 7 17 8 16 9 15 10 14 11 13 B2 B3 B4 B5 B6 B7 B8 § This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, JT, NT, and W packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–3 SN54BCT652, SN74BCT652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS038A – AUGUST 1989 – REVISED NOVEMBER 1993 logic diagram (positive logic) OEBA OEAB CLKBA SBA CLKAB SAB 21 3 23 22 1 2 One of Eight Channels 1D C1 A1 4 20 B1 1D C1 To Seven Other Channels Pin numbers shown are for the DW, JT, NT, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range: Control inputs (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 5.5 V Voltage range applied to any output in the disabled or power-off state, VO . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Voltage range applied to any output in the high state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC Current into any output in the low state: SN54BCT652 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74BCT652 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Operating free-air temperature range: SN54BCT652 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C SN74BCT652 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2–4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54BCT652, SN74BCT652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS038A – AUGUST 1989 – REVISED NOVEMBER 1993 recommended operating conditions SN54BCT652 SN74BCT652 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IIK Low-level input voltage 0.8 0.8 V Input clamp current –18 –18 mA IOH IOL High-level output current –12 –15 mA 64 mA TA Operating free-air temperature 70 °C High-level input voltage 2 2 Low-level output current V 48 – 55 125 V 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VCC = 4.5 V, VOH IIH‡ IIL‡ IOS§ ICCL ICCH ICCZ II = –18 mA IOH = – 3 mA VCC = 4.5 V VOL II TEST CONDITIONS A or B port Control inputs A or B port Control inputs A or B port Control inputs A or B port A or B port A or B port IOH = –12 mA IOH = –15 mA VCC = 4 4.5 5V IOL = 48 mA IOL = 64 mA VCC = 5 5.5 5V V, VI = 5 5.5 5V 5V VCC = 5 5.5 V, 7V VI = 2 2.7 VCC = 5 5.5 5V V, VI = 0 0.5 5V VCC = 5.5 V, VCC = 5.5 V, VO = 0 VI = 0 VCC = 5.5 V, VCC = 5.5 V, VI = 4.5 V VI = 0 SN54BCT652 TYP† MAX MIN SN74BCT652 TYP† MAX MIN –1.2 2.4 3.3 2 3.2 –1.2 2.4 3.1 0.55 0.42 – 100 V 3.3 V 2 0.38 UNIT 0.55 1 1 1 1 70 70 20 20 – 0.7 – 0.7 – 0.7 – 0.7 – 225 mA µA mA – 225 mA 43 69 mA 10 6 10 mA 17 10 17 mA 43 69 6 10 – 100 V Ci Control inputs VCC = 5 V, VI = 2.5 V or 0.5 V 6 Cio A or B port VCC = 5 V, VO = 2.5 V or 0.5 V 14 † All typical values are at VCC = 5 V, TA = 25°C. ‡ For I/O ports, the parameters IIH and IIL include the off-state output current. § Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 6 pF 14 pF timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) VCC = 5 V, TA = 25°C fclock tw Clock frequency tsu th Pulse duration, CLK high or low SN54BCT652 MIN MAX MIN MAX 0 77 0 77 SN7BCTT652 MIN MAX 0 77 UNIT MHz 6.5 7 6.5 ns Setup time, A or B before CLKAB↑ or CLKBA↑ 5 6 5 ns Hold time, A or B after CLKAB↑ or CLKBA↑ 1 1 1 ns POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–5 SN54BCT652, SN74BCT652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS038A – AUGUST 1989 – REVISED NOVEMBER 1993 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Note 2) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25°C MIN TYP SN54BCT652 MIN 77 CLKBA A CLKAB B A B B A SBA† (with B high) A SBA† (with B low) A SAB† (with A high) B SAB† (with A low) B OEBA A OEBA A OEAB B OEAB B MIN MAX 77 SN74BCT652 MIN 77 MHz 2.6 6.9 8.9 2.6 11.6 2.6 10.5 2.8 6.8 8.8 2.8 10.7 2.8 9.9 2.6 6.9 8.9 2.6 11.6 2.6 10.5 2.8 6.8 8.8 2.8 10.7 2.8 9.9 1.7 5.8 7.5 1.7 10.3 1.7 8.9 2.4 6.5 8.2 2.4 11 2.4 9.8 1.7 5.8 7.5 1.7 10.3 1.7 8.9 2.4 6.5 8.2 2.4 11 2.4 9.8 3.5 8.8 10.8 3.5 14.2 3.5 13.1 2.4 5.9 7.7 2.4 9.1 2.4 8.5 3 7.6 9.7 3 12.4 3 11.3 3.8 8.3 10.4 3.8 12.9 3.8 12.5 3.5 8.8 10.8 3.5 14.2 3.5 13.1 2.4 5.9 7.7 2.4 9.1 2.4 8.5 3 7.6 9.7 3 12.4 3 11.3 3.8 8.3 10.4 3.8 12.9 3.8 12.5 2.5 7.2 8.9 2.5 11.2 2.5 10.6 3.2 8.1 10.1 3.2 12.6 3.2 12 2.8 6.7 8.6 2.8 10.9 2.8 10 2.4 6.3 8.4 2.4 10.5 2.4 9.5 1.5 5.4 7.1 1.5 9 1.5 8.1 2.3 6.2 8.1 2.3 10.3 2.3 9.3 3.5 8.2 10 3.5 12.2 3.5 11.6 tPLZ 2.8 7.2 9.5 2.8 12 2.8 † These parameters are measured with the internal output state of the storage register opposite to that of the bus input. NOTE 2: Load circuits and voltage waveforms are shown in Section 1. 11.3 tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ 2–6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT MAX ns ns ns ns ns ns ns ns ns ns ns ns IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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