SN54ABT18652, SN74ABT18652 SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS SCBS132A – AUGUST 1992 – REVISED OCTOBER 1992 • • • • • • • Members of the Texas Instruments SCOPE Family of Testability Products Members of the Texas Instruments Widebus Family Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture Include D-Type Flip-Flops and Control Circuitry to Provide Multiplexed Transmission of Stored and Real-Time Data Two Boundary-Scan Cells per I/O for Greater Flexibility State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation • SCOPE Instruction Set – IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, and P1149.1A CLAMP and HIGHZ – Parallel Signature Analysis at Inputs With Masking Option – Pseudo-Random Pattern Generation From Outputs – Sample Inputs/Toggle Outputs – Binary Count From Outputs – Device Identification – Even-Parity Opcodes Packaged in 64-Pin Plastic Shrink Quad Flat Pack (PM) and 68-Pin Ceramic Quad Flat Pack (HV) PRODUCT PREVIEW 1A2 1A1 1OEBA GND 1SAB 1CLKAB TDO VCC NC TMS 1CLKBA 1SBA 1OEAB GND 1B1 1B2 1B3 SN54ABT18652 . . . HV PACKAGE (TOP VIEW) 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 1 51 2 50 3 49 4 48 5 47 6 46 7 45 8 44 9 43 10 42 11 41 12 40 13 39 14 38 15 37 16 36 1B4 1B5 1B6 GND 1B7 1B8 1B9 VCC NC 2B1 2B2 2B3 2B4 GND 2B5 2B6 2B7 TCK 2CLKBA 2SBA GND 2OEAB 2B9 2B8 VCC 17 35 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 2A7 2A8 2A9 GND 2OEBA 2SAB 2CLKAB TDI NC 1A3 1A4 1A5 GND 1A6 1A7 1A8 1A9 NC VCC 2A1 2A2 2A3 GND 2A4 2A5 2A6 NC – No internal connection Copyright 1992, Texas Instruments Incorporated PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ABT18652, SN74ABT18652 SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS SCBS132A – AUGUST 1992 – REVISED OCTOBER 1992 1A2 1A1 1OEBA GND 1SAB 1CLKAB TDO V CC TMS 1CLKBA 1SBA 1OEAB GND 1B1 1B2 1B3 SN74ABT18652 . . . PM PACKAGE (TOP VIEW) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 1B4 1B5 1B6 GND 1B7 1B8 1B9 VCC 2B1 2B2 2B3 2B4 GND 2B5 2B6 2B7 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 2A7 2A8 2A9 GND 2OEAB 2SAB 2CLKAB TDI VCC TCK 2CLKBA 2SBA GND 2OEAB 2B9 2B8 PRODUCT PREVIEW 1A3 1A4 1A5 GND 1A6 1A7 1A8 1A9 VCC 2A1 2A2 2A3 GND 2A4 2A5 2A6 description The SN54ABT18652 and SN74ABT18652 scan test devices with 18-bit bus transceivers and registers are members of the Texas Instruments SCOPE testability IC family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface. In the normal mode, these devices are 18-bit bus transceivers and registers that allow for multiplexed transmission of data directly from the input bus or from the internal registers. They can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE bus transceivers and registers. Data flow in each direction is controlled by clock (CLKAB and CLKBA), select (SAB and SBA), and output-enable (OEAB and OEBA) inputs. For A-to-B data flow, data on the A bus is clocked into the associated registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data is selected for presentation to the B bus (transparent mode). When SAB is high, stored A data is selected for presentation to the B bus (registered mode). When OEAB is high, the B outputs are active. When OEAB is low, the B outputs are in the high-impedance state. Control for B-to-A data flow is similar to that for A-to-B data flow but uses CLKBA, SBA, and OEBA inputs. Since the OEBA input is active-low, the A outputs are active when OEBA is low and are in the high-impedance state when OEBA is high. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ′ABT18652. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ABT18652, SN74ABT18652 SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS SCBS132A – AUGUST 1992 – REVISED OCTOBER 1992 description (continued) In the test mode, the normal operation of the SCOPE bus transceivers and registers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary scan test operations according to the protocol described in IEEE Standard 1149.1-1990. Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry can perform other testing functions such as parallel signature analysis on data inputs and pseudo-random pattern generation from data outputs. All testing and scan operations are synchronized to the TAP interface. Additional flexibility is provided in the test mode through the use of two boundary scan cells (BSCs) for each I/O pin. This allows independent test data to be captured and forced at either bus (A or B). A PSA/COUNT instruction is also included to ease the testing of memories and other circuits where a binary count addressing scheme is useful. The SN54ABT18652 is characterized over the full military temperature range of – 55°C to 125°C. The SN74ABT18652 is characterized for operation from – 40°C to 85°C. INPUTS CLKAB DATA I/O OEAB OEBA CLKBA L H L L H ↑ X H ↑ L H H ↑ L X L L L ↑ ↑ X X X‡ L L X X X L L L X L X H H X X H H L X H L L L H PRODUCT PREVIEW FUNCTION TABLE (normal mode, each 9-bit section) OPERATION OR FUNCTION SAB SBA A1 THRU A9 B1 THRU B9 L X X Input disabled Input disabled Isolation ↑ X X Input Input Store A and B data X Input Unspecified† Store A, hold B ↑ X X‡ X Store A in both registers X Input Unspecified† Output ↑ Input Hold A, store B Output Input Store B in both registers Output Input Real-time B data to A bus H Output Input Stored B data to A bus L X Input Output Real-time A data to B bus H X Input Output Stored A data to B bus H Output Output Stored A data to B bus and stored B data to A bus † The data output functions can be enabled or disabled by a variety of level combinations at the OEAB or OEBA inputs. Data input functions are always enabled; i.e., data at the bus pins is stored on every low-to-high transition on the clock inputs. ‡ Select control = L: clocks can occur simultaneously. Select control = H: clocks must be staggered in order to load both registers. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ABT18652, SN74ABT18652 SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS PRODUCT PREVIEW OEAB OEBA L L CLKAB CLKBA SAB X X X BUS B BUS A BUS A BUS B SCBS132A – AUGUST 1992 – REVISED OCTOBER 1992 SBA L OEAB OEBA H H OEBA H X H CLKAB CLKBA SAB ↑ X ↑ X ↑ ↑ X X X SBA X X X STORAGE FROM A, B, OR A AND B OEAB H SBA X BUS B OEBA L CLKAB CLKBA SAB SBA L L H H TRANSFER STORED DATA TO A AND/OR B Figure 1. Bus-Management Functions 4 SAB L BUS A BUS A OEAB X L L CLKBA X REAL-TIME TRANSFER BUS A TO BUS B BUS B REAL-TIME TRANSFER BUS B TO BUS A CLKAB X POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ABT18652, SN74ABT18652 SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS SCBS132A – AUGUST 1992 – REVISED OCTOBER 1992 functional block diagram Boundary-Scan Register 1OEAB 1OEBA 1CLKBA 1SBA 1CLKAB 1SAB 53 62 55 54 59 60 C1 1D 63 51 1A1 1B1 C1 1D 1 of 9 Channels 2OEBA 2CLKBA 2SBA 2CLKAB 2SAB 30 PRODUCT PREVIEW 2OEAB 21 27 28 23 22 C1 1D 2A1 40 10 C1 1D 2B1 1 of 9 Channels Bypass Register Boundary-Control Register Identification Register TDI TMS TCK VCC 24 58 Instruction Register TDO VCC 56 26 TAP Controller Pin numbers shown are for the PM package. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ABT18652, SN74ABT18652 SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS SCBS132A – AUGUST 1992 – REVISED OCTOBER 1992 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI: except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 5.5 V Voltage range applied to any output in the high state or power-off state, VO . . . . . . . . . . . . . – 0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT18652 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT18652 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885 mW Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. For the SN74ABT18652 (PM package), the power derating factor for ambient temperatures greater than 55°C is –10.5 mW/°C. recommended operating conditions (see Note 3) PRODUCT PREVIEW SN54ABT18652 SN74ABT18652 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current VCC – 24 Low-level output current 48 64 mA ∆t /∆v Input transition rise or fall rate 10 10 ns / V 85 °C High-level input voltage 2 0.8 Input voltage 0 TA Operating free-air temperature NOTE 3: Unused or floating pins (input or I/O) must be held high or low. 6 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 – 55 125 V 0.8 0 – 40 V VCC – 32 V V mA SN54ABT18652, SN74ABT18652 SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS SCBS132A – AUGUST 1992 – REVISED OCTOBER 1992 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Note 4) VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = – 3 mA VCC = 5 V, VCC = 4 4.5 5V MIN –1.2 MAX SN74ABT18652 MIN –1.2 IOH = – 3 mA IOH = – 24 mA 3 3 3 2 2 IOH = – 32 mA IOL = 48 mA 2* VCC = 5.5 V, VI = VCC or GND UNIT V V 2 0.55 IOL = 64 mA 0.55 0.55* CLK, OEAB, OEBA, S, TCK 0.55 V ±1 ±1 ±1 ±100 ±100 ±100 TDI, TMS 10 10 10 µA TDI, TMS –160 –160 –160 µA 50 50 50 µA A or B ports IIH IIL VCC = 5.5 V, VCC = 5.5 V, VI = VCC VI = GND IOZH‡ IOZL‡ VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VO = 0.5 V Ioff ICEX IO§ VCC = 0, VCC = 5.5 V, VI or VO ≤ 5.5 V VO = 5.5 V Outputs high VCC = 5.5 V, VO = 2.5 V A or B ports orts MAX –1.2 2.5 II – 50 –100 – 50 – 50 – 50 µA ± 450 ±100 µA 50 50 50 µA –180 mA –180 – 50 –180 – 50 4 4 4 Outputs low 80 80 80 4 4 4 1.5 1.5 1.5 Outputs disabled VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND Ci VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V Control inputs A or B ports mA mA 4 pF 10 pF Co VO = 2.5 V or 0.5 V TDO 8 NOTE 4: Preliminary specifications based on SPICE analysis * On products compliant to MIL-STD-883, Class B, this parameter does not apply. † All typical values are at VCC = 5 V. ‡ The parameters IOZH and IOZL include the input leakage current. § Not more than one output should be tested at a time, and the duration of the test should not exceed one second. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. POST OFFICE BOX 655303 µA µ ±100 Outputs high ∆ICC¶ Cio SN54ABT18652 2.5 VCC = 4 4.5 5V VCC = 5.5 V, IO = 0, VI = VCC or GND TA = 25°C TYP† MAX 2.5 VOL ICC MIN • DALLAS, TEXAS 75265 PRODUCT PREVIEW PARAMETER pF 7 SN54ABT18652, SN74ABT18652 SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS SCBS132A – AUGUST 1992 – REVISED OCTOBER 1992 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (normal mode) (see Note 4 and Figure 2) SN54ABT18652 SN74ABT18652 MIN MAX MIN MAX 0 100 0 100 UNIT fclock tw Clock frequency CLKAB or CLKBA Pulse duration CLKAB or CLKBA high or low 3 MHz ns tsu th Setup time A before CLKAB↑ or B before CLKBA↑ 5 ns Hold time A after CLKAB↑ or B after CLKBA↑ 0 ns timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (test mode) (see Note 4 and Figure 2)123 SN54ABT18652 fclock tw PRODUCT PREVIEW tsu SN74ABT18652 MIN MAX MIN MAX 0 50 0 50 Clock frequency TCK Pulse duration TCK high or low 5 A, B, CLK, OEAB, OEBA, or S before TCK↑ 5 TDI before TCK↑ 6 TMS before TCK↑ 6 A, B, CLK, OEAB, OEBA, or S after TCK↑ 0 TDI after TCK↑ 0 Setup time th Hold time td tr Delay time TMS after TCK↑ UNIT MHz ns ns ns 0 Power up to TCK↑ 50 ns Rise time VCC power up NOTE 4: Preliminary specifications based on SPICE analysis 1 µs 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ABT18652, SN74ABT18652 SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS SCBS132A – AUGUST 1992 – REVISED OCTOBER 1992 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (normal mode) (see Note 4 and Figure 2) fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) CLKAB or CLKBA A or B B or A CLKAB or CLKBA B or A SAB or SBA B or A OEAB or OEBA B or A OEAB or OEBA B or A VCC = 5 V, TA = 25°C MIN TYP 100 130 SN54ABT18652 MAX MIN MAX 100 SN74ABT18652 MIN UNIT MAX 100 MHz 1 6 1 6 2 6 2 6 2 8 2 8 2 7.5 2 7.5 2 7.5 2 7.5 ns ns ns ns ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (test mode) (see Note 4 and Figure 2)123 PARAMETER fmax tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25°C MIN TYP 50 90 TCK TCK↓ A or B TCK↓ TDO TCK↓ A or B TCK↓ TDO TCK↓ A or B SN54ABT18652 MAX TCK↓ TDO tPLZ NOTE 4: Preliminary specifications based on SPICE analysis POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN 50 MAX SN74ABT18652 MIN UNIT MAX 50 MHz 3 12 3 12 2 7 2 7 3 14 3 14 2 8 2 8 3 14 3 14 2 8 2 8 ns ns ns ns ns ns 9 PRODUCT PREVIEW PARAMETER SN54ABT18652, SN74ABT18652 SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS SCBS132A – AUGUST 1992 – REVISED OCTOBER 1992 PARAMETER MEASUREMENT INFORMATION 7V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open LOAD CIRCUIT FOR OUTPUTS 3V 1.5 V Timing Input 0V tw tsu 3V Input 1.5 V 3V 1.5 V Data Input 1.5 V 0V PRODUCT PREVIEW VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V 0V tPHL 1.5 V 1.5 V VOL VOH Output 1.5 V 1.5 V 0V 1.5 V VOL tPLZ Output Waveform 1 S1 at 7 V (see Note C) tPLH tPHL 1.5 V tPZL VOH Output 3V Output Control 1.5 V tPLH 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION Input (see Note B) th Output Waveform 2 S1 at Open (see Note C) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NON-INVERTING OUTPUTS 1.5 V tPZH 3.5 V VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement. Figure 2. Load Circuit and Voltage Waveforms 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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