TC255P 336- × 244-PIXEL CCD IMAGE SENSOR SOCS057 – JUNE 1996 • • • • • • • • • • • • • • Medium-Resolution, Solid-State Image Sensor for Low-Cost B/W TV Applications 324(H) x 243(V) Active Elements in Image Sensing Area 10-µm Square Pixels Fast Clear Capability Electronic Shutter Function From 1/60–1/50000 s Low Dark Current Electron-Hole Recombination Antiblooming Dynamic Range . . . 66 dB Typical High Sensitivity High Blue Response 8-Pin Dual-In-Line Plastic Package 4-mm Image-Area Diagonal Solid-State Reliability With No Image Burn-In, Residual Imaging, Image Distortion, Image Lag, or Microphonics High Photoresponse Uniformity DUAL-IN-LINE PACKAGE (TOP VIEW) IAG2 1 8 ABG ADB 2 7 IAG1 SUB 3 6 SAG OUT 4 5 SRG description The TC255P is a frame-transfer charge-coupled device (CCD) designed for use in B/W NTSC TV and specialpurpose applications where low cost and small size are desired. The image-sensing area of the TC255P is configured in 243 lines with 336 elements in each line. Twelve elements are provided in each line for dark reference. The blooming-protection feature of the sensor is based on recombining excess charge with charge of opposite polarity in the substrate. This antiblooming is activated by supplying clocking pulses to the antiblooming gate, which is an integral part of each image-sensing element. The sensor can be operated in a noninterlace mode as a 324(H) by 243(V) sensor with low dark current. The device can also be operated in an interlace mode, electronically displacing the image-sensing elements during the charge integration in alternate fields, and effectively increasing the vertical resolution and minimizing aliasing. One important aspect of this image sensor is its high-speed image-transfer capability. This capability allows for an electronic-shutter function comparable to interline-transfer and frame-interline-transfer sensors without the loss of sensitivity and resolution inherent in those technologies. The charge is converted to signal voltage with a 12-µV per electron conversion factor by a high-performance charge-detection structure with built-in automatic reset and a voltage-reference generator. The signal is buffered by a low-noise two-stage source-follower amplifier to provide high output-drive capability. The TC255P uses TI-proprietary virtual-phase technology, which provides devices with high blue response, low dark signal, high photoresponse uniformity, and single-phase clocking. The TC255P is characterized for operation from –10°C to 45°C. This MOS device contains limited built-in gate protection. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to SUB. Under no circumstances should pin voltages exceed absolute maximum ratings. Avoid shorting OUTn to ADB during operation to prevent damage to the amplifier. The device can also be damaged if the output terminals are reverse-biased and an excessive current is allowed to flow. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments. Copyright 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2-1 TC255P 336- × 244-PIXEL CCD IMAGE SENSOR SOCS057 – JUNE 1996 functional block diagram Image Area With Blooming Protection IAG2 ADB 1 Dark-Reference Elements IAG1 Clear Line OUT 3 6 Storage Area Amplifier 4 SAG Serial Register ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ Clearing Drain 2-2 7 ABG 2 2 Dummy Elements SUB 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SRG TC255P 336- × 244-PIXEL CCD IMAGE SENSOR SOCS057 – JUNE 1996 sensor topology diagram 324 Active Pixels 12 Buffer Column Effective-Imaging Area 243 Lines 1 Dark Line 1 Clear Line 244 Lines Storage Area 336 Pixels Dummy Pixels 2 12 324 Optical Black (OPB) 1 Dummy Pixel Active Pixels Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. ABG 8 I Antiblooming gate ADB 2 I Supply voltage for amplifier-drain bias SUB 3 IAG1 7 IAG2 OUT Substrate I Image-area gate 1 1 I Image-area gate 2 4 O Output SAG 6 I Storage-area gate SRG 5 I Serial-register gate POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2-3 TC255P 336- × 244-PIXEL CCD IMAGE SENSOR SOCS057 – JUNE 1996 detailed description The TC255P consists of five basic functional blocks: 1) the image-sensing area, 2) the image-clear line, 3) the image-storage area, 4) the serial register, and 5) the charge-detection node and output amplifier. image-sensing area Cross sections with potential-well diagrams and top views of image-sensing and storage-area elements are shown in Figure 1 and Figure 2. As light enters the silicon in the image-sensing area, free electrons are generated and collected in the potential wells of the sensing elements. During this time, the antiblooming gate is activated by the application of a burst of pulses every horizontal-blanking interval. This prevents blooming caused by the spilling of charge from overexposed elements into neighboring elements. To generate the dark reference that is necessary in subsequent video-processing circuits for restoration of the video-black level, there are 12 columns of elements on the left edge of the image-sensing area shielded from light. There is also one column of elements on the right side of the image-sensing area and one line between the image-sensing area and the image-clear line. 10 µm Light Clocked Barrier IAG 10 µm Virtual Barrier Antiblooming Gate ABG Antiblooming Clocking Levels Virtual Well Clocked Well Accumulated Charge Figure 1. Charge-Accumulation Process SAG Clocked Phase Virtual Phase Channel Stops Figure 2. Charge-Transfer Process image-clear line During start-up or electronic-shutter operations, it is necessary to clear the image area of charge without transferring it to the storage area. In such situations, the two image-area gates are clocked 244 times without clocking the storage-area gate. The charge in the image area is then cleared through the image-clear line. 2-4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TC255P 336- × 244-PIXEL CCD IMAGE SENSOR SOCS057 – JUNE 1996 image-storage area After exposure, the image-area charge packets are transferred through the image-clear line to the storage area. The stored charge is then transferred line by line into the serial register for readout. Figure 3 illustrates the timing to (1) transfer the image to the storage area and (2) to transfer each line from the storage area to the serial register. serial register After each line is clocked into the serial register, it is read out pixel by pixel. Figure 3 illustrates the serial-register clock sequence. 244 Cycles Composite Blank Integration Time ABG Electronic Shutter Operation 244 Clocks 244 Clocks IAG1 IAG2 SAG 339 Cycles SRG t = 80 ns SAG 1) 2) 3) IAG1 SRG IAG2 1) End of serial readout of line 2) Transfer of new line to serial register 3) Beginning of readout of new line SAG SRG Expanded Section of Parallel Transfer Figure 3. Timing Diagram POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2-5 TC255P 336- × 244-PIXEL CCD IMAGE SENSOR SOCS057 – JUNE 1996 charge-detection node and output amplifier The buffer amplifier converts charge into a video signal. Figure 4 shows the circuit diagram of the charge-detection node and output amplifier. As charge is transferred into the detection node, the potential of this node changes in proportion to the amount of signal received. This change is sensed by an MOS transistor and, after proper buffering, the signal is supplied to the output terminal of the image sensor. After the potential change is sensed, the node is reset to a reference voltage supplied by an on-chip reference generator. The reset is accomplished by a reset gate that is connected internally to the serial register. The detection node and buffer amplifier are located a short distance from the edge of the storage area; therefore, two dummy cells are used to span this distance. Reference Generator Q0 ADB Q2 Q1 Q3 QR Q5 SRG Detection Node VO Q4 Figure 4. Buffer Amplifier and Charge-Detection Node 2-6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Q6 TC255P 336- × 244-PIXEL CCD IMAGE SENSOR SOCS057 – JUNE 1996 spurious-nonuniformity specification The spurious-nonuniformity specification of the TC255P is based on several sensor characteristics: • • • Amplitude of the nonuniform pixel Polarity of the nonuniform pixel – Black – White Column amplitude The CCD sensor is characterized in both an illuminated condition and a dark condition. In the dark condition, the nonuniformity is specified in terms of absolute amplitude as shown in Figure 5. In the illuminated condition, the nonuniformity is specified as a percentage of the total illumination as shown in Figure 6. The specification for the TC255P is as follows: WHITE SPOT (DARK) WHITE SPOT (ILLUMINATED) COLUMN (DARK) COLUMN (ILLUMINATED) BLACK SPOT (ILLUMINATED) x < 15 mV x < 15% x < 0.5 mV x < 1 mV x < 15% † A white/black pair nonuniformity will be no more than 2 pixels even for integration times of 1/60 second. WHITE/BLACK† PAIR x < 9mV The conditions under which this specification is defined are as follows: • • • The integration time is 1/60 second except for illuminated white spots, illuminated black spots and white/black pair nonuniformities; in these three cases, the integration time is 1/240 second. The temperature is 45°C. The CCD video-output signal is 60 mV ± 10 mV. mV % Amplitude % of Total Illumination t Figure 5. Pixel Nonuniformity, Dark Condition POST OFFICE BOX 655303 t Figure 6. Pixel Nonuniformity, Illuminated Condition • DALLAS, TEXAS 75265 2-7 TC255P 336- × 244-PIXEL CCD IMAGE SENSOR SOCS057 – JUNE 1996 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC: ADB (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 15 V Input voltage range, VI: ABG, IAG1, IAG2, SAG, SRG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 15 V to 15 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 10°C to 45°C Storage temperature range, TSTG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30°C to 85°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltages are with respect to the substrate terminal. recommended operating conditions Supply voltage, VCC ADB MIN NOM MAX 11 12 13 Substrate bias voltage 0 IAG1 IAG2 IAG1, SAG Input voltage, VI SRG ABG 1.5 2 2.5 Low level –10.5 –10 –9.5 High level 1.5 2 2.5 Low level –10.5 –10 –9.5 High level 1.5 2 2.5 Low level –10.5 –10 –9.5 High level 3.5 4 4.5 Low level –6 12.5 25 SAG 12.5 6.25 OUT 0.008 Operating free-air temperature, TA ‡ Adjustment is required for optimum performance. POST OFFICE BOX 655303 –10 • DALLAS, TEXAS 75265 MHz 12.5 6 Plastic package thermal conductivity 2-8 –7 6.25 IAG1, IAG2 SRG Load capacitive V –2.5 –8 ABG Clock frequency, frequency fclock l k V V High level Intermediate level‡ UNIT pF J/cm•s•°C 45 °C TC255P 336- × 244-PIXEL CCD IMAGE SENSOR SOCS057 – JUNE 1996 electrical characteristics over recommended operating ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER Dynamic range (see Note 2) MIN Antiblooming disabled (see Note 3) Charge-conversion factor TYP† MAX UNIT 12 13 µV/e 0.9995 0.99999 66 11 Charge-transfer efficiency (see Note 4) Signal-response delay time, τ (see Note 5) dB 20 Gamma (see Note 6) 0.97 0.98 ns 0.99 350 Ω Noise-equivalent signal without correlated double sampling 62 electrons Noise-equivalent signal with correlated double sampling (see Note 7) 31 electrons Output resistance ADB (see Note 8) Rejection ratio 13 15 SRG (see Note 9) 50 ABG (see Note 10) 40 Supply current 5 IAG1, IAG2 Input capacitance, capacitance Ci 18 dB 10 mA 1000 SRG 22 ABG 850 pF SAG 2000 † All typical values are at TA = 25°C. NOTES: 2. Dynamic range is – 20 times the logarithm of the mean-noise signal divided by saturation-output signal. 3. For this test, the antiblooming gate must be biased at the intermediate level. 4. Charge-transfer efficiency is one minus the charge loss per transfer in the output register. The test is performed in the dark using an electrical-input signal. 5. Signal-response delay time is the time between the falling edge of the SRG pulse and the output-signal valid state. 6. Gamma (γ) is the value of the exponent is the equation below for two points on the linear portion of the transfer-function curve (this value represents points near saturation). ǒ Ǔ +ǒ Exposure (2) Exposure (1) g Ǔ Output signal (2) Output signal (1) 7. A three-level serial-gate clock is necessary to implement correlated double sampling. 8. ADB rejection ratio is – 20 times the logarithm of the ac amplitude at the output divided by the ac amplitude at ADB (see Figure 11 for measured ADB rejection ratio as a function of frequency). 9. SRG rejection ratio is – 20 times the logarithm of the ac amplitude at the output divided by the ac amplitude at SRG. 10. ABG rejection ratio is – 20 times the logarithm of the ac amplitude at the output divided by the ac amplitude at ABG. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2-9 TC255P 336- × 244-PIXEL CCD IMAGE SENSOR SOCS057 – JUNE 1996 optical characteristics, TA = 40°C (unless otherwise noted) PARAMETER Sensitivity MIN TYP No IR filter MAX 350 With IR filter UNIT mV/lx 45 Saturation signal, Vsat (see Note 11) Antiblooming disabled, Interlace off 600 750 mV Maximum usable signal, Vuse Antiblooming enabled 200 250 mV 100 200 50000 62500 Blooming-overload ratio (see Note 12) Image-area well capacity Smear (see Notes 13 and 14) Dark current electrons 0.00012 Interlace disabled, TA = 21°C 0.20 nA/cm2 200 µV Dark signal Pixel uniformity Output signal = 60 mV ± 10 mV 15 mV Column uniformity Output signal = 60 mV ± 10 mV 0.5 mV 15 % 1/60 s Shading Electronic-shutter capability 1/15000 NOTES: 11. Saturation is the condition in which further increase in exposure does not lead to further increase in output signal. 12. Blooming is the condition in which charge is induced in an element by light incident on another element. Blooming-overload ratio is the ratio of blooming exposure to saturation exposure. 13. Smear is a measure of the error introduced by transferring charge through an illuminated pixel in shutterless operation. It is equivalent to the ratio of the single-pixel transfer time to the exposure time using an illuminated section that is 1/10 of the image-area vertical height with recommended clock frequencies. 14. The exposure time is 16.67 ms, the fast-dump clocking rate during vertical transfer is 12.5 MHz, and the illuminated section is 1/10 of the height of the image section. timing requirements tr tf 2-10 Rise time Fall time MIN NOM ABG 10 40 IAG1, IAG2 (fast clear) 10 10 IAG1, IAG2 (image transfer) 10 20 SAG 10 20 SRG 10 40 ABG 10 40 IAG1, IAG2 (fast clear) 10 10 IAG1, IAG2 (image transfer) 10 20 SAG 10 20 SRG 10 40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT ns ns TC255P 336- × 244-PIXEL CCD IMAGE SENSOR SOCS057 – JUNE 1996 PARAMETER MEASUREMENT INFORMATION Blooming Point With Antiblooming Enabled VO Blooming Point With Antiblooming Disabled Dependent on Well Capacity Vsat (min) Level Dependent Upon Antiblooming Gate High Level Vuse (max) DR Vuse (typ) SNR Vn DR (dynamic range) + 20 log SNR (signal-to-noise-rate) ǒ Ǔ V sat Vn + 20 log ǒ Lux (light input) dB V use Vn Ǔd B Vn = noise-floor voltage Vsat (min) = minimum saturation voltage Vuse (max) = maximum usable voltage Vuse (typ) = typical user voltage (camera white clip) NOTES: A. Vuse (typ) is defined as the voltage determined to equal the camera white clip. This voltage must be less than Vuse (max). B. A system trade-off is necessary to determine the system light sensitivity versus the signal/noise ratio. By lowering the Vuse (typ), the light sensitivity of the camera is increased; however, this sacrifices the signal/noise ratio of the camera. Figure 7. Typical Vsat, Vuse Relationship POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2-11 TC255P 336- × 244-PIXEL CCD IMAGE SENSOR SOCS057 – JUNE 1996 PARAMETER MEASUREMENT INFORMATION 1.5 V to 2.5 V SRG – 8.5 V – 8.5 V to – 10 V 0% OUT 90% 100% CCD Delay t 10 ns 15 ns Sample and Hold Figure 8. SRG and CCD Output Waveforms 2-12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TC255P 336- × 244-PIXEL CCD IMAGE SENSOR SOCS057 – JUNE 1996 TYPICAL CHARACTERISTICS CCD SPECTRAL RESPONSIVITY Responsivity – A/W 1 0.1 0.01 0.001 300 400 500 600 700 800 900 1000 900 1000 Incident Wavelength – nm Figure 9 CCD QUANTUM EFFICIENCY Quantum Efficiency 1 0.1 0.01 0.001 300 400 500 600 700 800 Incident Wavelength – nm Figure 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2-13 TC255P 336- × 244-PIXEL CCD IMAGE SENSOR SOCS057 – JUNE 1996 TYPICAL CHARACTERISTICS 20 18 ADB Rejection Ratio – dB 16 14 12 10 8 6 4 2 0 0 5 10 15 20 25 f – Frequency – MHz Figure 11. Measured ADB Rejection Ratio as a Function of Frequency Noise-Power Spectral Density – nV/rt Hz 300 250 200 150 100 50 0 0 5 10 15 20 f – Frequency – MHz Figure 12. Noise-Power Spectral Density 2-14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 TC255P 336- × 244-PIXEL CCD IMAGE SENSOR SOCS057 – JUNE 1996 APPLICATION INFORMATION TMC57253 VCC 1 2 3 4 5 6 7 8 9 10 11 12 VAB VCC WIN TEST1 GND TEST3 TEST2 MON1 MON2 MON3 MON4 EFSEL2 EFSEL1 EFSEL3 VCC MINSEL WSEL1 WSEL2 SAG VCC SSEL2 GND SRG SRM SSEL3 DLSEL VR HR PHSEL2 SHTCOM PHSEL1 SRGSEL VACT 64 63 62 61 60 59 VCC 58 57 VABM ABOUT VABL GND ABIN IA1OUT VIA ABMIN IA1IN IA2OUT IA2IN GND SAIN SRIN SAOUT VS SRMIN SROUT VSM GND 24 23 22 21 20 19 18 17 16 15 14 13 VABM VABL VIA VS VSM 56 55 54 53 52 TC255P 8 ABG IAG2 7 ADB IAG1 6 SUB SAG 5 SRG OUT 51 50 49 1 2 ADB 3 SUB 4 FI 32 IAG2 TMC57750 SSEL1 VD 30 31 CPOB2 HD 28 29 IAG1 PUC VCC 27 CPOB1 SCAN VCC GND ABM VCC CLKIN 25 26 ABG CBLK CSYNC XIN 24 ABGSEL TEST4 MCLK/2 XSEL XOUT CPOB1 22 23 FSSEL MCLK/4 CSYNC 20 21 DSSEL EU CDS GND 19 CBLK ED S/H 17 18 SHTMON ED EU WINDOW 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VAB VCC GND EN 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Buffer and Preamp 1.0 V 4.0 V AMPTUNE VAB VABL 1.0 V 14 V 3V Low-Pass FIlter CBLK SYNCLVL HICPLVL SULVL SULVL SYNCLVL VREF HICPLVL HIB WIDTH CBLK DELAYIN CTRLVL WIDLVL 4.7 µF YIN 1.2 V AMPOUT SYNCLVL 0.1 µF 33 100 µF VCC 32 VIDEO 31 75Ω GND 30 CSYNC CSYNC 29 CPOB1 CLAMP 28 CHARAIN 27 VCC VCC 26 YHIN 25 APOUT 24 APGAIN 23 APFIL SN761210 GAINSEL CHD 1.9 V 1.2 V 0.1 µF AMPTUNE HICPLVL SULVL 1 DATAIN 2 S/HFB 3 SHP S/H 4 SHD1 CDS 5 SHD2 6 GND 7 AGCFIL 8 AGCLVL 9 AGCMAX 10 AGCOUT 11 AMPIN GND AGCFB 0.1 µF IRISFIL LOB 44 43 42 41 40 39 38 37 36 35 34 25 MHz DC VOLTAGES VIA, VM, VS 12 V VCC 5V ADB 22 V SUB 10 V VABM 7.5 V EU VCC OUT HOBP GND VCC CENTER 5V IRIS WINDOW VCC 4.7 µF ED VCC WIDLVL (see Note B) CDS VCC CTRLVL VCC S/H 0.1 µF 12 13 14 15 16 17 18 19 20 21 22 AMPTUNE NOTES: A. Decoupling capacitors are not shown. B. TI recommends designing AC coupled systems. WIN CPOB1 0.1 µF To Monitor Figure 13. Typical Application Circuit Diagram POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2-15 TC255P 336- × 244-PIXEL CCD IMAGE SENSOR SOCS057 – JUNE 1996 APPLICATION INFORMATION SUPPORT CIRCUITS DEVICE PACKAGE APPLICATION FUNCTION TMC57750PM 64 pin flatpack Timing generator EIA-170 timing and CCD control signals TMC57253DSB 24 pin small outline Driver Driver for ABG, IAG1, IAG2, SAG, and SRG SN761210FR 44 pin flatpack Video processor SYNC, BLANK, AGC, IRIS, CLAMP, S/H, CDS, and WINDOW Figure 13. Typical Application Circuit Diagram (Continued) 2-16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TC255P 336- × 244-PIXEL CCD IMAGE SENSOR SOCS057 – JUNE 1996 MECHANICAL DATA The package for the TC255P consists of a plastic base, a glass window, and an 8-lead frame. The glass window is sealed to the package by an epoxy adhesive. The package leads are configured in a dual in-line organization and fit into mounting holes with 2,54 mm (0.1 in) center-to-center spacings. TC255P (8 pin) Package Center 10,05 9,95 9,00 8,90 0,80 0,70 Optical Center 10,05 9,95 5,19 4,93 ÎÎÎ ÎÎ ÎÎ Î ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 2,67 2,53 10,16 9,00 8,90 4,20 3,93 0,27 0,23 Chip Surface 0,64 0,50 1,10 1,20 3,50 1,27 1,50 1,40 ÎÎ ÎÎÎÎÎ ÎÎ ÎÎÎÎÎ 0,46 2,54 0,30 6/96 ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2-17 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated