CXB1818Q Laser Diode Driver Description The CXB1818Q is a high-speed monolithic Laser Diode Driver/Current Switch with ECL/PECL input level. Open collector outputs are provided at the output pins (Q, QBX) and have the capacity of driving modulation current of 50mAp-p at a maximum data rate of 622Mbps. Along with the modulation current generator there is the laser diode bias current generator which has capacity of sourcing up to 60mA (Bias). The laser diode bias current can be controlled by either a voltage or current into the bias adjust pin (BiasAdj) and the bias set pin (SBias), depending on how these pins are configured. Control of the bias current is achieved through the APC (Automatic Power Control) circuit. In order to avoid having a large current go through the laser diode, this IC also provides an Activity detector function for laser protection. The Activity detector circuit detects data edge transitions and if no data transition occurs after a certain period, then both the modulation and bias currents are shutdown. The bias currents are shut it down by in order to pull down the output voltage of APC OP.Amp. When the automatic shutdown is conducted, it is possible to select whether the laser diode alarm output is activated or not. Additionally, this IC has the DFF for the input signal correction and the internal Duty Cycle correction circuit that can control the falling edge of the input pulse up to a maximum of 1.0ns(Min.). Features • Maximum data rate (NRZ): 622Mbps • Alarm and Shutdown function • DFF for input signal correction • Input signal Duty cycle correction • Automatic Power Control (APC) for bias current • Activity detector function for laser protection • Alarm signal mask function during shutdown • Differential PECL inputs or AC coupled inputs 40 pin QFP (Plastic) Applications • SONET/SDH: 622Mbps • Fibre channel: 531Mbps Absolute Maximum Ratings • Supply voltage VCC – VEE –0.3 to +6.0 VEE to VCC • Input voltage VIN • Differential input voltage | VD – VDB | 0 to 2.5 • Bias output current 0 to 80 • SBias input/output current 0 to 5 • Bias control current IBset (Ibiasadj) 0 to 5 • Bbias control voltage VBset (Vbiasadj) 0 to 3 • Modulation output current 70 • Modulation adjust current IQset (Idrvadj) 0 to 15 • Storage temperature Tstg –65 to +150 Recommended Operating Conditions • DC supply voltage 3.14 to 3.46 VCC – VEE • Operating ambient temperature Ta –40 to +85 V V V mA mA mA V mA mA °C V °C Structure Bipolar silicon monolithic IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E99227-PS CXB1818Q SDN SDNB RS RSB MaskSel VCC2 D DB VEE2 Clk Block Diagram and Pin Configuration 30 29 28 27 26 25 24 23 22 21 Vbb Gen. Reference Generator 20 ClkB 19 FFSel 18 ADCDis 17 Timer 16 CompB 15 CompA 14 DrvAdj D-FF Tset 31 VREF 32 VCC6 33 LDAlm 34 LDAlmB 35 MUX Vref In_ALM Duty Cycle Cont DRV Cont VCC3 36 VEE3 37 13 DrvMon WCompIn 38 12 TM RsetPD 39 APCOut 40 11 VCC1 VEE4 BiasAdj SBias Bias 6 7 8 9 10 VEE1 5 QBX 4 NC 3 Q 2 VEE5 1 VCC4 Bias Circuit –2– CXB1818Q Pin Description Pin No. Symbol Typical pin voltage [V] DC Equivalent circuit Description AC 1 VCC4 3.3 Positive power supply for APC circuit. 2 VEE4 0 Negative power supply for APC circuit. 3 BiasAdj 1.5 to 0 VCC 4 SBias 0mA to 2.5mA 3 5 Bias 0mA to 60mA 6 VEE5 0 7 9 4 5 Bias current setting. 260 30 Bias current setting or monitor. 10pF 8 240 Bias current output. Open collector output. VEE Negative power supply for bias circuit. Q 6mA to 30mA∗1 1.3 to 3.3 6mA to 50mA∗2 QBX 6mA to 30mA∗1 1.3 to 3.3 6mA to 50mA∗2 7 Modulation current output. Open collector output. 9 Complementary current output. Q and QBX are not symmetrical output. Use Q output for laser diode. Current Source VEE 8 NC — 10 VEE1 0 Negative power supply for driver circuit. 11 VCC1 3.3 Positive power supply for driver circuit. — No connected. VEE 12 TM 1.5 Chip temperature monitor. 10 12 VCC 13 0mA to 1.4mA DrvMon Rmon 14 13 14 DrvAdj 0mA to 9mA 22.5 150 VEE ∗1 Ta = –40 to 0°C ∗2 Ta = 0 to +85°C –3– Modulation current (IQ) monitor. IQ is monitored by connecting a resistor (Rmon) to this pin. Modulation current (IQ) setting. CXB1818Q Pin No. 15 Symbol Typical pin voltage [V] DC Equivalent circuit Description AC VCC CompA Modulation current driver compensation. Normally, connects 180pF capacitor between CompA and CompB pins. 15 180pF 16 30pF 16 10k CompB VEE VCC 2.1k Ctimer 2.4k 100 17 17 2.4k Timer 10pF 25µA 200µA VEE Capacitor connection for activity detector (IN_ALM) operation. This pin sets the period of inactive time for activity detector. Inactive time is controlled by connecting a capacitor to this pin. VCC 3.8k 18 ADCDis VEE to VCC (open) Activity detector circuit control. High (connected to VCC or open): Activity detector is disable. Low (connected to VEE): Activity detector is enable. 3.8k 35k 35k 35k 35k 18 15µA VEE VCC 9k 19 FFSel VEE or open 4.5k 4.5k 19 100k 4.5k VEE –4– 4.5k Input data D-FF selection control. High (open): FF not used (Through mode) Low (connect to VEE): FF used (FF mode) CXB1818Q Pin No. Symbol Typical pin voltage [V] DC Equivalent circuit Description AC VCC 20 ClkB 1.6 to 2.4 550 550 20 Differential PECL clock input. 200 21 200 400µA 21 Clk 22 VEE2 1.6 to 2.4 VEE Negative power supply for data input circuit. 0 25 300 23 DB 1.6 to 2.4 300 24 200 23 10k 200 24 D 1.6 to 2.4 10k 300µA 1mA 25 VCC2 3.3 22 Positive power supply for data input circuit. VCC 9k 26 MaskSel VEE or open 4.5k 4.5k 1k 26 2.2k 2.2k VEE VCC 27 RSB 100µA 0.5 2.5k 28 15k 27 28 RS Differential PECL data input. 2.0 5k VEE –5– Alarm signal control for optical power output forced shutdown. High (open): Alarm signal is High for shutdown. Low (connect to VEE): Alarm signal stays Low for shutdown. Window comparator top/bottom threshold voltage for LD_ALARM. The alarm (fault) assert voltage can be set by the external resistor. Default voltages are RS equal to 2.0V and RSB equal to 0.5V. (Option) CXB1818Q Pin No. Symbol Typical pin voltage [V] DC Equivalent circuit AC Description VCC 29 SDNB 5k 5k 0 to 3.3 5k 5k Complementary TTL input to disable the output current. (Shutdown input) When left open, High. 300 29 300 30 30 SDN 60µA 0 to 3.3 60µA VEE Output duty cycle control. This pin controls the falling edge of the input High pulse. Variable delay limit of that is from 0 to 1.0ns. Duty cycle is controlled by connecting a resistor value between VCC and this pin. VCC 2.4k 2.4k Rset 20pF 31 31 Tset 70µA 220 VEE 140 VCC 300 300 200 32 32 VREF 1.7 2.4k 9.1k 1.9mA Temperature compensated reference voltage for APC. Approximately 1.7V (Constant for VEE reference) VEE 33 VCC6 34 LDAlm Positive power supply for alarm output circuit. 3.3 0.2 to 3.0 VCC 34 35 35 LDAlmB 0.2 to 3.0 VEE –6– Activates when the fault is detected in the laser monitor diode circuit. (Pseudo LVTTL output) CXB1818Q Pin No. Symbol Typical pin voltage [V] DC Description Equivalent circuit AC 36 VCC3 3.3 Positive power supply for signal detection circuit. 37 VEE3 0 Negative power supply for signal detection circuit. VCC 550 38 WCompIn 550 RS 38 200 RSB 200 APC alarm signal control. 200 VEE VCC 300 300 200 39 39 RsetPD Monitor PD connection. 1.8mA VEE VCC 40 APCOut APC operational amplifier output. This signal controls the bias adjust pins. (BiasAdj and SBias) 40 500 VEE –7– CXB1818Q Electrical Characteristics DC Electrical Characteristics (VCC = 3.14 to 3.46V, VEE = 0V, Ta = –40 to +85°C) Symbol Item Condition Min. Typ. Max. Unit DC supply voltage Vdc VCC – VEE 3.14 3.3 3.46 V Supply current IEE IQ = 0mA, IBIAS = 0mA –80 –57 — mA IQ1 Ta = –40 to 0°C 6 — 30 IQ2 Ta = 0 to +85°C 6 — 50 VCC – 2 — VCC V Modulation output current range mA Modulation output voltage range VQ Ratio of IQ vs. IQset IQ vs IQset 4 6 9 — Bias output current range IB 0 — 60 mA Bias output voltage range VB VCC – 2 — VCC V Ratio of IB vs. IBset IB vs IBset 14 22 28 — ECL input High voltage VEIH VCC – 1.17 — VCC – 0.81 ECL input Low voltage VEIL VCC – 1.84 — VCC – 1.48 SDN, SDNB input High voltage VTIH 2 — VCC SDN, SDNB input Low voltage VTIL 0 — 0.8 LDA, LDAB output High voltage VTOH Iin = –0.4mA 2.4 — — LDA, LDAB output Low voltage VTOL Iin = 2.0mA — — 0.5 1.5 1.7 1.9 –500 — +500 Reference bias voltage for OP Amp VREF Operating current range of VREF VREFdrv V µA (VCC = 3.14 to 3.46V, VEE = 0V, Ta = –40 to +85°C) AC Electrical Characteristics Item Symbol Condition Min. Typ. Max. Maximum data rate fdmax 622 Rise time (20 to 80%) tr IQ = 20mA, RL = 25Ω 200 Fall time (20 to 80%) tf IQ = 20mA, RL = 25Ω 200 Max. variable High pulse width by duty cycle control tdelay Data rate = 622Mbps Max. setting time of IN_Alarm ts_alm Shutdown time tsut_off 10 Shutdown recovery time tsut_on 100 Maximum set up time TS 200 Maximum hold time TH 200 Unit Mbps ps 1.0 ns 20 –8– µs ps CXB1818Q DC and AC Electrical Characteristics for OpAmp of APC Circuit (VCC = 3.14 to 3.46V, VEE = 0V, Ta = –40 to +85°C) Item Symbol Condition Min. Typ. Max. Unit Input voltage range VIN 1.2 — 2.8 V Output voltage range VO 0.6 — 2 V Input bias current IB — 7 — µA Input offset voltage VOFF — 2.5 — mV Input offset current IOFF — 0.7 — µA Input impedance ZIN — 12 — kΩ Output drive current IO –5.0 — 1.0 mA Through rate SR — 1.9 — V/µs Open loop gain Av — 55 — dB Unity gain band width funit — 20 — MHz –9– CXB1818Q Description of Each Function Block 1. Data Buffer, Clock Buffer Data Buffer and Clock Buffer are comprised of the data buffer, clock buffer, DFF, MUX and delay generator. ECL/PECL data is input to the data buffer at a maximum data rate of 622Mbps. The input data DFF selection pin (Pin 19 FFSel) can select whether the input data is used in through mode or the signal which is corrected by the clock signal in the DFF is used. When the FFSel is open, the data becomes through mode, when the FFsel is connected VEE,the data becomes DFF mode. And, this data is input to the delay circuit. The delay circuit adds a delay to the falling edge of the pulse up to a maximum of 1.0ns for the D input signal High pulse (Q output current pulse). The delay is set by an external resistor between the delay set pin (Pin 31 Tset) and VCC. The relation between the High pulse width and the set resistance (Rset) is shown in Fig. 1. The Vbb generator provides a reference bias current to the data buffer for AC coupling inputs. 2. Modulation Current Generator This circuit modulates the laser diode and the modulation current can be set by feeding the current to the modulation current set pin (Pin 14 DrvAdj). The relation between the modulation current (IQ) and the modulation set current (IQset) is shown in Fig. 2. There is also a modulation current monitor pin (Pin 13 DrvMon) that allows the IC user to monitor the modulation current by putting an external fixed resistor between VCC and DrvMon pins, and the modulation current can be monitored by measuring the voltage of DrvMon pin. The relation between the modulation current (IQ) and the DrvMon current (Idrvmon) is shown in Fig. 7. 3. Laser Diode Bias Current Generator This circuit is a very large current source capable of sourcing up to 60mA of bias current to the laser diode. The circuit is a 22 to 1 (for current – current setting) current mirror that can be controlled externally two ways. The first method is to short BiasAdj (Pin 3) and SBias (Pin 4) together and inject a control current (IBset) into the two pins. Bias (Pin 5) is connected to the laser diode. Laser diode bias current vs. control current (IBset) characteristics is shown in Fig. 3. The second method is to tie SBias (Pin 4) to VCC and tune BiasAdj (Pin 3) with a voltage source. Varying the voltage at the BiasAdj pin will vary the current through the laser diode. Laser diode bias current vs. control voltage characteristics is shown in Fig. 4. 4. APC (Automatic Power Control) Circuit The APC circuit is comprised of the window comparator, APC OpAmp, and laser diode alarm circuit. The APC OpAmp is normally configured as an inverting integrator. The inverting input is connected to the photodiode that monitors the optical power output from the laser diode. The photodiode converts the optical power received from the laser diode to a current. The output of the OpAmp then drives the laser diode current bias adjust pin (BiasAdj), and the laser diode current bias set pin (SBias) is shorted to VCC via a resistor. With the OpAmp configured as an inverting integrator, the OpAmp can tune the laser diode current inversely to the current in the photodiode. That is to say that if a Low current is detected by the photodiode the integrator output goes up causing more bias current to flow through the laser diode. If the photodiode current is High, the output of the OpAmp will go Low causing less bias current to flow through the laser diode. When the output of the APC OpAmp (Pin 40 APCOut) is connected to the window comparator input pin (Pin 38 WCompIn), the function of the window comparator detects the voltage which is outside of the reference voltage range for each comparator (RS, RSB). When this happens, the comparator outputs cause the laser diode alarm output (LDAlm) to go High alerting the system that the laser diode current is in the outside of the range. – 10 – CXB1818Q The laser diode alarm output state can be controlled by the alarm signal control pin (Pin 26 MaskSel) for the optical power output forced shutdown. When the automatic shutdown is conducted and MaskSel pin is left open, the laser diode alarm output goes High. The laser diode alarm output is kept Low (disable) by connecting MaskSel pin to VEE. 5. Shutdown and Input Alarm Circuits These circuits disable both the modulation current and the bias current under various conditions. The function block diagram for all of the shutdown mechanisms for the circuit is shown in Fig. 5. The Shutdown circuit has complementary TTL input to disable the output current. Shown below is the desired truth table for the shutdown function. SDN SDNB Output current Low Low Off Low High On High Low Off High High Off The Activity detector (In_ALM) circuit is designed to detect the input data edge transition. If there is no input data transition over a certain period determined by the user (TACT), the Shutdown circuit is enabled, causing the modulation current and bias current to be shutdown. The Inactive time (TACT) is set by the external capacitor value between Timer (Pin 17) and VCC. The relation between the Inactive time and Ctimer is shown in Fig.6. SDN Shutdown SDNB Switch D To modulation and bias current Shutdown circuits In_ALM DB Timer ADCDis Fig.5. Shutdown and In_ALM Functional Block Diagram 6. Others Pay attention to handling this IC because its electrostatic discharge strength is weak. The Tset pin (Pin 31) should be connected to VCC through a resistor. Do not leave this pin open or connect to VCC directly. – 11 – CXB1818Q DC Electrical Characteristics Measurement Circuit 30 29 V V 28 27 26 25 24 23 22 21 20 Vbb Gen. Reference Generator D-FF 2k 31 –500 to +500µA 32 MUX Vref 19 V 18 33 17 In_ALM 0.1µF V 34 –0.4mA or +2.0mA 16 Duty Cycle Cont 35 15 DRV Cont V 36 14 37 13 38 12 1k A V 39 Bias Circuit 1k 11 40 V 180pF 1 2 3 4 5 6 A A 7 A 8 9 10 25 0 to –2V A 3.14 to 3.46V – 12 – CXB1818Q AC Electrical Characteristics Measurement Circuit PECL input 51 28 29 27 26 25 0.1µF 24 23 22 21 20 Vbb Gen. Reference Generator PECL input 51 0.1µF 30 PECL input D-FF 31 100k 32 MUX Vref 19 18 33 34 0.1µF 16 Duty Cycle Cont 35 14 37 13 38 12 39 180p 15 DRV Cont 36 1k Bias Circuit 1µF 11 40 1µF 1 2 3 4 5 6 7 8 9 10 25 ZO = 50Ω Spectrum analizar 17 In_ALM Osilloscope 50Ω input – 13 – 3.14 to 3.46V CXB1818Q Application Circuit (at VCC = 3.3V, VEE = 0V) SDN SDNB PECL input 30 28 29 27 26 25 24 PECL input 23 22 21 20 Vbb Gen. Reference Generator PECL input D-FF 100pF 31 Rset MUX Vref 32 19 18 33 LDAlm 34 LDAlmB 35 16 Duty Cycle Cont Cpd 14 37 13 38 12 39 1k Bias Circuit Rf 11 40 1 R1 180pF 15 DRV Cont 36 Ctimer 17 In_ALM Rs Iset 2 3 4 5 6 15 7 8 5.1 9 10 20 Rpd 100pF 0.1µF 3.3V Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 14 – CXB1818Q 2.8 70 2.6 60 2.4 50 2.2 40 IQ [mA] Pulse width [ns] Example of Representative Characteristics 2.0 30 1.8 20 1.6 10 1.4 0 2 4 6 8 Rset [kΩ] 10 12 0 14 VQ = 0V VQ = –0.5V VQ = –1.0V VQ = –1.5V VQ = –2.0V 70 70 60 60 50 50 30 10 10 0.5 1 2.5 1.5 2 IBset [mA] 0 3 Fig. 3. Bias current (IBIAS) vs. Bias adjust current (IBset) characteristics 0.4 0.6 0.8 1.4 1 1.2 VBset [V] 1.6 Fig. 4. Bias current (IBIAS) vs. Bias adjust voltage (VBset) characteristics 70 70 VQ = 0V VQ = –1V VQ = –2V 60 60 50 50 IQ [mA] Input detection time [µs] 10 30 20 0 8 40 20 0 4 6 IQset [mA] Fig. 2. Modulation current (IQ) vs. IQset characteristics IBIAS [mA] IBIAS [mA] Fig. 1. Pulse width vs. Rset characteristics when 1.6ns input data pulse (622Mbps) is applied 40 2 0 40 30 30 20 20 10 40 10 0.5 1 1.5 2 2.5 3 Ctimer [nF] 3.5 4 0 4.5 0 0.2 0.4 0.6 0.8 1 Idrvmon [mA] 1.2 1.4 1.6 Fig. 7. Modulation current (IQ) vs. DrvMon current characteristics Fig. 6. Input detection time vs. Ctimer characteristics – 15 – CXB1818Q VCC = 0V VEE = –3.3V RL = 25Ω Ta = 27°C IQ = 30mA Single-phase input Pattern = PRBS223 – 1 Data Rate 622Mbps Ch.1: 150mV/div Time Base: 500ps/div Fig. 8. Electrical Output Waveform 2 VCC = 0V VEE = –3.3V FP – LD (λ = 1330nm) Ta = 27°C Single-phase input Pattern = PRBS223 – 1 Data Rate 622Mbps Filter (Cut Off 450MHz) Mask: STM4/OC12 1 3 Ch.2: 5.0mV/div Time Base: 500ps/div Fig. 9. Optical Power Output Waveform – 16 – CXB1818Q Package Outline Unit: mm 40PIN QFP (PLASTIC) + 0.35 1.5 – 0.15 + 0.1 0.127 – 0.05 9.0 ± 0.4 + 0.4 7.0 – 0.1 0.1 21 30 20 31 A 11 40 1 + 0.15 0.3 – 0.1 0.65 10 0.24 M 0° to 10° 0.5 ± 0.2 (8.0) + 0.15 0.1 – 0.1 DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-40P-L01 LEAD TREATMENT SOLDER / PALLADIUM PLATING EIAJ CODE QFP040-P-0707 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.2g JEDEC CODE NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 17 –