CXG1009TN High Isolation SPDT Switch Description The CXG1009TN is a high Isolation SPDT (Single Pole Dual Throw) switch MMIC for personal communication, cable TV and so on. This IC is designed using the Sony’s GaAs J-FET process and operates at a single positive control supply. Features • Single positive control supply operation • Insertion Loss 0.7 dB (Typ.) @1.0 GHz, Vctl (H)=3 V 0.8 dB (Typ.) @2.0 GHz, Vctl (H)=3 V • High Isolation 56 dB (Typ.) @1.0 GHz, Vctl (H)=3 V 47 dB (Typ.) @2.0 GHz, Vctl (H)=3 V • 10pin TSSOP package (3.2 × 2.8 mm) 10 pin TSSOP (Plastic) Absolute Maximum Ratings (Ta=25 °C) • Control voltage Vctl (H) – Vctl (L) 6 V • Control Current Ictl 2 mA • Operating temperature Topr –35 to +85 °C • Storage temperature Tstg –65 to +150 °C Applications • Basestation Lo switching. • Other Low Power SPDT applications requiring high isolation (e.g. Cable TV). Structure GaAs J-FET MMIC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E98712A8X CXG1009TN Electrical Characteristics VCTL (L) =0 V, VCTL (H) =3 V, Pin=10 dBm Item Insertion Loss 1 Isolation 1 Insertion Loss 2 Isolation 2 VSWR Switching Speed Control Current Symbol IL1 ISO1 IL2 ISO2 VSWR TSW ICTL 1 dB Compression (Ta=25 °C) Condition MIN. f ≤ 1 GHz 52 f ≤ 2 GHz 43 500 MHz ≤ f ≤ 2 GHz f = 5 MHz P1dB 16 TYP. 0.7 56 0.8 47 1.2 100 60 19 8 MAX. 1.1 1.2 1.5 200 50 Ω source and load impedance Block Diagram Package Outline/Pin Configuration 1 RF3 RF1 RF2 10 CTLB RF3 GND GND RF1 GND GND GND CTLA RF2 10pin TSSOP (PLASTIC) VCTLA VCTLB High Low Low High RF1-RF2 ON RF1-RF3 OFF RF1-RF2 OFF RF1-RF3 ON —2— UNit dB dB dB dB ns µA dBm dBm CXG1009TN Recommended Circuit RCTL (1kΩ) 1 CTLB 10 Cbypass (100pF) 2 9 3 RF1 RF3 CRF (100pF) CXG1009TN 8 CRF (100pF) 4 7 5 6 RCTL (1kΩ) CTLA Cbypass (100pF) RF2 CRF (100pF) ∗ It is necessary to use DC blocking capacitors CRF and bypass capacitors Cbypass. ∗ It is necessary to use control resistors RCTL , if current consumption needs to be reduced or ESD performance needs to be improved. ∗ It is necessary to oprate at low frequency, DC blocking capacitors CRF needs higher valves. Frequency characteristics Measurement Conditions : Vctl (L) =0 V, Vctl (H) =3 V, Pin=0 dBm CW, T=25 °C Insertion Loss and Isolation v.s. Frequency 0 –10 Insertion Loss –20 –2 –30 –3 –40 Isolation –4 –50 –60 –5 0 1 2 Frequency (GHz) —3— 3 Isolation (dB) Insertion Loss (dB) –1 CXG1009TN Unit : mm 10PIN TSSOP(PLASTIC) 1.2MAX ∗2.8 ± 0.1 0.1 10 6 + 0.15 0.1 – 0.05 0.45 ± 0.15 3.2 ± 0.2 ∗2.2 ± 0.1 5 1 0.5 + 0.08 0.22 – 0.07 0.1 0.25 0° to 10° M A (0.1) + 0.025 0.12 – 0.015 Package Outline (0.2) + 0.08 0.22 – 0.07 DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING EIAJ CODE LEAD MATERIAL COPPER ALLOY JEDEC CODE PACKAGE MASS 0.02g SONY CODE TSSOP-10P-L01 —4—