SONY CXP845F60Q-1

CXP845F60
CMOS 8-bit Single Chip Microcomputer
Description
The CXP845F60 is a CMOS 8-bit microcomputer
integrating on a single chip an A/D converter, serial
interface, timer/counter, time-base timer, capture
timer/counter, PWM output and the like besides the
basic configurations of 8-bit CPU, flash EEPROM,
RAM and I/O port.
The CXP845F60 also provides a sleep/stop functions
that enable to execute the power-on reset function or
lower the power consumption.
The CXP845F60 is the flash EEPROM-incorporated
version of the CXP84540/84548 with a built-in mask
ROM. This enables program writing and erasing.
Thus, it is most suitable for evaluation use during
system development and for small-quantity production.
80 pin QFP (Plastic)
Features
• A wide instruction set (213 instructions) which covers various types of data
— 16-bit arithmetic/multiplication and division/Boolean bit operation instructions
• Minimum instruction cycle
143ns at 28MHz operation (4.5 to 5.5V)
• Incorporated flash EEPROM 60K bytes
Rewrite time 100 times
• Incorporated RAM
1472 bytes
• Peripheral functions
— A/D converter
8 bits, 8 channels, successive approximation method
(Conversion time of 1.93µs at 28MHz)
— Serial interface
Incorporated 8-bit, 8-stage FIFO (Auto transfer for 1 to 8 bytes,
latch output function, MSB/LSB first selectable), 1 channel
8-bit clock sync type, 1 channel
— Timer
8-bit timer
8-bit timer/counter
19-bit time-base timer
16-bit capture time/counter
— PWM output
8 bits, 2 channels
• Interruption
14 factors, 14 vectors, multi-interruption possible
• Standby mode
Sleep/stop
• Package
80-pin plastic QFP
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96906-PS
8 BIT PWM GENERATOR 0
PWM1
8 BIT PWM GENERATOR 1
–2–
SI1
SO1
SCK1
EC0
SERIAL
INTERFACE
UNIT 0
EXTAL
XTAL
RST
VDD
Vss
Flash EEPROM
60K BYTES
CLOCK
GENERATOR/
SYSTEM CONTROL
RAM
1472 BYTES
FIFO
SERIAL INTERFACE UNIT 1
PRESCALER/
TIME-BASE TIMER
8 BIT TIMER/COUNTER 0
8 BIT TIMER 1
TO
CINT
EC1
SPC700
CPU CORE
2
16 BIT CAPTURE
TIMER/COUNTER 2
2
PORT I PORT H PORT G PORT F PORT E PORT D PORT C PORT B PORT A
PWM0
CS0
SI0
SO0
SCK0
LAT0
NMI
INT0
INT1
INT2
INT3
A/D CONVERTER
8
PA0 to PA7
8
PB0 to PB7
8
PC0 to PC7
8
PD0 to PD7
4
PE0 to PE3
4
PE4 to PE7
8
PF0 to PF7
8
PG0 to PG7
8
PH0 to PH7
8
PI0 to PI7
CXP845F60
PWE
TETA
TETB
TETC
8
INTERRUPT CONTROLLER
AN0 to AN7
AVREF
AVss
Block Diagram
CXP845F60
PI5
PI6
PG0
PI7
PG1
PG2
PG3
VDD
PWE
PG4
PG6
PG5
PG7
PF0
PF2
PF1
Pin Assignment 1 (Top View)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
PF3
1
64
PI4
PF4
2
63
PI3/INT3
PF5
3
62
PI2/INT2
PF6
4
61
PI1/INT1
PF7
5
60
PI0/INT0
PD0
6
59
PE5/TO/PWM1/(TETA)
PD1
7
58
PE4/PWM0/(TETB)
PD2
8
57
PE3/NMI/(TETC)
PD3
9
56
PE2/CINT
PD4
10
55
PE1/EC1
PD5
11
54
PE0/EC0
PD6
12
53
PB7/SO1
PD7
13
52
PB6/SI1
PC0
14
51
PB5/SCK1
PC1
15
50
PB4/SO0
PC2
16
49
PB3/SI0
PB2/SCK0
PC3
17
48
PC4
18
47
PB1/CS0
PC5
19
46
PB0/LAT0
PC6
20
45
PA7/AN7
PC7
21
44
PA6/AN6
PH0
22
43
PA5/AN5
PH1
23
42
PA4/AN4
PH2
24
41
PA3/AN3
PA1/AN1
PA2/AN2
PA0/AN0
AVREF
PE7
AVSS
PE6
VSS
XTAL
EXTAL
RST
PH6
PH7
PH5
PH4
PH3
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Notes) 1. PWE (Pin 73) is left open during normal operation.
2. See the Appendix concerning the Pins 57 to 59 (TETA, TETB and TETC).
–3–
CXP845F60
Pin Description
Symbol
I/O
PA0/AN0
to
PA7/AN7
I/O/Analog input
PB0/LAT0
I/O/Output
PB1/CS0
I/O/Input
PB2/SCK0
I/O/I/O
PB3/SI0
I/O/Input
PB4/SO0
I/O/Output
PB5/SCK1
I/O/I/O
PB6/SI1
I/O/Input
PB7/SO1
I/O/Output
Description
(Port A)
8-bit I/O port. I/O can be
set in a unit of single bits.
Incorporation of the
pull-up resistor can be set
through the software in a
unit of 4 bits.
(8 pins)
Analog inputs to A/D converter.
(8 pins)
Latch output for serial interface (CH0).
(Port B)
8-bit I/O port. I/O can be
set in a unit of single bits.
Incorporation of pull-up
resistor can be set
through the software in a
unit of 4 bits.
(8 pins)
Chip select input for serial interface (CH0).
Serial clock I/O (CH0).
Serial data input (CH0).
Serial data output (CH0).
Serial clock I/O (CH1).
Serial data input (CH1).
Serial data output (CH1).
I/O
(Port C)
8-bit I/O port. I/O can be set in a unit of single bits. Can drive 12mA sink
current. Incorporation of pull-up resistor can be set through the software
in a unit of 4 bits.
(8 pins)
PD0 to PD7
I/O
(Port D)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits.
(8 pins)
PE0/EC0
Input/Input
PE1/EC1
Input/Input
External event inputs for timer/counter.
(2 pins)
PE2/CINT
Input/Input
Capture trigger input.
PE3/NMI/
(TETC)
Input/Input/
(Input)
PE4/PWM0/
(TETB)
Output/Output/
(Input)
PC0 to PC7
(Port E)
8-bit port. Lower 4 bits
are for inputs; upper
4 bits are for outputs.
(8 pins)
Output
PE7
Output
PF0 to PF7
I/O
8-bit PWM0 output.
Rectangular wave output for 16-bit
timer/counter and 8-bit PWM1 output.
Output/Output/
PE5/TO/
PWM1/(TETA) Output/(Input)
PE6
Non-maskable interruption
request input.
Control pins
for flash
EEPROM
write.
(3 pins)
(Port F)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of
pull-up resistor can be set through the software in a unit of 4 bits.
(8 pins)
–4–
CXP845F60
Symbol
I/O
Description
I/O
(Port G)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits.
(8 pins)
PH0 to PH7
I/O
(Port H)
8-bit I/O port. I/O and standby release input function can be set in a unit
of single bits. Incorporation of pull-up resistor can be set through the
software in a unit of 4 bits.
(8 pins)
PI0/INT0
to
PI3/INT3
I/O/Input
PI4 to PI7
I/O
EXTAL
Input
XTAL
Output
RST
I/O
System reset for active at Low level. This pin is I/O pin, and outputs Low
level at the power on with the power-on reset function executed.
PWE
Input
Flash EEPROM write enable pin.
Write is enabled at Low level; write is prohibited at High level.
Leave this pin open for normally operation.
AVREF
Input
Reference voltage input for A/D converter.
PG0 to PG7
(Port I)
8-bit I/O port. I/O can be set in a unit of single
bits. Incorporation of pull-up resistor can be set
through the software in a unit of 4 bits.
(8 pins)
External interruption
request inputs.
(4 pins)
Connects a crystal for system clock oscillation. When the clock is supplied
externally, input to EXTAL; opposite phase clock should be input to XTAL.
AVss
A/D converter GND.
VDD
Positive power supply.
Vss
GND
–5–
CXP845F60
Input/Output Circuit Formats for Pins
AAA
AAA
AAA
AAA
AAA
AAA
AAA
Pin
Port A
When reset
Circuit format
∗
Pull-up resistor
"0" when reset
AA
AA
AA
Port A data
PA0/AN0
to
PA7/AN7
Port A direction
IP
"0" when reset
Data bus
Input protection
circuit
Hi-Z
RD (Port A)
Port A function
selection
Input multiplexer
"0" when reset
A/D converter
∗ Pull-up transistor
Approx. 100kΩ (VDD = 4.5 to 5.5V)
8 pins
Port B
AAA
AAA
AAA
AAA
AAA
AAA
∗
Pull-up resistor
"0" when reset
LAT0
Latch output enable
AA
AA
AA
Port B data
PB0/LAT0
IP
Port B direction
Hi-Z
"0" when reset
Data bus
RD (Port B)
∗ Pull-up transistor
Approx. 100kΩ (VDD = 4.5 to 5.5V)
1 pin
Port B
AAAA
AAAA
AAAA
AAAA
AAAA
∗
Pull-up resistor
"0" when reset
Port B data
PB1/CS0
PB3/SI0
PB6/SI1
Port B direction
AA
A
AA
A
IP
"0" when reset
Schmitt input
Data bus
RD (Port B)
3 pins
CS0
SI0
SI1
∗ Pull-up transistor
Approx. 100kΩ (VDD = 4.5 to 5.5V)
–6–
Hi-Z
CXP845F60
Pin
When reset
Circuit format
Port B
AAAA
AAAA
AAAA
AAAA
AAAA
∗
Pull-up resistor
"0" when reset
SCK OUT
Serial clock output enable
AA
AA
AA
Port B function
selection
"0" when reset
PB2/SCK0
PB5/SCK1
IP
Port B data
Hi-Z
Port B direction
"0" when reset
Data bus
Schmitt input
RD (Port B)
SCK0, SCK1 in
2 pins
Port B
AAA
AAA
AAA
AAA
AAA
AAA
AAA
∗ Pull-up transistor
Approx. 100kΩ (VDD = 4.5 to 5.5V)
∗
Pull-up resistor
SO
Serial data output enable
AA
AA
AA
Port B function
selection
PB4/SO0
PB7/SO1
"0" when reset
IP
Port B data
Hi-Z
Port B direction
"0" when reset
Data bus
RD (Port B)
∗ Pull-up transistor
Approx. 100kΩ (VDD = 4.5 to 5.5V)
2 pins
Port C
AAAA
AAAA
AAAA
AAAA
AAAA
∗2
Pull-up resistor
"0" when reset
Port C data
PC0 to PC7
*1
Port C direction
"0" when reset
Data bus
RD (Port C)
AA
A
AA
A
IP
∗1 Large current drive
12mA (VDD = 4.5 to 5.5V)
∗2 Pull-up transistor
Approx. 100kΩ (VDD = 4.5 to 5.5V)
8 pins
–7–
Hi-Z
CXP845F60
Pin
When reset
Circuit format
Port E
PE0/EC0
PE1/EC1
PE2/CINT
PE3/NMI/
(TETC)
4 pins
AA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
Schmitt input
Port E
PE4/PWM0/
(TETB)
EC0, EC1
CINT, NMI (to flash EEPROM circuit)
IP
RD (Port E)
AA
AA
PWM0
Port E function
selection
"0" when reset
Port E data
"1" when reset
1 pin
Hi-Z
Data bus
High level
Data bus
RD (Port E)
(to flash EEPROM circuit)
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAA
AAAA
AAAAA
AAAAA
Port E
Internal reset signal
Port E data
PE5/TO/
PWM1/
(TETA)
00
"1" when reset
TO
PWM1
∗
MPX
01
1x
Port E function selection
(upper)
Port E function selection
(lower)
(to flash EEPROM circuit)
"00" when reset
1 pin
TO output enable
Port E
PE6, PE7
AAAA
AAAA
∗ Pull-up transistor
Approx. 150kΩ (VDD = 4.5 to 5.5V)
AA
AA
Port E data
"0" when reset
Data bus
2 pins
AA
AA
RD (Port E)
–8–
High level
High level
at ON
resistance
of pull-up
transistor
during
a reset.
Low level
CXP845F60
Pin
Port D
Port F
Port G
PD0 to PD7
PF0 to PF7
PG0 to PG7
PI4 to PI7
When reset
Circuit format
Port I
AAAA
AAAAAA
AAAA
AAAAAA
AAAAAA
AAAAAA
∗
Pull-up resistor
A
A
AA
AA
"0" when reset
Ports D, F, G, I data
Ports D, F, G, I direction
IP
"0" when reset
Data bus
RD
Hi-Z
∗ Pull-up transistor
Approx. 100kΩ (VDD = 4.5 to 5.5V)
28 pins
Port H
AAAA
AAAA
AAAA
AAAA
AAAA
A
A
AAAA
AAAA
AAAA
AAAA
AAAA
∗
Pull-up resistor
AA
A
AA
A
"0" when reset
Port H data
PH0 to PH7
Port H direction
IP
"0" when reset
Data bus
RD (Port H)
Edge detection
Standby release
8 pins
Port I
∗ Pull-up transistor
Approx. 100kΩ (VDD = 4.5 to 5.5V)
∗
Pull-up resistor
"0" when reset
Port I data
PI0/INT0
to
PI3/INT3
Port I direction
"0" when reset
Data bus
A
AA
A
AA
IP
Schmitt input
RD
INT0
INT1
INT2
INT3
∗ Pull-up transistor
Approx. 100kΩ (VDD = 4.5 to 5.5V)
4 pins
–9–
Hi-Z
Hi-Z
CXP845F60
Pin
EXTAL
XTAL
2 pins
RST
When reset
Circuit format
AA
AA
AA
AA
AA AA
AA
AA
AA
EXTAL
IP
IP
• Diagram shows the circuit
composition during oscillation.
• Feedback resistor is removed
during stop mode and XTAL
becomes High level.
Oscillation
XTAL
Pull-up resistor
Schmitt input
Low level
IP
from power-on reset circuit
1 pin
Pull-up resistor
PWE
AAAA
High level
to flash EEPROM circuit
IP
1 pin
– 10 –
CXP845F60
Absolute Maximum Ratings
(Vss = 0V reference)
Item
Symbol
Supply voltage
Ratings
Unit
VDD
–0.3 to +7.0
V
AVSS
V
Remarks
Input voltage
VIN
–0.3 to +0.3
–0.3 to +7.0∗1
Output voltage
VOUT
–0.3 to +7.0∗1
V
High level output current
IOH
–5
mA
Output (value per pin)
High level total output current
∑IOH
–50
mA
Total for all output pins
IOL
15
mA
IOLC
20
mA
All pins excluding large current outputs
(value per pin)
Large current outputs (value per pin∗2)
Low level total output current
∑IOL
100
mA
Total for all output pins
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
Allowable power dissipation
PD
600
mW
Low level output current
V
∗1 VIN and VOUT must not exceed VDD + 0.3V.
∗2 The large current drive transistor is the N-ch transistor of Port C (PC).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding these conditions may adversely
affect the reliability of the LSI.
Recommended Operating Conditions
Item
Supply voltage
High level input
voltage
Symbol
Min.
Max.
4.5
5.5
3.5
5.5
2.0
5.5
VIH
0.7VDD
VDD
V
VIHS
0.8VDD
VDD
V
VDD
VIHEX
Low level input
voltage
Operating temperature
(Vss = 0V reference)
Unit
Remarks
Guaranteed operation range for 1/2 and 1/4
frequency dividing modes
V
VDD – 0.4 VDD + 0.3
Guaranteed operation range for 1/16 frequency
dividing and sleep modes
Guaranteed data hold range during stop mode
∗1
V
Hysteresis input∗2
EXTAL∗3
∗1
VIL
0
0.3VDD
V
VILS
0
0.2VDD
V
VILEX
–0.3
+0.4
V
Topr
–20
+75
°C
Hysteresis input∗2
EXTAL∗3
∗1 Normal input ports (PA, PB0, PB4, PB7, PC, PE0 to PE3, PD, PF to PH, PI4 to PI7)
∗2 RST, CINT, CS0, SCK0, SCK1, EC0, EC1, SI0, SI1, NMI, INT0, INT1, INT2, INT3
∗3 Specifies only during external clock input.
– 11 –
CXP845F60
Electrical Characteristics
DC Characteristics (VDD = 4.5 to 5.5V)
Item
High level
output voltage
Low level
output voltage
Symbol
VOH
Pin
PA to PD,
PE4 to PE7,
PF to PI,
RST (only VOL)
VOL
PC
IIHE
EXTAL
IILE
Input current
I/O leakage
current
IILR
RST
IIL
PA to PD∗1
PF to PI∗1
IIZ
PA to PD∗1
PF to PI∗1
PE0 to PE3
Conditions
Min.
Typ. Max.
Unit
VDD = 4.5V, IOH = –0.5mA
4.0
V
VDD = 4.5V, IOH = –1.2mA
3.5
V
VDD = 4.5V, IOL = 1.8mA
0.4
V
VDD = 4.5V, IOL = 3.6mA
0.6
V
VDD = 4.5V, IOL = 12.0mA
1.5
V
VDD = 5.5V, VIH = 5.5V
0.1
25
µA
VDD = 5.5V, VIL = 0.4V
–0.1
–25
µA
–1.5
–400
µA
–50
µA
VDD = 5.5V, VIL = 4.0V
VDD = 4.5V, VIL = 4.0V
–2.78
µA
VDD = 5.5V,
VI = 0, 5.5V
±10
µA
38
66
mA
2.5
10
mA
30
µA
20
pF
For 1/2 frequency dividing mode
IDD1
VDD = 5.5V, 28MHz crystal oscillation
(C1 = C2 = 1pF)
IDD2
Supply
current ∗2
(Ta = –20 to +75°C, Vss = 0V reference)
Sleep mode
IDDS1
VDD
IDDS2
VDD = 5.5V, 28MHz crystal oscillation
(C1 = C2 = 1pF)
Stop mode
IDDS3
Input
capacity
CIN
VDD = 5.5V, termination of 28MHz
crystal oscillation
PA to PD,
PE0 to PE3,
PF to PI,
EXTAL,
RST
Clock 1MHz
0V for all pins excluding measured
pins
10
∗1 For PA to PD and PF to PI pins, specifies the input current when pull-up resistance is selected; leakage
current when no resistance is selected.
∗2 When all output pins are left open.
– 12 –
CXP845F60
AC Characteristics
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
(1) Clock timing
Item
Symbol
fC
System clock input pulse width
tXL,
tXH
tCR,
tCF
tEH,
tEL
tER,
tEF
Event count input clock
pulse width
Event count input clock
rise time, fall time
Conditions
Min.
XTAL
Fig. 1, Fig. 2
EXTAL
System clock frequency
System clock input
rise time, fall time
Pin
Typ. Max. Unit
1
EXTAL
Fig. 1, Fig. 2
External clock drive
EXTAL
Fig. 1, Fig. 2
External clock drive
EC0
EC1
Fig. 3
EC0
EC1
Fig. 3
28 MHz
15.6
ns
100
tsys + 50∗1
ns
ns
20
ms
∗1 tsys indicates the three values according to the contents of the clock control register (CLC: 00FEh) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
1/fc
VDD – 0.4V
EXTAL
0.4V
tXH
tCF
tXL
tCR
Fig. 1. Clock timing
AAAAA
AAAA
AAAAAAAAA
AAAAAAAAA
Crystal oscillation
Ceramic oscillation
EXTAL
External clock
EXTAL
XTAL
C1
C2
XTAL
74HC04
Fig. 2. Clock applied conditions
0.8VDD
EC0
EC1
0.2VDD
tEH
tTH
tEF
tTF
tEL
tTL
Fig. 3. Event count clock timing
– 13 –
tER
tTR
CXP845F60
(2) Serial transfer (CH0)
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Pin
Conditions
Min.
Max.
Unit
CS0 ↓ → SCK0
delay time
tDCSK
SCK0
Chip select transfer mode
(SCK0 = output mode)
1.5tsys + 100
ns
CS0 ↑ → SCK0
float delay time
tDCSKF SCK0
Chip select transfer mode
(SCK0 = output mode)
1.5tsys + 100
ns
CS0 ↓ → SO0
delay time
tDCSO SO0
Chip select transfer mode
1.5tsys + 100
ns
CS0 ↑ → SO0
float delay time
tDCSOF SO0
Chip select transfer mode
1.5tsys + 100
ns
CS0 High level width
tWHCS CS0
Chip select transfer mode
SCK0 cycle time
tKCY
SCK0
SCK0
High, Low level width
tKH
tKL
SCK0
SI0 input setup time
(for SCK0 ↑)
tSIK
SI0
SI0 input hold time
(for SCK0 ↑)
tKSI
SI0
SCK0 ↓ → SO0
delay time
tKSO
SO0
SCK0 ↑ → LAT0
output delay time
tLADLY LAT0
Latch output mode
(SCK0 = output mode)
LAT0 data pulse width
tLAPLS LAT0
Latch output mode
(SCK0 = output mode)
tsys + 150
2tsys + 200
ns
8000/fc
ns
tsys + 90
ns
4000/fc – 25
ns
SCK0 input mode
50
ns
SCK0 output mode
100
ns
tsys + 100
ns
50
ns
Input mode
Output mode
Input mode
Output mode
SCK0 input mode
SCK0 output mode
ns
tsys + 100
ns
50
ns
tKCY
tKCY + 50
ns
tKCY – 10
tKCY + 50
ns
SCK0 input mode
SCK0 output mode
Note 1) tsys indicates the three values according to the contents of the clock control register (CLC: 00FEh)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.
– 14 –
CXP845F60
tWHCS
0.8VDD
CS0
0.2VDD
tKCY
tDCSK
tKL
tDCSKF
tKH
0.8VDD
0.8VDD
0.8VDD
SCK0
0.2VDD
tSIK
tKSI
0.8VDD
Input
data
SI0
0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD
SO0
Output
data
0.2VDD
tLADLY
0.8VDD
LAT0
Fig. 4. Serial transfer CH0 timing
– 15 –
tLAPLS
0.8VDD
CXP845F60
(3) Serial transfer (CH1)
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V reference)
Symbol
Pin
Conditions
tKCY
SCK1
SCK1 High, Low level
width
tKH
tKL
SCK1
SI1 input setup time
(for SCK1 ↑)
tSIK
SI1
SI1 input hold time
(for SCK1 ↑)
tKSI
SI1
SCK1 ↓ → SO1 delay time
tKSO
SO1
SCK1 cycle time
Min.
Max.
500
ns
8000/fc
ns
200
ns
4000/fc – 25
ns
SCK1 input mode
50
ns
SCK1 output mode
100
ns
SCK1 input mode
100
ns
SCK1 output mode
50
ns
Input mode
Output mode
Input mode
Output mode
SCK1 input mode
100
ns
SCK1 output mode
50
ns
Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.
tKCY
tKL
tKH
0.8VDD
SCK1
0.2VDD
tSIK
tKSI
0.8VDD
Input data
SI1
Unit
0.2VDD
tKSO
0.8VDD
SO1
Output data
0.2VDD
Fig. 5. Serial transfer CH1 timing
– 16 –
CXP845F60
(4) A/D converter characteristics (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to VDD, Vss = AVSS = 0V reference)
Item
Symbol
Pin
Conditions
Min.
Typ.
Resolution
Linearity error
Zero transition voltage
VZT∗1
Full-scale transition
voltage
VFT∗2
Conversion time
tCONV
tSAMP
Sampling time
Ta = 25°C
VDD = AVREF = 5.0V
VSS = AVSS = 0V
AVREF
Analog input voltage
AN0 to AN7
VIAN
8
Bits
±4
LSB
–10
10
70
mV
4910
4970
5030
mV
AVREF current
AVREF
IREFS
µs
µs
VDD – 0.5
VDD
V
0
AVREF
V
1.0
mA
10
µA
Operation mode
IREF
Sleep mode
Stop mode
0.6
∗1 VZT: Value at which the digital conversion value changes
from 00H to 01H and vice versa.
∗2 VFT: Value at which the digital conversion value changes
from FEH to FFH and vice versa.
∗3 fADC indicates the values below due to the contents of bit 6
(CKS) of the A/D control register (ADC: 00F9H).
fADC = fc (CKS = "0"), fc/2 (CKS = "1")
However, the selection for fADC = fc (CKS = "0") is limited in
the clock range of fc = 1 to 14MHz (VDD = 4.5 to 5.5V).
FFh
FEh
Digital conversion value
Unit
27/fADC∗3
6/fADC∗3
Reference input voltage VREF
Linearity error
01h
00h
VFT
VZT
Max.
Analog input
Fig. 6. Definition of A/D converter terms
– 17 –
CXP845F60
(5) Interruption, reset input
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Pin
External interruption
High, Low level width
tIH
tIL
INT0
INT1
INT2
INT3
NMI
Reset input Low level width
tRSL
RST
Conditions
Min.
Max.
Unit
1
µs
32/fc
µs
tIH
tIL
0.8VDD
INT0
INT1
INT2
INT3
NMI
(Specifies NMI only for
the falling edge.)
0.2VDD
tIL
tIH
0.8VDD
0.2VDD
Fig 7. Interruption input timing
tRSL
RST
0.2VDD
Fig. 8. RST input timing
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V reference)
(6) Power-on reset
Item
Symbol
tR
tOFF
Power supply rise time
Power supply cut-off time
Pin
VDD
Conditions
Power-on reset
4.5V
VDD
0.2V
tR
tOFF
Turn the power on smoothly.
Fig. 9. Power-on reset
– 18 –
Max.
Unit
0.05
50
ms
1
Repetitive power-on reset
0.2V
Min.
ms
CXP845F60
Appendix
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
(i) Main clock
EXTAL
(ii) Main clock
EXTAL
XTAL
Rd
Rd
C1
XTAL
C2
C1 C2
Fig. 10. SPC700 Series recommended oscillation circuit
Manufacturer
MURATA
MFG
CO., LTD.
Model
fc (MHz)
CSA8.00MTZ
8.00
CSA10.0MTZ
10.00
CSA12.00MTZ
CST8.00MTW∗1
12.00
CST10.0MT∗1
10.00
CST12.0MTW∗1
12.00
C2 (pF)
Rd (Ω)
Circuit
example
(i)
30
8.00
30
0
(ii)
CSA16.00MXZ040
CST16.00MXZ0C1∗1
16.00
5
5
0
(i)
16.00
5
5
0
(ii)
CSA20.00MXZ040
20.00
OPEN
OPEN
0
CSA24.00MXZ040
24.00
3
3
0
CSA28.00MXZ040
CCR20.0MC6∗1
28.00
3
3
0
20.00
16
16
0
24.00
16
16
0
HC49/U-S
28.00
1
1
220
CX-11F
28.00
1
1
220
TDK
CORPORATION. CCR24.0MC6∗1
KINSEKI LTD.
C1 (pF)
∗1 Models with the built-in ground capacitance (C1, C2).
Selection Guide
Option item
Package
ROM capacitance
Mask
CXP845F60Q-1-
100-pin plastic QFP
40K bytes
48K bytes
100-pin plastic QFP
Flash EEPROM 60K bytes
Reset pin pull-up resistor
Existent/Non-existent
Existent
Power-on reset circuit
Existent/Non-existent
Existent
– 19 –
(i)
(ii)
(i)
CXP845F60
Characteristics Curves
IDD vs. fc
IDD vs. VDD
(fc = 28MHz, Ta = 25˚C, Typical)
(VDD = 5V, Ta = 25˚C, Typical)
50
1/2 dividing mode
40
30
20
1/4 dividing mode
1/16 dividing mode
40
10
1/2 dividing mode
IDD – Supply current [mA]
IDD – Supply current [mA]
Sleep mode
1
0.5
(500µA)
0.1
(100µA)
30
1/4 dividing mode
20
1/16 dividing mode
10
0.01
(10µA)
Stop mode
Sleep mode
0
1
2
3
4
5
6
7
VDD – Supply voltage [v]
8
9
– 20 –
0
10
20
fc – System clock [MHz]
30
CXP845F60
Writing to Flash EEPROM
The CXP845F60 contains the 60K bytes of flash EEPROM. There are two methods to write to the flash
EEPROM; off-board write and on-board write.
The on-board write supports boot mode and user programming mode. Rewriting at the room temperature is
recommended.
1. Off-board write
In order to execute the off-board write, the microcomputer is attached on a conversion adaptor and the adaptor
is inserted in the socket of the SFP-1 (flash memory programmer) or NICE-SPC700R. (See Fig. 11.)
See the operation manuals for the operation methods of the SFP-1 and NICE-SPC700R. (Mitec SYSTEMS,
Inc. manufactures and sells the SFP-1 and NICE-SPC700R.)
Conversion adaptor
Flash memory programmer SFP-1
Fig. 11. Off-board write (when writing by using SFP-1)
2. On-board write
This is performed with the microcomputer mounted on the board. The CXP845F60 supports boot mode and
user programming mode.
In boot mode, write is performed through the communication with the SFP-1 as shown in Fig. 12.
User board
SIO communication cable (8 pins)
CXP845F60
Flash memory programmer SFP-1
Fig. 12. On-board write boot mode
In user programming mode, write is performed in microcomputer mode (normal operation mode) by the
communication method (SIO, I/O, etc.) according to the user's application. See the guide of the CXP845F60
write for actual use.
– 21 –
CXP845F60
When the on-board write is performed, the pins and flash mode register (FMOD: 01F4h, 0FF0h) should be set
as follows.
Pins
FMOD resister
Mode
RST
TETA
Boot mode
Onboard
write
Low fixed
TETB
TETC
PWE
FLMOD bit
1∗1
High output High fixed
Low fixed
User programming
mode
High level
X
X
X
1
∗1 FLMOD bit is set to "1" automatically in boot mode.
X: don't care
User circuit
Cut off the connection to other circuits
during the flash EEPROM rewrite.
When normal
operation
GND
SI
SO
SCK
RES
VIN
GND
Vpp
VSS
SO1
SI1
SCK1
RST
VDD
VSS
SEL
SO1
SI1
SCK1
Switching circuit
VDD
In boot mode
Flash MCU
Switched to boot
mode for low level
PWE
RST
∗1
AMP CT receptacle AMP CT connector
173977-8
175489-8
TETC
TETB
TETA
When normal
operation
Switching circuit
In boot mode
Reset
circuit
VSS
Switched to boot
mode for low level
∗1 The Vpp signal for the SFP-1 is pulled down with 4.7kΩ. Connecting cable permits writing when PWE pin is
fixed at low level. Also, it can be used as select signal of the switching circuit.
Fig. 13. Connection example for boot mode
Pin
No.
Connector for SFP-1
(AMP CT receptacle 173977-8)
Symbol
Remarks
Signal
direction
Connector for user board
(AMP CT connector 175489-8)
Symbol
1
GND
2
SI
4.7kΩ pull-up
←
SO1
3
SO
Open drain, 4.7kΩ pull-up
→
SI1
4
SCK
Open drain, 4.7kΩ pull-up
←
→
SCK1
5
RST
Open drain, 4.7kΩ pull-up
→
RST
6
VIN
←
VDD
7
GND
8
Vpp
Remarks
GND
Pull-up in the microcomputer (mask option)
GND
4.7kΩ pull-up
→
PWE
– 22 –
Pull-up in the microcomputer
CXP845F60
Package Outline
Unit: mm
80PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
20.0 – 0.1
64
0.15
41
65
16.3
17.9 ± 0.4
+ 0.4
14.0 – 0.1
40
A
+ 0.2
0.1 – 0.05
25
1
24
0.8
0.12
M
+ 0.15
0.35 – 0.1
+ 0.35
2.75 – 0.15
0° to 10°
DETAIL A
PACKAGE STRUCTURE
SONY CODE
QFP-80P-L01
EIAJ CODE
∗QFP080-P-1420-A
JEDEC CODE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
1.6g
– 23 –
0.8 ± 0.2
80