CXP913P048 CMOS 16-bit Single Chip Microcomputer For the availability of this product, please contact the sales office. Description The CXP913P048 is a CMOS 16-bit microcomputer integrating on a single chip an A/D converter, serial interface with an incorporated buffer RAM, highprecision timing pattern generation function, pulse cycle measurement circuit, PWM generator, generalpurpose prescaler, vertical sync separation circuit, and a measurement circuit which measures the signals of capstan FG, drum FG/PG, reel FG and other servo systems with high precision, as well as basic configurations like a 16-bit CPU, ROM, RAM, and I/O port. This LSI also provides sleep/stop modes that enable lower power consumption. The CXP913P048 is the PROM-incorporated version of the CXP913040 with built-in mask ROM. This provides the additional feature of being able to write directly into the program. Thus, it is most suitable for evaluation use during system development and for small-quantity production. 100 pin LQFP (Plastic) Structure Silicon gate CMOS IC Features • An efficient instruction set as a controller — Direct addressing, numerous abbreviated forms, multiplication and division instructions • Instruction sets for C language and RTOS — Highly quadratic instruction system, general-purpose register of 16-bit × 8-pin × 16-bank configuration • Minimum instruction cycle 100ns at 20MHz operation • Incorporated ROM capacity 192K bytes • Incorporated RAM capacity 6144 bytes • Peripheral functions — A/D converter 8-bit 12-channel successive approximation system, automatic scanning function, 8-stage (soft) + 4-stage (hard) FIFO for conversion results (Conversion time: 20µs at 20MHz) — Serial interface Buffer RAM (128 bytes, supports high-speed transfer mode), 3 channels — Timers 8-bit timer/counter + 8-bit timer (with timing output), 1 channel 16-bit capture timer/counter (with timing output), 1 channel 16-bit timer, 4 channels — High-precision timing pattern generator PPG for 27 pins, 42 stages (max.) PPG for 16 pins, 16 stages (max.) RTG for 5 pins, 3 channels — PWM/DA gate output PWM for 14 bits, 2 channels (Repetitive frequency of 39.1kHz/20MHz) DA gate pulse for 14 bits, 2 channels — Servo input control Capstan FG, drum FG/PG, reel FG — VSYNC separator — FRC capture unit 24-bit and 8-stage FIFO — PWM output 14 bits, 2 channels — General-purpose prescaler 10 bits, 1 channel — Pulse cycle measurement circuit 1 channel with mask input • General-purpose I/O 80 pins (max.; when all multi-purpose pins are used as general-purpose I/O.) • Interruption 28 factors, 28 vectors, multi-interruption and priority selection possible • Standby mode Sleep/stop • Package 100-pin plastic LQFP • Piggy/evaluation chip CXP913000 100-pin ceramic LQFP Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96X04-PS 14-BIT PWM/DA GENERATOR (× 2ch) 14-BIT PWM GENERATOR (× 2ch) PULSE MEASURE UNIT PWM2 PWM3 PMI PMSK PROGRAMMABLE PRESCALER SERVO INPUT CONTROL PWM0 PWM1 DA0 DA1 PO PCK/OSCI (OSCO) XOUT 2 REEL CAPSTAN DRUM V SYNC SEPARATOR SYNC0 SYNC1 DFG DPG CFG RFG0 RFG1 EXI0 EXI1 16-BIT CAPTURE TIMER/COUNTER 8-BIT TIMER 1 8-BIT TIMER/COUNTER 0 RAM SERIAL INTERFACE UNIT (CH2) EC2 CINT T2 T1 EC0 RAM SERIAL INTERFACE UNIT (CH1) 4 2 2 3 FIFO CH0 CH1 CH2 REALTIME PULSE GENERATOR 3 PRESCALER 12 A/D CONVERTER FIFO 16-BIT TIMER (× 4ch) 5 PROGRAMMABLE PATTERN (CH1) RAM GENERATOR FIFO 4 10 4 4 PROGRAMMABLE (CH0) RAM PATTERN GENERATOR FRC CAPTURE UNIT RAM 6144 BYTES CLOCK GENERATOR/ SYSTEM CONTROLLER 19 2 2 PROM 192K BYTES SPC900 CPU CORE A PPO000 to PPO018 CS1 SI1 SO1 SCK1 CS2 SI2 SO2 SCK2 INT2 INT1 INT0 NMI INTERRUPT CONTROLLER PPO100 to PPO109 RAM EXTAL XTAL RTO0 to RTO4 SERIAL INTERFACE UNIT (CH0) RST VDD Vss Vpp AVSS AVREF AVDD CS0 SI0 SO0 SCK0 AN0 to AN11 PORT A 8 8 4 4 8 2 6 4 4 8 8 8 8 PORT B PORT C PORT D PORT E PORT F PORT G PORT H PORT I –2– PORT J Block Diagram CXP913P048 CXP913P048 AVDD AVREF PJ0/AN4/KS8 PJ1/AN5/KS9 PJ2/AN6/KS10 PJ3/AN7/KS11 PJ4/AN8/KS12 PJ5/AN9/KS13 PJ6/AN10/KS14 PJ7/AN11/KS15 VDD/Vpp VSS VDD PA0/PPO000/PPO100 PA1/PPO001/PPO101 PA2/PPO002/PPO102 PA3/PPO003/PPO103 PA4/PPO004/PPO104 PA5/PPO005/PPO105 PA6/PPO006/PPO106 PA7/PPO007/PPO107 PB0/PPO008/PPO108 PB1/PPO009/PPO109 PB2/PPO010 PB3/PPO011 Pin Configuration (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PB4/PPO012 1 75 AVSS PB5/PPO013 2 74 AN3 PB6/PPO014 3 73 AN2 PB7/PPO015 4 72 AN1 PC0/PPO016 5 71 PI7/AN0 PC1/PPO017 6 70 VSS PC2/PPO018 7 69 PI6/XOUT PC3/RTO0 8 68 PI5/OSCO PC4/RTO1 9 67 PI4/PCK/OSCI PC5/RTO2 10 66 PI3/CS2/PO PC6/RTO3 11 65 PI2/SCK2 PC7/RTO4 12 64 PI1/SO2 VSS 13 63 PI0/SI2 PD0/KS0 14 62 SCK0 PD1/KS1 15 61 SO0 PD2/KS2 16 60 SI0 PD3/KS3 17 59 CS0 PD4/KS4 18 58 PH7/CFG PD5/KS5 19 57 PH6/DFG PD6/KS6 20 56 PH5/DPG PD7/KS7 21 55 PH4/PMSK PE0 22 54 PH3/SYNC1 PE1 23 53 PH2/SYNC0/PMI PE2 24 52 PH1/EXI1 PE3 25 51 PH0/EXI0 PG7/RFG1 PG6/RFG0 PG5/DA1 PG4/DA0 PG3/PWM3 PG2/PWM2 PG1/PWM1 PG0/PWM0 VDD EXTAL XTAL VSS RST PF7/T2 PF6/T1 PF5/SCK1 PF4/SO1 PF3/SI1/INT2 PF1/EC2/INT1 PF2/CS1/NMI/CINT PF0/EC0/INT0 PE7 PE6 PE5 PE4 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note) 1. Vss (Pins 13, 39, 70 and 88) must be connected to GND. 2. VDD (Pins 42 and 87) and VDD/VPP (Pin 86) must be connected to VDD. –3– CXP913P048 Pin Description Symbol I/O PA0/PPO000 /PPO100 to PA7/PPO007 /PPO107 Output / Real time output / Real time output PB0/PPO008 /PPO108 PB1/PPO009 /PPO109 Output / Real time output / Real time output PB2/PPO010 to PB7/PPO015 Output / Real time output PC0/PPO016 to PC2/PPO018 Output / Real time output PC3/RTO0 to PC7/RTO4 Output / Real time output Functions (Port A) 8-bit output port. Data is gated with PPO0 and PPO1 contents by OR-gate and they are output. (8 pins) (Port B) 8-bit output port. Data is gated with PPO0 and PPO1 contents by ORgate and they are output. (8 pins) (Port C) 8-bit I/O port. I/O can be specified by bit unit. Data is gated with PPO0 or RTO contents by ORgate and they are output. (8 pins) Programmable pattern generator (PPG0, PPG1) output. Functions as high-precision real-time pulse output port. (PPG0 19 pins, PPG1 10 pins) Real-time pulse generator (RTG) output. Functions as high-precision real-time pulse output port. (5 pins) I/O (Port D) 8-bit I/O port. I/O can be specified by bit unit. Standby release input function can also be specified by bit unit. Can drive 12mA sink current when VDD = 5V. (8 pins) PE0 to PE7 I/O (Port E) 8-bit I/O port. I/O can be specified by bit unit. Can drive 12mA sink current when VDD = 5V. (8 pins) PF0/EC0/ INT0 Input / Input / Input PF1/EC2/ INT1 Input / Input / Input PF2/CS1/ NMI/CINT Input / Input / Input / Input PF3/SI1/INT2 Input / Input / Input PF4/SO1 Output / Output Serial data (CH1) output. PF5/SCK1 Output / I/O Serial data (CH1) I/O. PF6/T1 Output / Output 8-bit timer/counter output. PF7/T2 Output / Output 16-bit capture timer/counter output. PD0 to PD7 External event input for timer/counter. (2 pins) (Port F) 8-bit port. Lower 4 bits are for input; upper 4 bits are for output. (8 pins) Serial chip select (CH1) input. Input to request non-maskable interruption. Active at the falling edge. Serial data (CH1) input. –4– Input to request external interruption. Active at the falling edge. (2 pins) External capture input for 16-bit timer/counter. Input to request external interruption. Active at the falling edge. CXP913P048 Symbol I/O Functions PG0/PWM0 Output / Output PG1/PWM1 Output / Output PG2/PWM2 Output / Output PG3/PWM3 Output / Output PG4/DA0 Output / Output PG5/DA1 Output / Output PG6/RFG0 Input / Input PG7/RFG1 Input / Input PH0/EXI0 Input / Input PH1/EXI1 Input / Input PH2/ SYNC0/PMI Input / Input / Input PH3/SYNC1 Input / Input PH4/PMSK Input / Input PH5/DPG Input / Input Drum PG input. PH6/DFG Input / Input Drum FG input. PH7/CFG Input / Input Capstan FG input. SCK0 I/O Serial clock (CH0) I/O. SO0 Output Serial data (CH0) output. SI0 Input Serial data (CH0) input. CS0 Input Serial chip select (CH0) input. PI0/SI2 I/O / Input Serial data (CH2) input. PI1/SO2 I/O / Output (Port I) 8-bit port. I/O / I/O Lower 4 bits I/O / Input / Output are for I/O; upper 4 bits Input / Input / are for input. Input Lower 4 bits can be Input / Output specified by bit unit. Input / Output (8 pins) Serial data (CH2) output. PI2/SCK2 PI3/CS2/PO PI4/PCK/ OSCI PI5/OSCO PI6/XOUT PI7/AN0 Input / Input AN1 to AN3 Input PJ0/AN4 to PJ7/AN11 I/O / Input (Port G) 8-bit port. Lower 6 bits are for output; upper 2 bits are for input. (8 pins) 14-bit PWM output. (4 pins) DA gate pulse output. (2 pins) Reel FG input. (2 pins) External input for FRC capture unit. (2 pins) (Port H) 8-bit input port. (8 pins) Composite sync signal input. (2 pins) Pulse input for pulse cycle measurement circuit. Mask input for pulse cycle measurement circuit. Serial clock (CH2) I/O. Serial chip select (CH2) input. General-purpose prescaler output. General-purpose Connects a crystal for generalprescaler external clock input. purpose prescaler clock oscillation. (Mask option) Clock output from clock generator or general-purpose prescaler. (Port J) 8-bit I/O port. I/O can be specified by bit unit. Standby release input function can also be specified by bit unit. (8 pins) –5– Analog input for A/D converter. (12 pins) CXP913P048 Symbol I/O Functions EXTAL Input XTAL Output Connects a crystal for system clock oscillation. When the clock is supplied externally, input it to EXTAL and input an opposite phase clock to XTAL. RST I/O System reset. Active at "L" level. Positive power supply for A/D converter. AVDD AVREF Input Reference voltage input for A/D converter. AVSS A/D converter GND. VDD Positive power supply. All three VDD pins must be connected to the positive power supply. VSS GND. All four VSS pins must be connected to GND. VPP Positive power supply for incorporated PROM writing. Connect to VDD for normal operation. –6– CXP913P048 I/O Circuit Format for Pins Pin PA0/PPO000/ PPO100 to PA7/PPO007/ PPO107 When reset Circuit format Port A AA AA Port B AAAA AAAA PPO0 data PPO1 data PB0/PPO008/ PPO108 to PB1/PPO009/ PPO109 Port A or Port B data Data bus 10 pins Hi-Z Output becomes active from Hi-Z by writing data to port register. RD AA AA Port B AAAA AAAA PPO0 data PB2/PPO010 to PB7/PPO015 Hi-Z Port B data Data bus 6 pins Output becomes active from Hi-Z by writing data to port register. RD Port C PC0/PPO016 to PC2/PPO018 AAAA AAAA AAAA PPO0 or RTO data Port C data PC3/RTO0 to PC7/RTO4 "0" when reset Data bus A A A A Input protection circuit Hi-Z IP Port C direction (Every bit) 8 pins RD (Port C) A A Port D AAAA AAAA AAAA AA AAAAA AA AAAAA Port D data PD0/KS0 to PD7/KS7 "0" when reset ∗ Port D direction Data bus A A IP (Every bit) RD Standby release 8 pins Port D standby release data Edge detection –7– ∗ Large current drive transistor Hi-Z CXP913P048 Pin When reset Circuit format Port E AAA AAA AAA Port E data PE0 to PE7 "0" when reset AA AA A A ∗ Port E direction Hi-Z IP (Every bit) Data bus RD 8 pins ∗ Large current drive transistor AA A AAA Port F PF0/EC0/INT0 PF1/EC2/INT1 PF3/SI1/INT2 Schmitt trigger input Interrupt circuit and timer/counter or SIO IP Hi-Z Data bus RD (Port F) 3 pins Port F AAAAA AAAAA AAA "0" when reset PF2/CS1/ NMI/CINT Port F function selection Interrupt circuit Schmitt trigger input Timer/counter or SIO Hi-Z Data bus IP RD (Port F) 1 pin Port F AAA AAA AA AAA AA AAAA AA AAAAAA "0" when reset PF4/SO1 AA AA Port F function selection SO1 from SIO MPX Port F data Data bus 1 pin RD (Port F) –8– Hi-Z control Hi-Z CXP913P048 Pin AAAA AAAAAA AA AAAAAA AA When reset Circuit format Port F "0" when reset Port F function selection Internal serial clock from SIO PF5/SCK1 MPX Port F data Data bus Hi-Z control RD (Port F) AA AA AA AA IP AAAA AAAA AA AAAA AA AA AAAA AA AA AAAAAA 1 pin SIO Schmitt trigger input Port F Port F function selection "0" when reset PF6/T1 PF7/T2 Hi-Z Timer/counter MPX "1" when reset "H" level Port F data Data bus 2 pins RD (Port F) Port G PG0/PWM0 PG1/PWM1 PG2/PWM2 PG3/PWM3 PG4/DA0 PG5/DA1 AAAA AAAA AA AAAA AA AAAAAA "0" when reset Port G function selection AA DA gate output or PWM output MPX Port G data Data bus 6 pins Hi-Z Hi-Z control RD (Port G) AA AA AAAA AA AA AAAA Port G PG6/RFG0 PG7/RFG1 2 pins PH0/EXI0 PH1/EXI1 PH2/SYNC0/PMI PH3/SYNC1 PH4/PMSK PH5/DPG PH6/DFG PH7/CFG 8 pins Schmitt trigger input Servo circuit IP Hi-Z Data bus RD (Port G) Port H Schmitt trigger input Servo circuit IP Data bus RD (Port H) Note) PH2/SYNC0/PMI and PH3/SYNC1 can select CMOS Schmitt trigger input or TTL Schmitt trigger input with the mask option. –9– Hi-Z CXP913P048 Pin AA A AAA Schmitt trigger input CS0 SI0 AA AA AA AA AA SO0 SO0 from SIO SCK0 SO0 output enable Internal serial clock from SIO SCK0 output enable External serial clock to SIO Schmitt trigger input AAAA AAAA AAAA Port I data PI0/SI2 "0" when reset Hi-Z Hi-Z IP 1 pin Port I Hi-Z SIO IP 2 pins 1 pin When reset Circuit format Port I direction AA AA A Hi-Z IP (Every bit) Data bus RD (Port I) 1 pin SIO Port I Schmitt trigger input AAAA AAAAAAA AAA AAAAAAA AAA AA AA AAAA AA "0" when reset Port I function selection SIO MPX Port I data PI1/SO2 PI2/SCK2 SIO MPX "0" when reset Data bus 2 pins AA AA A IP Port I direction RD (Port I) SIO (PI2 only) Schmitt trigger input – 10 – Note) Only PI2 is Schmitt trigger input. Hi-Z CXP913P048 Pin When reset Circuit format Port I AAAA AAAAAA AAAA AA AAAA AA AAAA "0" when reset Port I function selection General-purpose prescaler MPX PI3/CS2/PO Port I data "0" when reset Data bus Port I direction SIO Port I PI4/PCK/OSCI Schmitt trigger input AAAA AA AA AAAA AA AA AA AA AA A AAA "0" when reset OSCI Hi-Z IP RD (Port I) 1 pin A AA AA Port I function selection General-purpose prescaler IP Oscillation Fig. 1. OSCO PI4/PCK or PI5 PI5/OSCO General-purpose prescaler IP Data bus RD (Port I) 2 pins Fig. 2. Note) The circuit format in Fig. 1 or Fig. 2 can be selected with the mask option. Port I AAAA AAAA AA AA AA AA "0" when reset PI6/XOUT Hi-Z Port I function selection Clock generator MPX General-purpose prescaler Data bus 1 pin RD (Port I) – 11 – AA AA AA IP Hi-Z CXP913P048 Pin When reset Circuit format AAAA AA AAAA AAAA Port I Input multiplexer A/D converter IP PI7/AN0 Hi-Z Data bus Port I function selection 1 pin "0" when reset RD (Port I) AAAA AA AAA AAA AAA AAAA AAAA Input multiplexer AN1 to AN3 3 pins Port J AA A AA A Port J data Port J direction "0" when reset PJ0/AN4/KS8 to PJ7/AN11/KS15 Hi-Z A/D converter IP IP Data bus RD (Port J) Hi-Z Standby release Port J input selection Input multiplexer "0" when reset 8 pins EXTAL XTAL AAAA AA AA AA AA EXTAL A/D converter Stop signal • Diagram shows circuit composition during oscillation. IP • Feedback resistor is removed during stop mode. XTAL 2 pins AA AA Mask option RST 1 pin AA AA Oscillation Pull-up resistor Schmitt trigger input OP IP Emulator (CXP913000 only) – 12 – "L" level CXP913P048 Absolute Maximum Ratings Item (VSS = 0V reference) Symbol VDD Supply voltage AVDD Rating Unit –0.3 to +7.0 AVss to +7.0∗1 V V Remarks V Input voltage VIN –0.3 to +0.3 –0.3 to +7.0∗2 Output voltage VOUT –0.3 to +7.0∗2 V High level output current IOH –5 mA High level total output current ∑IOH –50 mA Total for all output pins IOL 15 mA IOLC 20 mA All pins excluding large current output pins Large current output pins∗3 Low level total output current ∑IOL 130 mA Total for all output pins Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +150 °C Allowable power dissipation PD 380 mW AVSS Low level output current V ∗1 AVDD and VDD must be the same voltage. ∗2 VIN and VOUT must not exceed VDD + 0.3V. ∗3 N-ch transistors of PD and PE output ports are the large current drive transistors. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI. – 13 – CXP913P048 Recommended Operating Conditions Item Supply voltage Analog voltage High level input voltage Symbol Min. Max. Unit 2.7 5.5 V Guaranteed operation range for high-speed mode (1/2 frequency dividing clock) 2.7 5.5 V Guaranteed operation range for low-speed mode (1/16 frequency dividing clock) 2.5 5.5 V 2.7 5.5 V Guaranteed data hold range during stop mode ∗1 VIH 0.7VDD VDD V ∗2 VIHS 0.8VDD VDD V VIHTS 2.2 VDD V VDD AVDD VIHEX VIL Low level input voltage (VSS = 0V reference) CMOS Schmitt trigger input∗3 TTL Schmitt trigger input∗4, ∗7 0.3VDD V EXTAL∗5 ∗2 0.2VDD V ∗2, ∗6 VDD – 0.4 VDD + 0.3 0 Remarks V VILS 0 0.2VDD V VILTS 0 0.8 V CMOS Schmitt trigger input∗3 TTL Schmitt trigger input∗4, ∗7 VILEX –0.3 0.4 V EXTAL Operating temperature Topr –20 +75 °C ∗1 AVDD and VDD must be the same voltage. ∗2 PC, PD, PE, PI1, PI3 to PI7, PJ for normal input port ∗3 CS0, SI0, SCK0, RST, PF0/EC0/INT0, PF1/EC2/INT1, PF2/CS1/NMI/CINT, PF3/SI1/INT2, PF5/SCK1, PG6/RFG0, PG7/RFG1, PH (PH2 and PH3 when CMOS Schmitt trigger input is selected with the mask option), PI0/SI2, PI2/SCK2. ∗4 PH2 and PH3 (when TTL Schmitt trigger input is selected with the mask option). ∗5 Specified only during external clock input. ∗6 When the supply voltage (VDD) is within the range of 2.7 to 3.6V. ∗7 When the supply voltage (VDD) is within the range of 4.5 to 5.5V. – 14 – CXP913P048 DC Characteristics Item High level output voltage Low level output voltage (Ta = –20 to +75°C, VSS = 0V reference) Symbol VOH VOL Pin Unit VDD = 4.5V, IOH = –1.2mA 3.5 V VDD = 2.7V, IOH = –0.15mA 2.4 V VDD = 2.7V, IOH = –0.5mA 2.0 V PF4, PF5, PI1, PI2, SO0, SCK0 VDD = 4.5V, IOH = –4.0mA 3.6 V VDD = 3.0V, IOH = –4.0mA 2.0 V PA to PC, PF4 to PF7, PG0 to PG5, PI0 to PI3, PI6, PJ, SO0, SCK0, RST∗1 VDD = 4.5V, IOL = 1.8mA 0.4 V VDD = 4.5V, IOL = 3.6mA 0.6 V VDD = 2.7V, IOL = 1.2mA 0.3 V VDD = 2.7V, IOL = 1.6mA 0.5 V VDD = 4.5V, IOL = 12.0mA 1.5 V VDD = 2.7V, IOL = 5.0mA 1.0 V Input current IILE IILR RST∗2 IIZ PA to PJ, AN1 to AN3, CS0, SI0, SO0, SCK0, RST∗2 IDD∗4 VDD, VSS IDDS1∗5 VDD = 5.5V, VIH = 5.5V 0.5 40 µA VDD = 3.6V, VIH = 3.6V 0.3 20 µA VDD = 5.5V, VIL = 0.4V –0.5 –40 µA VDD = 3.6V, VIL = 0.3V –0.3 –20 µA VDD = 5.5V, VIL = 0.4V –1.5 –400 µA VDD = 3.6V, VIL = 0.3V –0.9 –200 µA VDD = 5.5V, VI = 0, 5.5V ±10 µA VDD = 3.6V, VI = 0, 3.6V ±10 µA 20MHz crystal oscillation (C1 = C2 = 10pF), VDD = 5V ± 10% 40 65 mA 20MHz crystal oscillation (C1 = C2 = 10pF), VDD = 3.3V ± 0.3V 22 40 mA 20MHz crystal oscillation (C1 = C2 = 10pF), VDD = 5V ± 10%, Sleep mode 8 14 mA 4.5 8 mA VDD = 5.5V, Stop mode 10 µA VDD = 3.6V, Stop mode 10 µA 20 pF 20MHz crystal oscillation (C1 = C2 = 10pF), VDD = 3.3V ± 0.3V, Sleep mode IDDS2 CIN Max. V EXTAL Input capacitance Typ. 4.0 IIHE Supply current∗3 Min. VDD = 4.5V, IOH = –0.5mA PA to PE, PF6 to PF7, PG0 to PG5, PI0, PI3, PI6, PJ PD, PE I/O leakage current Conditions Pins other than VDD, VSS, AVDD, AVSS Clock 1MHz 0V for all pins excluding measured pins – 15 – 10 CXP913P048 ∗1 RST is specified only in evaluation mode. ∗2 In RST, the input current is specified when pull-up resistor is selected; the leakage current is specified when no resistor is selected. ∗3 When all output pins are open. ∗4 When the upper two bits (CPU clock selected) of the clock control register (CLC: 0002FEh) are set to "00" and the LSI is operated in high-speed mode (1/2 frequency dividing clock). ∗5 When the clock generator output is not selected at PI6. AC Characteristics (1) Clock timing Item (Ta = –20 to +75°C, VSS = 0V reference) Symbol Pin Conditions Min. Max. Unit VDD = 5.0V ± 10% 1 20 MHz VDD = 3.0V ± 10% 1 20 MHz VDD = 5.0V ± 10% Fig. 1, Fig. 2 External clock drive VDD = 3.0V ± 10% 20 ns EXTAL 20 ns tCR, tCF EXTAL VDD = 5.0V ± 10% Fig. 1, Fig. 2 External clock drive VDD = 3.0V ± 10% Event count input clock pulse width tEH, tEL PF0/EC0, PF1/EC2 Fig. 3 Event count input clock rise time, fall time tER, tEF PF0/EC0, PF1/EC2 Fig. 3 System clock frequency fC XTAL, EXTAL Fig. 1, Fig. 2 System clock input pulse width tXH, tXL System clock input rise time, fall time 200 ns 200 ns tsys + 50∗1 ns VDD = 3.0V ± 10% tsys + 100∗1 ns VDD = 5.0V ± 10% VDD = 5.0V ± 10% 20 ms VDD = 3.0V ± 10% 20 ms ∗1 tsys indicates the three values below according to the upper two bits (CPU clock selected) of the clock control register (CLC: 0002FEh). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Fig. 1. Clock timing 1/fc VDD – 0.4V EXTAL 0.4V AAAA AAAAA AAAA AAAAA AAAA AAAAA tXH tCF tXL tCR Fig. 2. Clock applied conditions Crystal oscillation EXTAL External clock EXTAL XTAL XTAL 74HC04 Fig. 3. Event count clock timing 0.8VDD PF0/EC0 PF1/EC2 0.2VDD tEH tEF – 16 – tEL tER CXP913P048 (2) Serial transfer (CH0, CH1, CH2) Item Symbol (Ta = –20 to +75°C, VSS = 0V reference) Conditions Pin SCK0, Chip select transfer tsys + 200 SCK2 (SCK = output mode) VDD = 3.0V ± 10% tsys + 250 SO0, VDD = 5.0V ± 10% tsys + 200 SO2 (SCK = output mode) VDD = 3.0V ± 10% tsys + 250 SO0, Chip select transfer mode VDD = 5.0V ± 10% Chip select transfer mode VDD = 5.0V ± 10% tsys + 200 tsys + 250 tsys + 200 tsys + 250 tDCSK SCK1, mode CS ↑ → SCK float delay time tDCSKF SO1, mode CS ↓ → SO delay time tDCSO SO1 CS ↑ → SO float delay time tDCSOF CS1 SCK cycle time SO2 CS0, CS2 Chip select transfer SI input setup time (for SCK ↑) SI input hold time (for SCK ↑) SCK ↓ → SO delay time tKCY Input mode SCK0, SCK1, SCK2 Output mode VDD = 3.0V ± 10% tKH, tKL tSIK tKSI tKSO SI0, SI1, SI2 SO0, SO1, SO2 tINT 16000/fc VDD = 3.0V ± 10% 16000/fc ns ns ns ns ns ns tsys + 100 VDD = 3.0V ± 10% tsys + 100 VDD = 5.0V ± 10% SCK0, SCK1, SCK2 Output mode SI0, SI1, SI2 VDD = 5.0V ± 10% Unit ns VDD = 3.0V ± 10% 2tsys + 200 ns VDD = 5.0V ± 10% 8000/fc – 50 ns VDD = 3.0V ± 10% 8000/fc – 75 SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode Minimum interval time VDD = 3.0V ± 10% SCK0, VDD = 5.0V ± 10% tsys + 100 tWHCS SCK1 Chip select transfer mode VDD = 3.0V ± 10% tsys + 100 SCK2 VDD = 5.0V ± 10% 2tsys + 200 Input mode SCK high, low level width Max. VDD = 5.0V ± 10% CS ↓ → SCK delay time CS high level width Min SCK0, SCK1, SCK2 SCK output mode – 17 – VDD = 5.0V ± 10% 100 VDD = 3.0V ± 10% 100 ns VDD = 5.0V ± 10% 200 – tsys ns VDD = 3.0V ± 10% 200 – tsys tsys + 100 VDD = 3.0V ± 10% tsys + 100 VDD = 5.0V ± 10% tsys + 100 VDD = 3.0V ± 10% tsys + 100 VDD = 5.0V ± 10% ns ns VDD = 3.0V ± 10% tsys + 100 tsys + 150 VDD = 5.0V ± 10% 50 VDD = 3.0V ± 10% 100 VDD = 5.0V ± 10% VDD = 5.0V ± 10% 2tsys + 100 VDD = 3.0V ± 10% 2tsys + 125 VDD = 5.0V ± 10% 8000/fc – 50 VDD = 3.0V ± 10% 8000/fc – 75 ns ns ns ns CXP913P048 Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selected) of the clock control register CLC (address: 0002FEh). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Note 2) The load condition for the SCK output mode, SO output delay time is 150pF when VDD = 5.0V ± 10% and 100pF when VDD = 3.0V ± 10%. Fig. 4. Serial transfer CH0, CH1, CH2 timing tWHCS 0.8VDD CS0 CS1 CS2 0.2VDD tKCY tDCSK tKL tDCSKF tKH 0.8VDD SCK0 SCK1 SCK2 0.2VDD tSIK tKSI 0.8VDD SI0 SI1 SI2 Input data 0.2VDD tDCSO SO0 SO1 SO2 tDCSOF tKSO 0.8VDD Output data 0.2VDD tINT 0.8VDD SCK0 SCK1 SCK2 – 18 – CXP913P048 (3) A/D converter characteristics (Ta = –20 to +75°C, VDD = AVDD = AVREF = 2.7 to 5.5V, VSS = AVSS = 0V reference) Item Symbol Pin Conditions Min. Typ. Resolution Linearity error VZT∗1 Zero transition voltage Ta = 25°C Max. Unit 8 Bits VDD = AVDD = 5.0V ±1.5 VDD = AVDD = 3.0V ±1.5 VDD = AVDD = 5.0V –10 10 50 VDD = AVDD = 3.0V –10 5 35 VDD = AVDD = 5.0V 4935 4975 5015 VDD = AVDD = 3.0V 2955 2985 3015 LSB mV Full-scale transition voltage VFT∗2 Conversion time Sampling time tCONV tSAMP Reference input voltage VREF AVREF 0.9AVDD AVDD V Analog input voltage VIAN AN0 to AN11 0 AVREF V Operation mode IREF AVREF AVREF current 200tsys µs 14tsys µs VDD = 5.5V 0.65 1.2 VDD = 3.6V 0.45 0.8 Sleep mode VDD = 5.5V Stop mode VDD = 3.6V IREFS mV 10 mA µA 10 ∗1 VZT: Value at which the digital conversion value changes from 00h to 01h and vice versa. ∗2 VFT: Value at which the digital conversion value changes from FEh to FFh and vice versa. Note) tsys indicates the three values below according to the upper two bits (CPU clock selected) of the clock control register (CLC: 0002FEh). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Fig. 5. Definition of A/D converter terms Digital conversion value FFH FEH Linearity error 01H 00H VFT VZT Analog input – 19 – CXP913P048 (4) Interruption and reset input Item (Ta = –20 to +75°C, VDD = 2.7 to 5.5V, VSS = 0V reference) Symbol Pin Conditions External interruption high, low level width tIH, tIL NMI INT0 INT1 INT2 PD0 to PD7 Reset input low level width tRSL RST Min. Max. Unit 1 µs 6tsys∗1 µs ∗1 tsys indicates the three values below according to the upper two bits (CPU clock selected) of the clock control register (CLC: 0002FEh). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Fig. 6. Interruption input timing tIH tIL NMI INT0 INT1 INT2 PD0 to PD7 PJ0 to PJ7 (During standby release input) (Falling edge) 0.8VDD 0.2VDD Fig. 7. RST input timing tRSL RST 0.2VDD – 20 – CXP913P048 (5) General-purpose prescaler Item (Ta = –20 to +75°C, Vss = 0V reference) Symbol Pin External clock input frequency fPCK PCK External clock input pulse width tWH, tWL PCK External clock input rise time, fall time tR, tF PCK tPLH Prescaler output delay time (for PCK ↑) PO tPHL tTLH Prescaler output rise time, fall time PO tTHL Conditions Min. 12 VDD = 3.0V ± 10% 12 VDD = 5.0V ± 10% 33 VDD = 3.0V ± 10% 33 200 VDD = 3.0V ± 10% 200 VDD = 5.0V ± 10% External clock input VDD = 3.0V ± 10% PCK VDD = 5.0V ± 10% tR = tF = 6ns 80 130 130 220 60 100 VDD = 3.0V ± 10% 90 150 VDD = 5.0V ± 10% External clock input VDD = 3.0V ± 10% PCK VDD = 5.0V ± 10% tR = tF = 6ns 50 100 100 280 20 40 VDD = 3.0V ± 10% 40 80 1/fPCK tWH tF 0.8VDD 0.5VDD 0.2VDD tWL tPLH tR tPHL 0.8VDD 0.5VDD 0.2VDD tTLH tTHL – 21 – Unit MHz ns VDD = 5.0V ± 10% Fig. 8. General-purpose prescaler timing PO Max. VDD = 5.0V ±10% Note) PO pin load condition: 50pF PCK Typ. ns ns ns ns ns CXP913P048 (6) Other (Ta = –20 to +75°C, VSS = 0V reference) Item Symbol Pin CFG input high, low level width tCFH, tCFL CFG DFG input high, low level width tDFH, tDFL DFG DPG minimum pulse width tDPW DPG DPG minimum removal time tDPR DPG RFG input high, low level width tRFH, tRFL RFG0 RFG1 EXI input high, low level width tEIH, tEIL EXI0 EXI1 PMI input high, low level width tPIH, tPIL PMI PMSK minimum pulse width tPMW PMSK PMSK minimum removal time tPMR PMSK VDD = 5.0V ± 10% Note) Typ. Max. tsys +200 tsys +200 Unit ns ns VDD = 3.0V ± 10% 1000/fc +200 VDD = 5.0V ± 10% 50 VDD = 3.0V ± 10% 50 VDD = 5.0V ± 10% 50 VDD = 3.0V ± 10% 50 VDD = 5.0V ± 10% tsys +200 tsys +200 tsys +200 tsys +200 tsys +200 tsys +200 tsys +200 tsys +200 tsys +200 tsys +200 VDD = 3.0V ± 10% When tsys = 2000/fc VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% XOUT tTHL VDD = 3.0V ± 10% Min. VDD = 5.0V ± 10% 1000/fc +200 tTLH XOUT output rise time, fall time Conditions VDD = 3.0V ± 10% When the load is 50pF ns ns ns ns ns ns ns VDD = 5.0V ± 10% 50 100 VDD = 3.0V ± 10% 100 280 VDD = 5.0V ± 10% 20 40 VDD = 3.0V ± 10% 40 80 ns tsys indicates the three values below according to the upper two bits (CPU clock selected) of the clock control register (CLC: 0002FEh). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") – 22 – CXP913P048 Fig. 9. Other timing tCFH tCFL 0.8VDD CFG 0.2VDD tDFH tDFL 0.8VDD DFG 0.2VDD tDPR tDPW tDPR 0.8VDD DPG tRFH tRFL 0.8VDD RFG0 RFG1 0.2VDD tEIH tEIL 0.8VDD EXI0 EXI1 0.2VDD tPIH tPIL 0.8VDD PMI 0.2VDD tPMR tPMW tPMR 0.8VDD PMSK 0.8VDD XOUT 0.2VDD tTLH tTHL – 23 – CXP913P048 Appendix Fig. 10. Recommended oscillation circuit AAAAA AAAAA AAAAA AAAA AAAA AAAA General-purpose prescaler clock Mask option Main clock EXTAL C1 Manufacturer Model OSCI XTAL C2 OSCO C2 C1 Main clock fc (MHz) C1 (pF) General-purpose prescaler clock C2 (pF) C1 (pF) C2 (pF) 4 4 4 4 12 RIVER ELETEC CO.,LTD. HC-49/U03 16 10 10 20 12 HC-49/U (-S) KINSEKI LTD. 16 10 10 20 Note 1) Use the general-purpose prescaler clock at 12MHz or less. Note 2) Crystals and capacitors should be placed near the LSI and wiring should be as short as possible. Product List Item Package Mask ROM CXP913P048R-2- 100-pin plastic LQFP 100-pin plastic LQFP 160K byte PROM 192K byte EXTAL system operating voltage∗1 2.7 to 5.5V/4.5 to 5.5V 2.7 to 5.5V Reset pin pull-up resistor Existent/Non-existent Existent ROM capacity PH2 input format CMOS Schmitt trigger/ TTL Schmitt trigger CMOS Schmitt trigger PH3 input format CMOS Schmitt trigger/ TTL Schmitt trigger CMOS Schmitt trigger PI4/PI5 pin format Oscillation circuit/Input port Oscillation circuit ∗1 Select 4.5V to 5.5V when this LSI is used with a supply voltage range of 4.5V to 5.5V. – 24 – CXP913P048 Example of Representative Characteristics IDD vs. VDD (fc = 20MHz, Ta = 25°C, Typical) 50 1/2 frequency dividing mode IDD – Supply current [mA] 40 30 25 1/4 frequency dividing mode 20 1/8 frequency dividing mode 15 1/16 frequency dividing mode 10 Sleep mode 8 6 5 4 3 2 3 4 5 6 VDD – Supply voltage [V] IDD vs. fC IDD – Supply current [mA] (VDD = 5V, Ta = 25°C, Typical) 1/2 frequency dividing mode 40.00 38.00 36.00 34.00 32.00 30.00 28.00 26.00 24.00 22.00 20.00 18.00 16.00 14.00 12.00 10.00 8.00 6.00 4.00 2.00 0.00 1/4 frequency dividing mode 1/8 frequency dividing mode 1/16 frequency dividing mode Sleep mode 0 5 10 15 fc – System clock [MHz] – 25 – 20 CXP913P048 Package Outline Unit: mm 100PIN LQFP (PLASTIC) 16.0 ± 0.2 ∗ 14.0 ± 0.1 75 51 76 (15.0) 50 0.5 ± 0.2 A 26 (0.22) 100 1 0.5 + 0.08 0.18 – 0.03 25 + 0.2 1.5 – 0.1 0.13 M + 0.05 0.127 – 0.02 0.1 0° to 10° 0.5 ± 0.2 0.1 ± 0.1 DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE LQFP-100P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE LQFP100-P-1414 LEAD MATERIAL 42 ALLOY PACKAGE MASS 0.8g JEDEC CODE – 26 –