CXD2452R
Timing Generator for Progressive Scan CCD Image Sensor
Description
The CXD2452R is a timing generator which generates
the timing pulses for performing progressive scan
readout for digital still cameras and personal
computer image input applications using the
ICX098AK CCD image sensor.
Features
• Base oscillation frequency 36.81MHz (2340fH)
• Monitoring readout allowed
• High-speed/low-speed electronic shutter function
• Horizontal driver for CCD image sensor
• Signal processor IC system clock generation 1170fH,
780fH
• Vertical/horizontal sync (SSG) timing generation
Applications
• Digital still cameras
• Personal computer image input
• Operating temperature
Topr
V
V
V
°C
°C
V
–20 to +75
°C
Applicable CCD Image Sensors
ICX098AK (Type 1/4 CCD)
RST
VDD6
SSI
SSK
SEN
FRO
EBCKSM
HRO
HRI
FRI
Pin Configuration
VSS5
Absolute Maximum Ratings
Vss – 0.5 to +7.0
• Supply voltage VDD
• Input voltage
VI
Vss – 0.5 to VDD + 0.5
• Output voltage VO
Vss – 0.5 to VDD + 0.5
• Operating temperature
Topr
–20 to +75
• Storage temperature
Tstg
–55 to +150
Recommended Operating Conditions
• Supply voltage
VDDa, VDDb, VDDc, VDDd 3.0 to 3.6
Structure
Silicon gate CMOS IC
CLD
48 pin LQFP (Plastic)
36 35 34 33 32 31 30 29 28 27 26 25
DSGAT 37
24 VDD5
MCK 38
23 3/2MCK
VSS6 39
22 1/2MCK
XSUB 40
21 PBLK
XV3 41
20 VSS4
XSG2 42
19 XRS
18 XSHD
XSG1 43
XV2 44
VDD7 45
XV1 46
17
XSHP
16
VDD4
15 XCLPDM
5
6
7
8
9 10 11 12
TEST
VDD1
XCLPOB
VDD2
RG
H1
4
VSS3
3
VSS2
2
ID
H2
1
WEN
VDD3
13
VSS1
14
OSCI 48
3MCK
OSCO 47
*Groups of pins enclosed in the fingure indicate sections for which power supply separationis possible.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96830C9X
CXD2452R
OSCI
XRS
XV1
19
46 44 41 43 42
OSCO
XV3
XSG2
XSHD
17 18
XSG1
XSHP
9
XV2
RG
12 13
H1
H2
Block Diagram
48
47
40 XSUB
21 PBLK
3/2MCK 23
1/2MCK
22
15 XCLPDM
1/3
1
Pulse Generator
1/2
Latch
3MCK
1/2
CLD 35
MCK
7
XCLPOB
4
ID
3
WEN
HRI
differential
38
6
8
Latch
14
VDD
16
24
Latch
26
45
SSG
27 SSI
Register
1/390
29 SEN
2
1/2
10
11
20
36
1/525
–2–
25 37 30
EBCKSM
5
DSGAT
FRI
34
RST
33
HRI
32
HRO
31
TEST
39
FRO
VSS
28 SSK
CXD2452R
Pin Description
Pin
No.
Symbol
I/O
Description
1
3MCK
I
2
Vss1
—
GND
3
WEN
O
Memory write timing.
Stop control possible using the serial interface data.
4
ID
O
Vertical direction line identification pulse output.
Stop control possible using the serial interface data.
5
TEST
I
IC test pin; normally fixed to GND. (With pull-down resistor)
6
VDD1
—
3.3V power supply. (Power supply for common logic block)
7
XCLPOB
O
CCD optical black signal clamp pulse output.
Stop control possible using the serial interface data.
8
VDD2
—
3.3V power supply. (Power supply for RG)
9
RG
O
CCD reset gate pulse output. (780fH)
10
Vss2
—
GND
11
Vss3
—
GND
12
H1
O
CCD horizontal register drive clock output. (780fH)
13
H2
O
CCD horizontal register drive clock output. (780fH)
14
VDD3
—
3.3V power supply. (Power supply for H1/H2)
15
XCLPDM
O
Pulse output for dummy bit block clamp .
16
VDD4
—
3.3V power supply. (Power supply for CDS system)
17
XSHP
O
Precharge level sample-and-hold pulse output. (780fH)
18
XSHD
O
Data level sample-and-hold pulse output. (780fH)
19
XRS
O
Sample-and-hold pulse output for analog/digital conversion phase alignment. (780fH)
20
Vss4
—
GND
21
PBLK
O
Pulse output for horizontal and vertical blanking interval pulse cleaning.
22
1/2MCK
O
Horizontal direction pixel identification pulse output.
Stop control possible using the serial interface data.
23
3/2MCK
—
System clock output for signal processing IC (1170fH).
Stop control possible using the serial interface data.
24
VDD5
—
3.3V power supply. (Power supply for common logic block)
25
RST
I
26
VDD6
—
27
SSI
I
Serial interface data input for internal mode settings.
28
SSK
I
Serial interface clock input for internal mode settings.
29
SEN
I
Serial interface strobe input for internal mode settings.
30
EBCKSM
I
CHKSUM enable. (With pull-down resistor)
High: Sum check invalid, Low: Sum check valid
31
FRO
O
Vertical sync signal output.
Stop control possible using the serial interface data.
Internal main clock. (2340fH)
Internal system reset input. High: Normal status, Low: Reset status
Always input one reset pulse after power-on.
3.3V power supply. (Power supply for common logic block)
–3–
CXD2452R
Pin
No.
Symbol
I/O
Description
32
HRO
O
Horizontal sync signal output.
Stop control possible using the serial interface data.
33
HRI
I
Horizontal sync signal input.
34
FRI
I
Vertical sync signal input.
35
CLD
O
Clock output for analog/digital conversion IC. (780fH)
Phase adjustment in 60° units possible using the serial interface data.
36
VSS5
—
GND
37
DSGAT
I
Control input used to stop pulse generation for CCD image sensor, sample-andhold IC and analog/digital conversion IC. High: Normal status, Low: Stop status
Controlled pulse can be changed using the serial interface data.
38
MCK
O
System clock output for signal processor IC. (780fH)
39
Vss6
—
GND
40
XSUB
O
Pulse output for electronic shutter.
41
XV3
O
CCD vertical register drive pulse output.
42
XSG2
O
CCD sensor readout pulse output.
43
XSG1
O
CCD sensor readout pulse output.
44
XV2
O
CCD vertical register drive pulse output.
45
VDD7
—
3.3V power supply. (Power supply for common logic block)
46
XV1
O
CCD vertical register drive pulse output.
47
OSCO
O
Inverter output for oscillation.
48
OSCI
I
Inverter input for oscillation.
–4–
CXD2452R
Electrical Characteristics
(Within the recommended operating conditions)
DC Characteristics
Item
Pins
Symbol
Conditions
Min.
Typ.
Max.
Unit
Supply voltage 1
VDD2
VDDa
3.0
3.3
3.6
V
Supply voltage 2
VDD3
VDDb
3.0
3.3
3.6
V
Supply voltage 3
VDD4
VDDc
3.0
3.3
3.6
V
Supply voltage 4
VDD1, VDD5,
VDD6, VDD7
VDDd
3.0
3.3
3.6
V
RST, DSGAT,
Input voltage 1∗1 SSI, SSK, SEN,
FRI, HRI
VIH1
0.8VDDd
Input
voltage 2∗1 ∗2
EBCKSM
VIH2
Input
voltage 3∗2
TEST
Output
voltage 1
RG
Output
voltage 2
H1, H2
Output
voltage 3
XSHP, XSHD,
XRS, PBLK,
XCLPDM
V
0.2VDDd
VIL1
0.8VDDd
V
0.2VDDd
VIL2
0.7VDDd
VIH3
VDDa – 0.8
VOH1
Feed current where IOH = –3.3mA
VOL1
Pull-in current where IOL = 2.4mA
VOH2
Feed current where IOH = –10.4mA VDDb – 0.8
VOL2
Pull-in current where IOL = 7.2mA
VOH3
Feed current where IOH = –3.3mA
VOL3
Pull-in current where IOL = 2.4mA
VOH4
Feed current where IOH = –10.4mA VDDd – 0.8
VOL4
Pull-in current where IOL = 7.2mA
VOH5
Feed current where IOH = –3.3mA
Output
voltage 4
3/2MCK, MCK,
CLD
Output
voltage 5
1/2MCK
VOL5
Pull-in current where IOL = 2.4mA
Output
voltage 6
XV1, XV2, XV3, VOH6
XSUB, XSG1,
XSG2, XCLPOB,
VOL6
ID, WEN
Feed current where IOH = –2.4mA
Output
voltage 7
FRO, HRO
VOH7
Feed current where IOH = –3.6mA
VOL7
Pull-in current where IOL = 7.2mA
–5–
V
V
0.4
V
V
VDDc – 0.8
0.4
V
V
0.4
VDDd – 0.8
V
V
0.4
VDDd – 0.8
V
V
0.4
VDDd – 0.8
∗1 These input pins do not have protective diodes on the internal power supply side.
∗2 These input pins have internal pull-down resistors.
∗3 The above table indicates the condition for 3.3V drive.
V
V
0.4
Pull-in current where IOL = 4.8mA
V
V
0.3VDDd
VIL3
V
V
V
0.4
V
CXD2452R
(Within the recommended operating conditions)
Inverter I/O Characteristics for Oscillation
Item
Pins
Logical Vth
OSCI
Input voltage
OSCI
Output voltage
Feedback resistor
Symbol
Conditions
Min.
LVth
Typ.
VDDd/2
VIH
V
OSCI, OSCO
Oscillation frequency OSCI, OSCO
0.3VDDd
VOH
Feed current where
IOH = –6.0mA
VOL
Pull-in current where
IOL = 6.0mA
RFB
VIN = VDDd or Vss
f
VDDd/2
500k
Unit
V
0.7VDDd
VIL
OSCO
Max.
V
V
2M
20
VDDd/2
V
5M
Ω
50
MHz
Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment
(Within the recommended operating conditions)
Item
Pins
Logical Vth
Input voltage
Input amplitude
Symbol
Conditions
Min.
LVth
V
0.3VDDd
fmax 50MHz sine
wave
0.3
Unit
V
0.7VDDd
VIL
VIN
Max.
VDDd/2
VIH
3MCK
Typ.
V
Vp-p
∗1 Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude is
the input amplitude characteristics in the case of input through capacitor.
–6–
CXD2452R
AC Characteristics
1) AC characteristics between the serial interface clocks
0.8VDDd
SSI
0.2VDDd
0.8VDDd
SSK
0.2VDDd
ts1
SEN
th1
0.2VDDd
ts3
0.8VDDd
SEN
ts2
th2
(Within the recommended operating conditions)
Symbol
ts1
th1
ts2
th2
ts3
Definition
Min.
Typ.
Max.
Unit
SSI setup time, activated by the rising edge of SSK
20
ns
SSI hold time, activated by the rising edge of SSK
20
ns
SSK setup time, activated by the rising edge of SEN
20
ns
SSK hold time, activated by the rising edge of SEN
20
ns
SEN setup time, activated by the rising edge of SSK
20
ns
2) Serial interface clock internal loading characteristics
Example: During recording drive mode
FRI
HRI
XSG1
Enlarged view
HRI
0.2VDDd
XSG1
SEN
ts4
th4
0.8VDDd
0.2VDDd
Note) Be sure to maintain a constantly high SEN logic level near the HRI fall immediately before XSG1
generation.
(Within the recommended operating conditions)
Symbol
ts4
th4
Definition
Min.
Typ.
Max.
Unit
SEN setup time, activated by the falling edge of HRI
0
ns
SEN hold time, activated by the falling edge of HRI
0
ns
–7–
CXD2452R
3) Serial interface clock output variation characteristics
Normally, the serial interface data is loaded to the CXD2452R at the timing shown in 2) above. However, one
exception to this is when the data such as SSGSEL and STB is loaded to the CXD2452R and controlled at the
rising edge of SEN. For STB, see control data D62 to D63 STB in “Description of Operation”.
0.8VDDd
SEN
Output signal
tpdPULSE
(Within the recommended operating conditions)
Definition
Symbol
tpdPULSE
Min.
Output signal delay, activated by the rising edge of SEN
Typ.
5
Max.
Unit
100
ns
4) RST loading characteristics
0.8VDDd
RST
0.2VDDd
tw1
(Within the recommended operating conditions)
Symbol
tw1
Definition
Min.
RST pulse width
Typ.
Max.
Unit
ns
35
5) Phase identification characteristics using FRI and HRI input
When the HRI logic level is low tpd1 after the
falling edge of FRI
When the HRI logic level is high tpd1 after the
falling edge of FRI
FRI
FRI
HRI
0.2VDDd
tpd1
0.2VDDd
tpd1
HRI
The field is identified as an ODD field .
The field is identified as an EVEN field .
(Within the recommended operating conditions)
Symbol
Definition
Min.
tpd1
Field identification clock phase, activated by the falling edge of FRI
1100
–8–
Typ.
Max.
Unit
1300
ns
CXD2452R
6) FRI and HRI loading characteristics
0.8VDDd
0.8VDDd
FRI, HRI
ts5
th5
0.8VDDd
MCK
MCK load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
ts5
th5
Definition
Miin.
Typ.
Min.
Unit
FRI and HRI setup time, activated by the rising edge of MCK
10
ns
FRI and HRI hold time, activated by the rising edge of MCK
0
ns
7) Output timing characteristics using DSGAT
DSGAT
0.2VDDd
H1, H2, RG, XV1, XV2, XV3, XSUB, XSG1, XSG2,
XSHP, XSHD, XRS, PBLK, XCLPDM, XCLPOB, CLD
0.2VDDd
tpDSGAT
H1 and H2 load capacitance = 100pF, RG load capacitance = 20pF, XV1, XV2, XV3, XSG1, XSG2, XSUB,
XSHP, XSHD, XRS, PBLK, XCLPDM, XCLPOB and CLD load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
tpDSGAT
Definition
Min.
Typ.
Time until the above outputs go low after the fall of DSGAT
Max.
Unit
100
ns
8) Output variation characteristics
MCK
0.8VDDd
WEN, ID
tpd2
WEN and ID load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
tpd2
Definition
Miin.
Time until the above outputs change after the rise of MCK
–9–
20
Typ.
Min.
Unit
40
ns
CXD2452R
9) H1 and RG waveform characteristics
0.9VDDb
0.9VDDb
H1
0.1VDDb
0.9VDDa
trH1
0.1VDDb
tfH1
0.9VDDa
RG
0.1VDDa
trRG
0.1VDDa
tfRG
VDDb = 3.3V, Topr = 25°C, H1 and H2 load capacitance = 100pF, RG load capacitance = 20pF
(Within the recommended operating conditions)
Symbol
Definition
Min.
Typ.
Max.
Unit
trH1
tfH1
trRG
H1 rise time
10
ns
H1 fall time
10
ns
RG rise time
3
ns
tfRG
RG fall time
3
ns
(Within the recommended operating conditions)
10) I/O pin capacitance
Symbol
Definition
Min.
Typ.
Max.
Unit
CIN
Input pin capacitance
9
pF
COUT
Output pin capacitance
11
pF
CI/O
I/O pin capacitance
11
pF
– 10 –
CXD2452R
Description of Operation
All pulses output from the CXD2452R are controlled by the RST and DSGAT pins and by the serial interface
data shown below. The details of control by the serial interface data and a description of operation are as
follows.
SSI
00 01 02 03 04 05 06 07 08 09 10 11
58 59 60 61 62 63 64 65 66 67 68 69 70 71
SSK
SEN
The CXD2452R basically loads and reflects the serial interface data sent in the above format in the readout
portion at the falling edge of HRI. Here, readout portion specifies the horizontal interval during which XSG1
rises.
There are two types of serial interface data: drive control data and phase adjustment data. Hereafter, these
data are distinguished by referring to the former as control data and the latter as adjustment data.
An example of the initialization data for the CXD2452R control data is shown below. This data is based on the
Application Circuit Block Diagram, so care should be taken as there are some differences from the RST pin
initialization data. Concretely, the internal SSG operates, the XCLPOB and ID pulses are generated, and the
3/2 MCK pulse is stopped. This data shows the values when the EBCKSM pin is low and D64 to D71
CHKSUM is valid.
MSB
D71 D70
1
0
MSB
D55 D54
1
1
MSB
D39 D38
0
0
MSB
D23 D22
0
0
MSB
D07 D06
1
0
D69
D68
D67
D66
D65
D64
D63
D62
D61
D60
D59
D58
D57
LSB
D56
1
0
1
1
0
1
0
0
0
0
0
0
1
0
D53
D52
D51
D50
D49
D48
D47
D46
D45
D44
D43
D42
D41
LSB
D40
0
1
0
0
0
0
0
0
0
0
0
0
0
0
D37
D36
D35
D34
D33
D32
D31
D30
D29
D28
D27
D26
D25
LSB
D24
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D09
LSB
D08
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D05
D04
D03
D02
D01
LSB
D00
0
0
0
0
0
1
The adjustment data does not normally need to be set. However, when adjustment is difficult due to the
system configuration or for other reasons, the data considered most appropriate at that time should be set as
the initialization data.
– 11 –
CXD2452R
Control Data
Data
Symbol
Function
Data = 0
Data = 1
When a reset
D00
to
D07
CHIP
Chip switching
See D00 to D07 CHIP.
All 0
D08
to
D15
CTGRY
Category switching
See D08 to D15 CTGRY.
All 0
D16
to
D17
SMD
Electronic shutter mode setting
See D16 to D35
Electronic shutter mode.
All 0
D18
to
D25
Shut.FRM
Electronic shutter vertical interval
setting
See D16 to D35
Electronic shutter mode.
All 0
D26
to
D35
Shut.HD
Electronic shutter horizontal interval
setting
See D16 to D35
Electronic shutter mode.
All 0
D36
to
D47
D48
—
—
—
All 0
Recording exposure setting switching
OFF
ON
0
—
—
—
All 0
Monitoring
Recording
0
—
EXPOSE
D49
to
D50
—
D51
PSMT
Drive mode switching
D52
SSGSEL
Internal SSG operation switching
OFF
ON
0
D53
WENSEL
WEN pulse operation switching
ON
OFF
0
D54
CLPSEL
XCLPOB pulse operation switching
OFF
ON
0
D55
IDSEL
ID pulse operation switching
OFF
ON
0
D56
HMCKSEL
1/2MCK pulse operation switching
OFF
ON
0
D57
TMCKSEL
3/2MCK pulse operation switching
ON
OFF
0
D58
HMCKREV
1/2MCK pulse reset polarity switching Positive polarity Negative polarity
0
D59
TMCKREV
2/3MCK pulse reset polarity switching Negative polarity Positive polarity
0
D60
to
D61
DSG
Pulse generation control
See D60 to D61 DSG table.
All 0
D62
to
D63
STB
IC pin status control
See D62 to D63 STB table.
All 0
D64
to
D71
CHKSUM
Check sum bit
See D64 to D71 CHKSUM.
All 0
– 12 –
CXD2452R
Detailed Description of Each Data
D00 to D07 CHIP
The serial interface data is loaded to the CXD2452R when D00 and D07 are 1. However, this assumes that
either the EBCKSM pin is low and D64 to D71 CHKSUM is satisfied or the EBCKSM pin is high.
MSB
D07 D06
1
0
D05
D04
D03
D02
D01
LSB
D00
0
0
0
0
0
1
Function
Loading to the CXD2452R
Note that when SEN is shared with other ICs and indentification is performed using CHIP-ID, the CXD2452R
data must be positioned immeditately before the load timing, that is to say at the very end.
D08 to D15 CTGRY
Of the data provided to the CXD2452R by the serial interface, the CXD2452R loads D16 and subsequent data
to the control register side when D08 is 0, and to the adjustment register side when D08 is 1. However, this
assumes that the CXD2452R is selected by CHIP and that either the EBCKSM pin is low and D64 to D71
CHKSUM is satisfied or the EBCKSM pin is high.
MSB
D15 D14
D13
D12
D11
D10
D09
LSB
D08
Function
0
0
0
0
0
0
0
0
Loading to the control register side
0
0
0
0
0
0
0
1
Loading to the adjustment register side
Note that the CXD2452R cannot apply both categories simultaneously during the same vertical interval. Also,
care should be taken as the data is overwritten even if the same category is applied.
D16 to D35 Electronic shutter mode
The CXD2452R's electronic shutter mode can be switched as follows by SMD D16 to D17 . Handling of the
data from D18 to D35 differs according to the mode, and is explained in detail below.
D17
D16
Description of operation
X
0
XSUB stopped mode
0
1
High-speed/low-speed shutter mode
1
1
HTSG control mode
The electronic shutter data is expressed as shown in the table below using Shut.HD as an example.
MSB
D35
0
↓
1
LSB
D34
D33
D32
1
1
1
↓
C
D31
D30
D29
D28
0
0
0
0
↓
3
D27
D26
1
1
Shut.HD is expressed as 1C3h .
[XSUB stopped mode]
During this mode, the data from D18 to D35 is invalid. The shutter speed is 1/60s during monitoring drive
mode, and 1/30s during recording drive mode.
– 13 –
CXD2452R
[High-speed/low-speed shutter mode]
During this mode, the data has the following meanings.
Symbol
Data
Description
Shut.FRM
D18 to D25
Shutter speed data (number of vertical intervals) specification
Shut.HD
D26 to D35
Shutter speed data (number of horizontal intervals) specification
The CXD2452R does not distinguish between the high-speed shutter and low-speed shutter modes. The
interval during which Shut.FRM and Shut.HD are specified together is the shutter speed. At this time,
Shut.FRM controls the XSG1, XSG2 output, and Shut.HD controls the XSUB output. Concretely, when
specifying high-speed shutter, Shut.FRM is set to 00h. (See the figure.) During low-speed shutter, or in other
words when Shut.FRM is set to 01h or higher, the serial interface data is not loaded until this interval is
finished.
However, care should be taken as the vertical interval indicated here is set in 1/60s units when the drive mode
is monitoring drive mode and 1/30s units during recording drive mode.
For monitoring drive mode, care should be taken that shut.HD value is offset. This is because the same
exposure time can be obtained for the same shut.HD data without depending on drive mode basically for highspeed shutter.
Formula for calculating the electronic shutter speed: [Shut.FRM/Shut.HD] (unit: µs)
Monitoring drive mode:
T = Shut.FRM∗1.66834∗104 + {(20Ch – Shut.HD)∗780 + 447} ∗81.5∗10–3 (107h ≤ Shut.HD ≤ 20Ch)
FRI
XSG1
XSUB
Shut.HD-106h
SMD
01
Shut. FRM
00h
Shut. HD
Shut.FRM
01
01
AA
1A6h
WEN
01h
00h
1DDh
1A6h
During monitoring drive mode/low-speed shutter mode
Recording drive mode:
T = Shut.FRM∗3.33667∗104 + {(20Ch – Shut.HD)∗780 + 447} ∗81.5∗10–3 (000h ≤ Shut.HD ≤ 20Ch)
FRI
XSG1
XSUB
Shut.HD
SMD
Shut. FRM
Shut. HD
WEN
Shut.FRM
01
AA
01
01h
00h
1DDh
1A6h
During recording drive mode/low-speed shutter mode
– 14 –
CXD2452R
Electronic shutter speed table [Shut.FRM/Shut.HD]
Shut.FRM Shut.HD
Shutter speed
(s)
Calculation
results (s)
Shut.FRM Shut.HD
Shutter speed
(s)
Calculation
results (s)
1/60
00h
20Ch
1/27000
1/27450
00h
107h∗1
00h
20Bh
1/10000
1/10000
01h
20Ch
1/60
1/60∗2
1/50∗2
00h
209h
1/4500
1/4403
01h
1D8h
00h
205h
1/2000
1/2077
02h
20Ch
00h
1FDh
1/1000
1/1010
07h
18Bh
00h
1EDh
1/500
1/498
09h
109h
00h
1CEh
1/250
1/251
00h
0D2h
00h
18Fh
1/125
1/125
00h
083h
00h
16Fh
1/100
1/100
00h
000h
1/30∗2
1/8∗2
1/6∗2
1/50∗3
1/40∗3
1/30∗3
1/60
1/50
1/30
1/8
1/6
1/50
1/40
1/30
∗1 One XSUB pulse is generated for odd fields and two for even fields.
∗2 These are the settings during monitoring drive mode.
∗3 These can only be specified during recording drive mode.
Note) Input prohibited data:
Monitoring drive mode
Recording drive mode and monitoring drive mode
000h to 106h
20Dh to 3FFh
[HTSG control mode]
During this mode, the data from D18 to D35 is invalid. The shutter speed is the value obtained by adding
the shutter speed specified in the preceding vertical interval to the vertical period during which XSG1 (and
XSG2) is stopped as shown in the figure.
FRI
XSG1
XSUB
Vck
SMD
01
11
WEN
During HTSG control mode
– 15 –
01
CXD2452R
D48 EXPOSE
0: No operation
1: XSUB for recording exposure is generated.
This control specification is such that one XSUB pulse is always generated during the horizontal interval
immediately following the readout portion even if the electronic shutter speed is set to 1/60s (SMD = 00). This
mode is closely related to D51 PSMT, so see D51 regarding the control.
D51 PSMT
0: Driving is controlled in accordance with monitoring drive mode under the assumption that vertical/horizontal sync
signals are input.
1: Driving is controlled in accordance with recording drive mode under the assumption that vertical/horizontal sync
signals are input.
See the timing charts for the vertical/horizontal sync signals in accordance with each mode.
Note that when switching from monitoring drive to recording drive mode, the pixels decimated thus far must be
cleaned.
Concretely, this operation is supported by generating XSUB, but the CXD2452R facilitates this control by
using D48 EXPOSE. (See the figure.)
FRI
XSG1
XSUB
Exposure time
WEN
SMD
00
00
00
00
EXPOSE
0
1
0
0
PSMT
0
0
1
0
Mode
Monitoring
Monitoring
Recording
Monitoring
Image of switching from monitoring drive mode to recording drive mode
D52 SSGSEL
0: Internal SSG functions are stopped.
1: Internal SSG functions operate, and FRO and HRO are generated.
When generation is stopped, these pulses are fixed low.
D53 WENSEL
0: WEN is generated.
1: WEN generation is stopped.
When generation is stopped, operation is the same as for D52 SSGSEL.
– 16 –
CXD2452R
D54 CLPSEL
0: XCPOB generation is stopped.
1: XCPOB is generated.
When generation is stopped, operation is the same as for D52 SSGSEL.
D55 IDSEL
0: ID generation is stopped.
1: ID is generated.
When generation is stopped, operation is the same as for D52 SSGSEL.
D56 HMCKSEL
0: 1/2MCK generation is stopped.
1: 1/2MCK is generated.
When generation is stopped, operation is the same as for D52 SSGSEL.
D57 TMCKSEL
0: 3/2MCK is generated.
1: 3/2MCK generation is stopped.
When generation is stopped, operation is the same as for D52 SSGSEL.
D58 HMCKREV
0: 1/2MCK reset when positive polarity.
1: 1/2MCK reset when negative polarity.
D59 HMCKREV
0: 3/2MCK reset when negative polarity.
1: 3/2MCK reset when positive polarity.
D60 to D61 DSG
The CXD2452R can stop control to the CCD pulses and pulses for the sample-and-hold and analog/digital
conversion ICs by setting the DSGAT pin low. Conversely, when the DSGAT pin is set high, the controlled
pulses can be switched as follows using the serial interface data.
D61
D60
Operating mode
0
0
No control performed
0
1
CCD pulse control
1
0
Sample-and-hold and analog/digital conversion IC pulse control
1
1
CCD pulse and sample-and-hold and analog/digital conversion IC pulse control
Here, CCD pulses refer to the H1, H2, RG, XV1, XV2, XV3, XSUB, XSG1 and XSG2 pulses. Sample-and-hold
and analog/digital conversion IC pulses refer to the XSHP, XSHD, XRS, PBLK, XCLPOB, XCLPDM and CLD
pulses.
See 7) Output timing characteristics using DSGAT of "AC Characteristics" for the stop control status of each
pulse.
– 17 –
CXD2452R
D62 to D63 STB
This switches the operating mode as shown below. However, the IC pin status control bit is loaded to the
CXD2452R and controlled immediately at the rise of the SEN input.
Operating mode
D63
D62
Symbol
X
0
CAMERA
0
1
SLEEP
Normal operation mode
Sleep mode∗1
1
1
STNBY
Standby mode
∗1 Mode for the status which does not require CCD drive when playing back recorded data within the system.
The pin status during each mode is shown in the table below.
Pin
Symbol
CAMERA
SLEEP
STNBY
Pin
ACT
ACT
ACT
25
RST
26
VDD6
Symbol
CAMERA
SLEEP
STNBY
ACT
ACT
ACT
1
3MCK
2
Vss1
3
WEN
ACT
L
L
27
SSI
ACT
ACT
ACT
4
ID
ACT
L
L
28
SSK
ACT
ACT
ACT
5
TEST
—
29
SEN
ACT
ACT
ACT
6
VDD1
—
30
EBCKSM
ACT
ACT
ACT
7
XCLPOB
31
FRO
ACT
ACT
L
8
VDD2
32
HRO
ACT
ACT
L
9
RG
33
HRI
ACT
ACT
ACT
10
Vss2
—
34
FRI
ACT
ACT
ACT
11
Vss3
—
35
CLD
ACT
L
L
12
H1
ACT
L
L
36
VSS5
13
H2
ACT
L
L
37
DSGAT
ACT
ACT
ACT
14
VDD3
38
MCK
ACT
ACT
L
15
XCLPDM
39
Vss6
16
VDD4
40
XSUB
ACT
L
L
17
XSHP
ACT
L
L
41
XV3
ACT
L
L
18
XSHD
ACT
L
L
42
XSG2
ACT
L
L
19
XRS
ACT
L
L
43
XSG1
ACT
L
L
20
Vss4
44
XV2
ACT
L
L
21
PBLK
ACT
L
L
45
VDD7
22
1/2MCK
ACT
L
L
46
XV1
ACT
L
L
23
3/2MCK
ACT
ACT
L
47
OSCO
ACT
ACT
ACT
24
VDD5
48
OSCI
ACT
ACT
ACT
—
ACT
L
L
—
ACT
L
L
—
ACT
L
L
—
—
—
—
—
—
—
Note) ACT means that the circuit is operating. L indicates a low output level in the controlled status.
– 18 –
CXD2452R
D64 to D71 CHKSUM
This is the check sum bit. Apply the data shown below.
+)
MSB
D07
D15
D23
D31
D39
D47
D55
D63
D71
0
D06
D14
D22
D30
D38
D46
D54
D62
D70
0
D05
D13
D21
D29
D37
D45
D53
D61
D69
0
D04
D12
D20
D28
D36
D44
D52
D60
D68
0
D03
D11
D19
D27
D35
D43
D51
D59
D67
0
D02
D10
D18
D26
D34
D42
D50
D58
D66
0
D01
D09
D17
D25
D33
D41
D49
D57
D65
0
LSB
D00
D08
D16
D24
D32
D40
D48
D56
D64
0
– 19 –
→ CHKSUM
→ Reflected when the total is 0.
HRI
FRI
– 20 –
WEN
ID
XCLPDM
XCLPOB
PBLK
CCD OUT
XV3
XV2
XV1
XSUB
XSG2
1
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
R B R B R B R B
490491492493494 1
B R B R B
2
MODE (Base oscillation frequency: 2340fH)
Recording drive mode
525
1
ICX098AK
Applicable CCD image sensor
1
2
3
4
5
6
7
8
1
R
from the fall of FRI.
∗ Note that R and B of CCDOUT indicate lines containing these components, and do not mean the lead pixel component of that line.
∗ The number of XSUB pulses is determined by the serial interface data. This chart shows the case where Shut.HD = 20Ch and XSUB pulses are generated over the entire horizontal interval.
∗ In addition to the phase relationship between FRI and HRI shown above, the phases may also be offset by 1/2 horizontal interval. In any case, the readout interval is the 9th HRI fall counted
525
Vertical Direction Timing Chart
XSG1
Chart-1
CXD2452R
– 21 –
WEN
ID
XCLPDM
XCLPOB
PBLK
CCD OUT
XV3
XV2
XV1
XSUB
XSG2
XSG1
HRI
FRI
Chart-2
1
1
2
5
6
1
2
5
6
9 10 13 14 17 18 21 22 25 26 29
R B R B R B R B R B R B R B R
262
ICX098AK
466469470473474 477478 481482485486489490 493494
1
2
5
Applicable CCD image sensor
B R B R B R B R B R B R B R B
MODE (Base oscillation frequency: 2340fH)
Monitoring drive mode
6
1
2
5
6
9 10 13 14
R B R B R B R B
∗ The number of XSUB pulses is determined by the serial interface data. This chart shows the case where Shut.HD = 20Ch and XSUB pulses are generated over the entire horizontal interval.
∗ Note that R and B of CCDOUT indicate lines containing these component, and do not mean the lead pixel component of that line.
482 485486489490493494
B R B R B R B
525
Vertical Direction Timing Chart
CXD2452R
– 22 –
WEN
ID
XCLPDM
XCLPOB
PBLK
RG
XSUB
XSG2
XSG1
XV3
XV2
XV1
H1
MCK
HRI
Chart-3
40
56
68
68
68
80
81
92
104
104
100
118
116
129
129
G G
R R R
550
G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
ICX098AK
Applicable CCD image sensor
∗ The HRI fall interval should be between 3.6 to 9.4µs. This chart shows an interval of 78ck (6.3µs).
∗ XSUB is output at the timing shown above when specified by the serial interface data.
∗ The ID transition timing is synchronized with the fall of XV3.
∗ WEN is output during the horizontal interval shown in Chart-1. The transition timing is the same as that for ID.
∗ R, G and B of H1 indicate the output pixel color. In addition to the lines starting from R and G shown above, there are also lines starting from G and B.
21
44
44
43
50
MODE (Base oscillation frequency: 2340fH)
Recording drive mode
∗ The HRI of this chart is equivalent to HRI' of Chart-7. This HRI indicates a timing that the CXD2452R takes in actually.
∗ The numbers at the output pulse transition points indicate the count at the MCK (780fH) rise from the fall of HRI.
B B B B B B B B B
G G G G G G G G G G
0
Horizontal Direction Timing Chart
CXD2452R
HRI
– 23 –
WEN
ID
XCLPDM
XCLPOB
PBLK
RG
XSUB
XSG2
XSG1
XV3
XV2
XV1
H1
MCK
Chart-4
40
56
68
68
68
80
81
92
104
104
100
118
116
116
129
∗ The HRI fall interval should be between 3.6 to 9.4µs. This chart shows an interval of 78ck (6.3µs).
∗ XSUB is output at the timing shown above when specified by the serial interface data.
∗ The ID transition timing is synchronized with the fall of XV3. ID is reset low at this timing during the readout horizontal interval.
∗ WEN is output during the horizontal interval shown in Chart-1. The transition timing is the same as that for ID.
21
44
43
50
MODE (Base oscillation frequency: 2340fH)
Recording drive mode (readout portion)
∗ The HRI of this chart is equivalent to HRI' of Chart-7. This HRI indicates a timing that the CXD2452R takes in actually.
∗ The numbers at the output pulse transition points indicate the count at the MCK (780fH) rise from the fall of HRI.
0
Horizontal Direction Timing Chart
520
520
521
ICX098AK
551
551
550
Applicable CCD image sensor
CXD2452R
– 24 –
WEN
ID
XCLPDM
XCLPOB
PBLK
RG
XSUB
XSG2
XSG1
XV3
XV2
XV1
H1
MCK
HRI
Chart-5
21
40
44
44
43
50
50
58
62
68
74
80
81
86
92
92
92
98
104
110
104
100
118
116
129
129
G G
R R R
MODE (Base oscillation frequency: 2340fH)
Monitoring drive mode
550
G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
ICX098AK
Applicable CCD image sensor
∗ The HRI of this chart is equivalent to HRI' of Chart-7. This HRI indicates a timing that the CXD2452R takes in actually.
∗ The numbers at the output pulse transition points indicate the count at the MCK (780fH) rise from the fall of HRI.
∗ The HRI fall interval should be between 3.6 to 9.4µs. This chart shows an interval of 78ck (6.3µs).
∗ XSUB is output at the timing shown above when specified by the serial interface data.
∗ The ID transition timing is synchronized with the fall of XV3.
∗ WEN is output during the horizontal interval shown in Chart-2. The transition timing is the same as that for ID.
∗ R, G and B of H1 indicate the output pixel color. In addition to the lines starting from R and G shown above, there are also lines starting from G and B.
B B B B B B B B B
G G G G G G G G G G
0
Horizontal Direction Timing Chart
CXD2452R
HRI
– 25 –
WEN
ID
XCLPDM
XCLPOB
PBLK
RG
XSUB
XSG2
XSG1
XV3
XV2
XV1
H1
MCK
Chart-6
40
50
58
62
68
74
81
80
86
92
92
92
98
104
110
104
100
118
116
116
129
∗ The HRI fall interval should be between 3.6 to 9.4µs. This chart shows an interval of 78ck (6.3µs).
∗ XSUB is output at the timing shown above when specified by the serial interface data.
∗ The ID transition timing is synchronized with the fall of XV3. ID is reset low at this timing during the readout horizontal interval.
∗ WEN is output during the horizontal interval shown in Chart-2. The transition timing is the same as that for ID.
21
44
43
50
MODE (Base oscillation frequency: 2340fH)
Monitoring drive mode (readout portion)
∗ The HRI of this chart is equivalent to HRI' of Chart-7. This HRI indicates a timing that the CXD2452R takes in actually.
∗ The numbers at the output pulse transition points indicate the count at the MCK (780fH) rise from the fall of HRI.
0
Horizontal Direction Timing Chart
520
521
ICX098AK
551
550
Applicable CCD image sensor
CXD2452R
– 26 –
XRS
XSHD
XSHP
RG
H2
H1
MCK
CLD
1/2MCK
3/2MCK
3MCK
HRI'
HRI
Chart-7
1
43
43
MODE (Base oscillation frequency: 2340fH)
ICX098AK
116
116
Applicable CCD image sensor
∗ The phase relationship of each pulse indicates logical position. For actual output waveform, delay is added respectively.
∗ HRI' indicates the HRI, which is a timing that taken in actually.
∗ 3/2MCK and 1/2MCK can inverse polarity according to each serial interface data. This chart indicates that 3/2 MCK is negative polarity; 1/2 MCK is positive polarity.
1
High-speed Phase Timing Chart
CXD2452R
CXD2452R
Application Circuit Block Diagram
XSG2
XSUB
CLD
38
41
34
43
33
42
32
SSG
40
3MCK
OSCO
1
47
48
25 37 5 30
31
1/2MCK
ID
WEN
MCK
FRI
HRI
HRO
Signal Processing Block
44
FRO
27 28 29
SSK
XSG1
TG
CXD2452R
3/2MCK
SEN
XV3
3
46
SSI
V-Dr
CXD1267AN
4
EBCKSM
XV2
22
9
TEST
XV1
23
13
DSGAT
RG
35
7
12
OSCI
RST
V1
V2a
V2b
V3
VSUB
H2
D0 to 9 10
A/D
CXD2311AR
XCLPOB
PBLK
XCLPDM
XRS
XSHD
17 18 19 21 15
H1
DRV OUT
VRT
VRB
S/H
CXA2006Q
CCD OUT
XSHP
CCD
ICX098AK
Controller
Note) When the CXD2311AR is used as A/D converter, CLD must be inversed.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 27 –
CXD2452R
Package Outline
Unit: mm
48PIN LQFP (PLASTIC)
9.0 ± 0.2
∗
7.0 ± 0.1
36
S
25
13
0.5 ± 0.2
B
A
48
(8.0)
24
37
(0.22)
12
1
+ 0.05
0.127 – 0.02
0.5
+ 0.08
0.18 – 0.03
+ 0.2
1.5 – 0.1
0.13 M
0.1
S
0.5 ± 0.2
(0.18)
0° to 10°
DETAIL B:SOLDER
DETAIL A
0.18 ± 0.03
0.127 ± 0.04
+ 0.08
0.18 – 0.03
(0.127)
+0.05
0.127 – 0.02
0.1 ± 0.1
DETAIL B:PALLADIUM
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
LQFP-48P-L01
LEAD TREATMENT
SOLDER/PALLADIUM
PLATING
EIAJ CODE
LQFP048-P-0707
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
0.2g
JEDEC CODE
– 28 –