HV9708 HV9808 32-Channel Serial To Parallel Converter With High Voltage Push-Pull Outputs Ordering Information Package Options Device 44 J-Lead Quad Plastic Chip Carrier Die in waffle pack HV9708 HV9708PJ HV9708X HV9808 HV9808PJ HV9808X Features General Description ❏ Processed with HVCMOS® technology The HV97 and HV98 are low-voltage serial to high-voltage parallel converters with push-pull outputs. These devices have been designed for use as drivers for AC-electroluminescent displays. They can also be used in any application requiring multiple output high-voltage current sourcing and sinking capabilities such as driving plasma panels, vacuum fluorescent displays, or large matrix LCD displays. The inputs are fully CMOS compatible. ❏ Output voltages up to 80V ❏ Low power level shifting ❏ Shift register speed 8MHz ❏ Latched data outputs ❏ Forward and reverse shifting options These devices consist of a 32-bit shift register, 32 latches, and control logic to perform the polarity select and blanking of the outputs. HVOUT1 is connected to the first stage of the shift register through the polarity and blanking logic. Data is shifted through the shift register on the logic low to high transition of the clock. The HV97 shifts data in the clockwise direction when viewed from the top of the package and the HV98 shifts in the counterclockwise direction. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register (HVOUT32). Operation of the shift register is not affected by the LE (latch enable), BL (blanking), or the POL (polarity) inputs. Transfer of data from the shift register to the latch occurs when the LE (latch enable) input is high. The data in the latch is stored when LE is low. ❏ Diode to VPP allows efficient power recovery ❏ 5V CMOS compatible inputs Absolute Maximum Ratings1 Supply voltage, VDD2 -0.5V to +7V Output voltage, VPP2 Logic input levels2 -0.5V to VDD +0.5V Ground current3 Continuous total power dissipation4 Operating temperature range Storage temperature range Lead temperature 1.6mm (1/16 inch) from case for 10 seconds VDD to +90V 1.5A 1200mW -40°C to +85°C -65°C to +150°C 260°C Notes: 1. Device will survive (but operation may not be specified or guaranteed) at these extremes. 2. All voltages are referenced to GND. 3. Duty cycle is limited by the total power dissipated in the package. 4. For operation above 25°C ambient, derate linearly to 70°C at 12mW/°C. 02/96/022 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. 1 HV9708/HV9808 Electrical Characteristics (VPP = 60V, VDD = 5V, TA =25°C) DC Characteristics Symbol Parameter Min Max Units Conditions IPP VPP Supply Current 100 µA HVOUT outputs HIGH to LOW IDDQ IDD Supply Current (Quiescent) 100 µA All inputs = VDD or GND IDD IDD Supply Current (Operating) 15 mA VDD = VDD max, fCLK = 8 MHz VOH (Data) Shift Register Output Voltage VOL (Data) Shift Register Output Voltage IIH VDD-0.5 V IO = -100µA 0.5 V IO = 100µA Current Leakage, any input 1 µA Input = VDD IIL Current Leakage, any input -1 µA Input = GND VOC HVOUT Output Clamp Diode Voltage -1.5 V IOC = -5mA VOH HVOUT Output when Sourcing V IOH = -20mA, 0 to 70°C VOL HVOUT Output when Sinking V IOL = 5mA, 0 to 70°C 52 4 AC Characteristics Symbol Parameter Min Max Units 8 MHz Conditions fCLK Clock Frequency tWL or tWH Clock width, HIGH or LOW 62 ns tSU Setup time before CLK rises 25 ns tH Hold time after CLK rises 10 ns tDLH (Data) Data Output Delay after L to H CLK 110 ns CL = 15pF tDHL (Data) Data Output Delay after H to L CLK 110 ns CL = 15pF tDLE LE Delay after L to H CLK 50 ns tWLE Width of LE Pulse 50 ns tSLE LE Setup Time before L to H CLK 50 ns tON Delay from LE to HVOUT, L to H 500 ns tOFF Delay from LE to HVOUT, H to L 500 ns Recommended Operating Conditions Symbol Parameter Min Max Units VDD Logic Voltage Supply 4.5 5.5 V VPP High Voltage Supply 8.0 80 V VIH Input HIGH Voltage VDD-0.5 VDD V VIL Input LOW Voltage 0 0.5 V fCLK Clock Frequency 0 8 MHz TA Operating free-air temperature -40 +85 °C Notes: Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply VPP. Power-down sequence should be the reverse of the above. 5. The VPP should not drop below VDD or float during operations. 2 Comments HV9708/HV9808 Input and Output Equivalent Circuits VDD VDD VPP Data Out Input HVOUT GND GND GND Logic Data Output Logic Inputs High Voltage Outputs Switching Waveforms VIH Data Input 50% Data Valid 50% VIL tSU tH VIH Clock 50% 50% 50% tWL 50% VIL tWH VOH 50% VOL tDLH Data Out VOH 50% VOL tDHL Latch Enable VIH 50% 50% VOL tDLE tWLE tSLE 90% 10% HVOUT w/ S/R LOW VOH VOL tOFF HVOUT w/ S/R HIGH 10% tON 3 90% VOH VOL HV9708/HV9808 Functional Block Diagram VPP Polarity Blanking Latch Enable HVOUT1 Data Input Latch Clock HVOUT2 Latch 32-Bit Shift Register (Outputs 3 to 30 not shown) HVOUT31 Latch Data Out HVOUT32 Latch Function Table Inputs Function Outputs Shift Reg 1 2…32 HV Outputs 1 2…32 Data Out * Data CLK LE BL POL All on X X X L L * *…* H H…H * All off X X X L H * *…* L L…L * Invert mode X X L H L * *…* * *…* * H or L *…* * *…* * H or L ↑ L H H Load latches Load S/R X H or L ↑ H H * *…* * *…* * X H or L ↑ H L * *…* * *…* * Transparent latch mode L ↑ H H H L *…* L *…* * H ↑ H H H H *…* H *…* * Notes: H = high level, L = low level, X = irrelevant, ↑ = low-to-high transition. * = dependent on previous stage’s state before the last CLK or last LE high. 4 HV9708/HV9808 Pin Configurations Package Outline HV97 44 Pin J-Lead Package 39 38 37 36 35 34 33 32 31 30 29 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function HVOUT 17 HVOUT 16 HVOUT 15 HVOUT 14 HVOUT 13 HVOUT 12 HVOUT 11 HVOUT 10 HVOUT 9 HVOUT 8 HVOUT 7 HVOUT 6 HVOUT 5 HVOUT 4 HVOUT 3 HVOUT 2 HVOUT 1 Data Out NC NC Polarity Clock Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function GND VPP VDD Latch Enable Data In Blanking NC HVout 32 HVOUT 31 HVOUT 30 HVOUT 29 HVOUT 28 HVOUT 27 HVOUT 26 HVOUT 25 HVOUT 24 HVOUT 23 HVOUT 22 HVOUT 21 HVOUT 20 HVOUT 19 HVOUT 18 Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function GND VPP VDD Latch Enable Data In Blanking NC HVOUT 1 HVOUT 2 HVOUT 3 HVOUT 4 HVOUT 5 HVOUT 6 HVOUT 7 HVOUT 8 HVOUT 9 HVOUT 10 HVOUT 11 HVOUT 12 HVOUT 13 HVOUT 14 HVOUT 15 40 28 41 27 42 26 43 25 44 24 1 23 2 22 3 21 4 20 5 19 6 18 7 8 9 10 11 12 13 14 15 16 17 top view 44-pin J-Lead Package HV98 44 Pin J-Lead Package Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function HVOUT 16 HVOUT 17 HVOUT 18 HVOUT 19 HVOUT 20 HVOUT 21 HVOUT 22 HVOUT 23 HVOUT 24 HVOUT 25 HVOUT 26 HVOUT 27 HVOUT 28 HVOUT 29 HVOUT 30 HVOUT 31 HVOUT 32 Data Out NC NC Polarity Clock 02/06//02 ©2002 Supertex Inc. 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