TI THS4120

THS4120
THS4121
www.ti.com
SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
HIGH-SPEED FULLY DIFFERENTIAL I/O AMPLIFIERS
FEATURES
KEY APPLICATIONS
•
•
•
•
High Performance
– 100 MHz, –3 dB Bandwidth
– 50 V/µs Slew Rate
– 75 dB Total Harmonic Distortion at 1 MHz
(VO = 2 VPP)
– 5.4 nV/√Hz Input-Referred Noise (10 kHz)
Differential Input/Differential Output
– Balanced Outputs Reject Common-Mode
Noise
– Differential Reduced Second Harmonic
Distortion
Power Supply Range
– VDD = 3.3 V
Simple Single-Ended To Differential
Conversion
Differential ADC Driver/Differential
Antialiasing
Differential Transmitter and Receiver
Output Level Shifter
•
•
•
THS4121
D, DGN, OR DGK PACKAGE
(TOP VIEW)
THS4120
D, DGN, OR DGK PACKAGE
(TOP VIEW)
VIN−
VOCM
VDD
VOUT+
1
8
2
7
3
6
4
5
VIN−
VOCM
VDD
VOUT+
VIN+
PD
GND
VOUT−
1
8
2
7
3
6
4
5
VIN+
NC
GND
VOUT−
DESCRIPTION
The THS412x is one in a family of fully differential-input, differential-output devices fabricated using
Texas Instruments' state-of-the-art submicron CMOS
process.
The THS412x consists of a true fully-differential
signal path from input to output. This results in
excellent common-mode noise rejection and
improved total harmonic distortion.
HIGH-SPEED DIFFERENTIAL I/O FAMILY
(1)
DEVICE
NUMBER OF
CHANNELS
POWERDOWN
THS4120 (1)
1
Yes
THS4121
1
–
For proper functiionality, an external 10-kΩ pullup resistor is
required between the PD pin and the positive supply.
RELATED DEVICES
(1)
DEVICE (1)
DESCRIPTION
SINGLE SUPPLY
VOLTAGE RANGE
SPLIT SUPPLY
VOLTAGE RANGE
THS413x
150 MHz, 51 V/µs, 1.3 nV/√Hz
5 V to 30 V
±2.5 to ±15
THS414x
160 MHz, 450 V/µs, 6.5 nV/√Hz
5 V to 30 V
±2.5 to ±15
THS415x
150 MHz, 650 V/µs, 7.6 nV/√Hz
5 V to 30 V
±2.5 to ±15
See the TI Web site for additional high-speed amplifier devices.
TYPICAL A/D APPLICATION CIRCUIT
VDD
3.3 V
VIN
VOCM
−
+
AIN
+
−
AIN
AVDD
AVSS
DVDD
Vref
DIGITAL
OUTPUT
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2004, Texas Instruments Incorporated
THS4120
THS4121
www.ti.com
SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
MSOP PowerPAD™
SMALL OUTLINE(D)
0°C to 70°C
–40°C to 85°C
EVALUATION
MODULES
MSOP
(DGN)
SYMBOL
(DGK)
THS4120CD
THS4120CDGN
ARL
THS4120CDGK
SYMBOL
ATZ
THS4120EVM
THS4121CD
THS4121CDGN
ASB
THS4121CDGK
ATO
THS4121EVM
THS4120ID
THS4120IDGN
ARM
THS4120IDGK
ARN
–
THS4121ID
THS4121IDGN
ASC
THS4121IDGK
ASN
–
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
Supply voltage, GND to VDD
3.6 V
±VDD
VI
Input voltage
IO
Output current (sink)
VID
Differential input voltage
(2)
110 mA
±VDD
Continuous total power dissipation
See Dissipation Rating Table
TJ
Maximum junction temperature (3)
150°C
TJ
Maximum junction temperature, continuous operation, long-term reliability (4)
TA
Operating free-air temperature
Tstg
Storage Temperature
125°C
C suffix
0°C to 70°C
I suffix
–40°C to 85°C
–65°C to 150°C
Lead temperature 1,6 mm (1/16 Inch) from case for 10 seconds
ESD ratings
(1)
(2)
(3)
(4)
300°C
HBM
4000 V
CDM
1500 V
MM
200 V
Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The THS412x may incorporate a PowerPad™ on the underside of the chip. This acts as a heatsink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature
which could permanently damage the device. See TI technical brief SLMA002 and SLMA004 for more information about utilizing the
PowerPad™ thermally enhanced package.
The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
DISSIPATION RATING TABLE
(1)
(2)
2
POWER RATING (2)
PACKAGE
θJA (1) (°C/W)
θJC (°C/W)
TA = 25°C
TA = 85°C
D
97.5
38.3
1.02 W
410 mW
DGN
58.4
4.7
1.71 W
685 mW
DGK
260
54.2
385 mW
154 mW
This data was taken using the JEDEC standard High-K test PCB.
Power rating is determined with a junction temperature of 125°C. This is the point where distortion
starts to substantially increase. Thermal management of the final PCB should strive to keep the
junction temperature at or below 125°C for best performance and long-term reliability.
THS4120
THS4121
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SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
RECOMMENDED OPERATING CONDITIONS
Split supply
VDD
Supply voltage
TA
Operating free-air temperature
Single supply
C suffix
I suffix
MIN
TYP
MAX
±1.5
±1.65
±1.75
3
3.3
3.5
0
70
–40
85
UNIT
V
°C
ELECTRICAL CHARACTERISTICS
VDD = 3.3 V, RL = 800 Ω, TA = 25°C (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC PERFORMANCE
BW
Small-signal bandwidth (–3 dB)
VDD = 3.3 V,
Gain = 1, Rf = 200 Ω
SR
Slew rate (2)
VDD = 3.3 V,
Gain = 1
Settling time to 0.1%
ts
Settling time to 0.01%
100
MHz
55
V/µs
60
Differential step voltage = 2 VPP, Gain = 1
ns
292
DISTORTION PERFORMANCE
THD
Total harmonic distortion
Differential input, differential output
Gain = 1, Rf = 200 Ω, RL = 800 Ω, VO = 2 VPP
VDD = 3.3 V,
f = 1 MHz
–75
dB
THD
Total harmonic distortion
Differential input, differential output
Gain = 1, Rf = 200 Ω, RL = 800 Ω, VO = 4 VPP
VDD = 3.3 V,
f = 1 MHz
–66
dB
Spurious free dynamic range (SFDR)
Differential input, differential output, VO = 4 VPP
Rf = 200 Ω,
f = 1 MHz
–69
dB
Third intermodulation distortion
VI = 0.071 VRMS
Gain = 1, f = 10 MHz
–75
dBc
NOISE PERFORMANCE
Vn
Input voltage noise
f = 10 kHz
5.4
nV/√Hz
In
Input current noise
f = 10 kHz
1
fA/√Hz
DC PERFORMANCE
Open-loop gain
Input offset voltage
VS
Input offset voltage, referred to VOCM
Offset voltage drift
IIB
Input bias current
IOS
Input offset current
Current offset drift
(1)
(2)
TA = 25°C
TA = full range
60
66
dB
66
TA = 25°C
3
TA = full range
4
9
TA = 25°C
5
13
TA = full range
TA = full range
TA = full range
TA = full range
8
mV
14
25
µV/°C
1.2
pA
100
5
fA
fA/°C
The full range temperature is 0°C to 70°C for the C suffix, and –40°C to 85°C for the I suffix.
Slew rate is measured differentially from an output level range of 25% to 75%.
3
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THS4121
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SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS (Continued)
VDD = 3.3 V, RL = 800 Ω, TA = 25°C (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CHARACTERISTICS
CMRR Common-mode rejection ratio
TA = full range
VICR
Common-mode input voltage range
TA = full range
ri
Input resistance (dc level)
Measured into each input terminal
Ci
Input capacitance, closed loop
ro
Output resistance
64
96
dB
0.65 to
VDD - 0.1
0.35
to
VDD
V
820
MΩ
3
pF
1
Ω
See Figure 16
OUTPUT CHARACTERISTICS
VOH
High-level output Voltage
VIC = VDD/2, VDD = 3.3 V,
TA = 25°C
3.05
3.15
V
VOL
Low-level output Voltage
VIC = VDD/2, VDD = 3.3 V,
TA = 25°C
0.25
0.15
V
IO
Output current (sink), RL = 7 Ω
VDD = 3.3 V,
TA = 25°C
80
100
mA
IO
Output current (source), RL = 7 Ω
VDD = 3.3 V,
TA = 25°C
20
25
mA
POWER SUPPLY
VDD
Supply voltage range
Single supply
IDD
Quiescent current (per amplifier)
VDD = 3.3 V
PSRR
Power supply rejection ratio
TA = 25°C
3.3
TA = 25°C
11
V
13.5
TA = full range
16
68
85
mA
dB
POWER-DOWN CHARACTERISTICS (THS4120 ONLY)
Power-down voltage level (2)
Power-down quiescent current
ton
Turn-on time delay
toff
Turn-off time delay
zo
Output impedance
(1)
(2)
4
Enable
>1.4
Power-down
<1.2
TA = 25°C
120
TA = full range
130
50% of final supply current value
f = 1 MHz
4.8
V
µA
µs
3
ns
1
kΩ
The full range temperature is 0°C to 70°C for the C suffix, and –40°C to 85°C for the I suffix.
For detail information on the power-down circuit, see the power-down section in the application section of this data sheet.
THS4120
THS4121
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SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Small-signal frequency response
1
SR
Slew rate
2
THD
Total harmonic distortion
vs Frequency
4
vs Frequency
Harmonic distortion
VO
3
vs Output voltage
5, 6, 7
vs Output voltage
8, 9
Third intermodulation distortion
vs Output voltage
10
Output voltage
vs Load resistance
11
Settling time
12
Vn
Voltage noise
vs Frequency
13
VOO
Output offset voltage
vs Common-mode input voltage
14
CMMR
Common-mode rejection ratio
vs Frequency
15
zos
Single-ended output impedance (closed loop)
vs Frequency
16
zo
Single-ended (VOCM) input impedance
vs Frequency
17
SMALL-SIGNAL FREQUENCY RESPONSE
SLEW RATE
2
1.5
Rf = 390 Ω
Falling Edge
VO − Output Voltage − V
Rf = 200 Ω
0
Gain − dB
1
Rf = 270 Ω
1
Rf = 150 Ω
−1
−2
−3
1M
0
−0.5
−1
G=1
VI = 22.5 mVRMS
VDD = 3.3 V
−4
100 k
VDD = 3.3 V,
VO = 2 VPP,
TA= 25°C
G=1
RL = 800 Ω
0.5
Rising Edge
−1.5
10 M
f − Frequency − Hz
Figure 1.
100 M
1G
0
20
40
t − Time − ns
60
80
Figure 2.
5
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THS4121
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SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
TOTAL HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−50
−40
Single−Ended Input /
Differential Output
−50
−60
−70
Differential Input/
Differential Output
−40
Harmonic Distortion − dB
−50
−60
1M
f − Frequency − Hz
−60
Differential Input /
Differential Output
−70
−80
10 M
0
1
2
3
VO − Output Voltage − V
Figure 4.
THS4121
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
THS4121
HARMONIC DISTORTION
vs
FREQUENCY
−30
−40
5th_HD
−50
2nd_HD
3rd_HD
−80
−90
3rd_HD
−100
VDD = 3.3 V,
VO = 4 VPP,
RL = 800 Ω,
Rf = 200 Ω,
G=1
−60
4
5
3rd_HD
2nd_HD
−70
−80
−90
5th_HD
4th_HD
−100
−110
4th_HD
−120
100 k
Single Input /
Differential Output
Figure 3.
VDD = 3.3 V,
VO = 2 VPP,
RL = 800 Ω,
Rf = 270 Ω,
G=1
−70
VDD = 3.3 V,
f = 1 MHz
Rf = 200 Ω,
RL = 800 Ω
−90
−80
100 k
−110
Differential Input /
Differential Output
1M
f − Frequency − Hz
Figure 5.
6
THD − Total Harmonic Distortion − dB
−30
VDD = 3.3 V,
VO = 4 VPP
Rf = 200 Ω,
RL = 800 Ω
G=1
Harmonic Distortion − dB
THD − Total Harmonic Distortion − dB
−20
10 M
−120
100 k
Differential Input /
Differential Output
1M
f − Frequency − Hz
Figure 6.
10 M
THS4120
THS4121
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SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
THS4121
HARMONIC DISTORTION
vs
FREQUENCY
−20
−60
VDD = 3.3 V,
VO = 4 VPP,
RL = 800 Ω,
Rf = 200 Ω,
G=1
−40
−70
Harmonic Distortion − dB
−30
Harmonic Distortion − dB
THS4121
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
2nd_HD
−50
3rd_HD
−60
−70
5th_HD
−80
4th_HD
−90
VDD = 3.3 V,
f = 1 MHz,
RL = 800 Ω,
Rf = 200 Ω,
G=1
−80
2nd_HD
3rd_HD
−90
−100
−110
Differential Input /
Differential Output
Single Input / Differential Output
−100
100 k
Harmonic Distortion − dB
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Figure 8.
THS4121
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
THIRD INTERMODULALTION DISTORTION
vs
OUTPUT VOLTAGE
−80
−10
2nd_HD
3rd_HD
−90
4th_HD
−100
5
VO − Output Voltage − V
Figure 7.
VDD = 3.3 V,
f = 1 MHz,
RL = 800 Ω,
Rf = 200 Ω,
G=1
−70
−120
0
10 M
Third Intermodulation Distortion − dBc
−60
1M
f − Frequency − Hz
5th_HD
−110
−20
VDD = 3.3 V,
f = 1 MHz
Rf = 270 Ω,
RL = 800 Ω
−30
f = 10 MHz
−40
−50
−60
f = 5 MHz
−70
−80
Single Input / Differential Output
−120
0
0.5
1
1.5
2
2.5
3
VO − Output Voltage − V
Figure 9.
3.5
4
4.5
−90
−25
−20
−15
−10
−5
0
5
10
VO − Output Voltage − V
Figure 10.
7
THS4120
THS4121
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SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
THS4121
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
SETTLING TIME
1.03
2
VDD = 3.3 V,
VO = 2 VPP,
RF = 330 Ω,
RL = 800 Ω,
G=1
VDD = 3.3 V
1.5
1.02
VO − Output Voltage − V
VO − Output Voltage − V
Sink
1
0.5
0
−0.5
−1
1.01
1
0.99
0.98
Settling Time,
1% = 40 ns,
0.1% = 60 ns,
0.01% = 292 ns
0.97
Source
−1.5
0.96
−2
100
1k
RL − Load Resistance − Ω
0.95
10k
100
200
300
t − Time − ns
400
Figure 11.
Figure 12.
VOLTAGE NOISE
vs
FREQUENCY
OUTPUT OFFSETE VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
140
500
0.1
120
VOO − Output Offset Voltage − V
V n − Voltage Noise − nV/ Hz
0
100
80
60
40
0
−0.1
−0.2
−0.3
20
0
−0.4
1
10
100
1k
f − Frequency − Hz
Figure 13.
8
10 k
100 k
0
0.5
1
1.5
2
2.5
V IC − Common-Mode Input Voltage − V
Figure 14.
3
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THS4121
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SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
THS4121
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
THS4121
SINGLE-ENDED OUTPUT IMPEDANCE
vs
FREQUENCY
z os − Single-Ended Output Impedance − Ω
−60
1000
VDD = 3.3 V,
Rf = 1 kΩ,
RL = 800 Ω,
G=1
−70
−80
−90
−100
−110
100 k
1M
10 M
VDD = 3.3 V,
VI = 5 dBm
G=1
100
10
1
100 k
100 M
f − Frequency − Hz
1M
10 M
f − Frequency − Hz
Figure 15.
Figure 16.
100 M
THS4121
SINGLE-ENDED (VOCM) INPUT IMPEDANCE
vs
FREQUENCY
1M
Z is − Single-Ended (VOCM ) Input Impedance − Ω
CMRR − Common-Mode Rejection Ratio − dB
−50
VDD = 3.3 V,
VI = −0.071 V(RMS)
100 k
10 k
1k
100
10
100 k
1M
100 M
10 M
f − Frequency − Hz
1G
Figure 17.
9
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SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
APPLICATION INFORMATION
RESISTOR MATCHING
Resistor matching is important in fully differential amplifiers. The balance of the output on the reference voltage
depends on matched ratios of the resistors. CMRR, PSRR, and cancellation of the second harmonic distortion
diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or better to
keep the performance optimized.
VOCM sets the dc level of the output signals. If no voltage is applied to the VOCM pin, it is set to the midrail voltage
internally defined as:
V DD
V
SS
2
(1)
In the differential mode, the VOCM on the two outputs cancel each other. Therefore, the output in the differential
mode is the same as the input with the gain of 1. VOCM has a high bandwidth capability up to the typical operation
range of the amplifier. For the prevention of noise going through the device, use a 0.1-µF capacitor on the VOCM
pin as a bypass capacitor. The following graph shows the simplified diagram of the THS412x.
VDD
Output Buffer
VIN-
x1
VOUT+
C
VIN+
Vcm Error
Amplifier
+
_
C
x1
VDD
30 kΩ
VSS
30 kΩ
VSS
VOCM
Figure 18. THS412x Simplified Diagram
R
VOUT-
Output Buffer
10
R
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SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
DATA CONVERTERS
Data converters are one of the most popular applications for the fully differential amplifiers.
Fully differential amplifiers can operate with a single supply. VOCM defaults to the midrail voltage, VDD/2. The
differential output may be fed into a data converter. This method eliminates the use of a transformer in the circuit.
If the ADC has a reference voltage output (Vref), then it is recommended to connect it directly to the VOCM of the
amplifier using a bypass capacitor for stability. For proper operation, the input common-mode voltage to the input
terminal of the amplifier should not exceed the common-mode input voltage range.
3.3 V
VDD
3.3 V
VIN
+
-
AIN1
-
+
AIN2
VOCM
0.1 µF
AVDD
DVDD
AVSS
Vref
Figure 19. Differential Amplifier Using a Single Supply
Some single-supply applications may require the input voltage to exceed the common-mode input voltage range.
In such cases, the following circuit configuration is suggested to bring the common-mode input voltage within the
specifications of the amplifier.
VDD
VCC
R(g)
VIN
Rf
RPU
VP
3.3 V
VOUT
+
-
-
+
VOCM
0.1 µF
R(g)
VDD
AIN1
AIN2
VOUT
RPU
VCC
AVDD
DVDD
AVSS
Vref
Rf
Figure 20. Circuit With Improved Common-Mode Input Voltage
The following equation is used to calculate RPU:
V –V
P
DD
R
PU
1
VIN – V P R V OUT – VP R1
(g)
f
(2)
11
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SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
DRIVING A CAPACITIVE LOAD
Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS412x has been internally compensated to maximize its bandwidth and
slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output decreases the device's phase margin leading to high-frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 21. A minimum value of 20 Ω should work well for most applications. For
example, in 50-Ω transmission systems, setting the series resistor value to 50 Ω both isolates any capacitance
loading and provides the proper line impedance matching at the source end.
Rf
20 Ω
Output
R(g)
THS412x
20 Ω
R(g)
Output
Rf
Figure 21. Driving a Capacitive Load
ACTIVE ANTIALIAS FILTERING
For signal conditioning in ADC applications, it is important to limit the input frequency to the ADC. Low-pass
filters can prevent the aliasing of the high-frequency noise with the frequency of operation. Figure 22 presents a
method by which the noise may be filtered in the THS412x. Proper ground referencing should be considered.
R2
C1
VDD
-
VIN-
VIN+
R(t)
VINVOCM
R3
VIC
C3
R4
VSS
C1
R2
Figure 22. Antialias Filtering
12
AVDD
VIN+
+
THS412x
+
C2
R1
VDD
C3
R3
R1
Vs
R4
DVDD
VOCM
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SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
The transfer function for this filter circuit is:
Rt
2R4 Rt
K
H (f) x
d
f 2 1 jf
1 j2πfR4RtC3
2R4 Rt –FSF x fc Q FSF x fc 1 2 x R2R3C1C2
1
FSF x fc and Q R3C1 R2C1 KR3C1
2π 2 x R2R3C1C2
Where K R2
R1
(3)
(4)
K sets the pass-band gain, fc is the cutoff frequency for the filter, FSF is a frequency scaling factor, and Q is the
quality factor.
FSF Re
2
|Im|
2
and Q Re
2
|Im|
2Re
2
(5)
Where Re is the real part, and Im is the imaginary part of the complex pole pair. Setting R2 = R, R3 = mR,
C1 = C, and C2 = nC results in:
2 x mn
1
FSF x fc and Q 1 m(1 K)
2πRC 2 x mn
(6)
Start by determining the ratios, m and n, required for the gain and Q of the filter type being designed, then select
C and calculate R for the desired fc.
13
THS4120
THS4121
www.ti.com
SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
PRINCIPLES OF OPERATION
THEORY OF OPERATION
The THS412x is a fully differential amplifier. Differential amplifiers are typically differential in/single out, whereas
fully differential amplifiers are differential in/differential out.
Differential Amplifier
Rf
R(g)
THS412x
Fully Differential Amplifier
VDD
_
_
VIN−
VIN+
+
VO+
+
+
R(g)
Rf
_
VO−
VOCM
GND
Figure 23. Differential Amplifier Versus a Fully Differential Amplifier
To understand the THS412x fully differential amplifiers, the definition for the pinouts of the amplifier are provided.
Input voltage definition
V
ID
Output voltage definition
V
Transfer function
V
VI – V I–
VO – VO–
OD
OD
V
Output common−mode voltage V
OC
V
ID
x A
V
IC
V
OC
VI
VI–
2
(7)
VO VO–
2
f
(8)
(9)
OCM
(10)
Differential Structure Rejects
Coupled Noise at the Input
Differential Structure Rejects
Coupled Noise at the Output
VDD
VINVIN+
Differential Structure Rejects
Coupled Noise at the Power Supply
_
+
+
_
VO+
VO-
VOCM
GND
Figure 24. Definition of the Fully Differential Amplifier
The following schematics depict the differences between the operation of the THS412x, fully differential amplifier,
in two different modes. Fully differential amplifiers can work with differential input or can be implemented as
single in/differential out.
14
THS4120
THS4121
www.ti.com
SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
PRINCIPLES OF OPERATION (continued)
Rf
VDD
R(g)
VINVs
VIN+
R(g)
Note: For proper operation, maintain
symmetry by setting
Rf1 = Rf2 = Rf and R(g)1 = R(g)2 = R(g)
⇒ A = Rf/R(g)
- +
VO+
+-
VO-
VOCM
GND
Rf
Figure 25. Amplifying Differential Signals
Rf
VIN-
R(g)
VDD
RECOMMENDED RESISTOR VALUES
- +
+-
VIN+
Vs
R(g)
VO+
GAIN
R(g) Ω
Rf Ω
VO-
1
150
150
VOCM
GND
Rf
Figure 26. Single In With Differential Out
If each output is measured independently, each output is one-half of the input signal when gain is 1. The
following equations express the transfer function for each output:
V 1 V
O
2 I
(11)
The second output is equal and opposite in sign:
V –1 V
O
2 I
(12)
Fully differential amplifiers may be viewed as two inverting amplifiers. In this case, the equation of an inverting
amplifier holds true for gain calculations. One advantage of fully differential amplifiers is that they offer twice as
much dynamic range compared to single-ended amplifiers. For example, a 1-VPP ADC can only support an input
signal of 1 VPP. If the output of the amplifier is 2 VPP, then it is not practical to feed a 2-VPP signal into the
targeted ADC. Using a fully differential amplifier enables the user to break down the output into two 1-VPP signals
with opposite signs and feed them into the differential input nodes of the ADC. In practice, the designer has been
able to feed a 2-V peak-to-peak signal into a 1-V differential ADC with the help of a fully differential amplifier. The
final result indicates twice as much dynamic range. Figure 27 illustrates the increase in dynamic range. The gain
factor should be considered in this scenario. The THS412x fully differential amplifier offers an improved CMRR
and PSRR due to its symmetrical input and output. Furthermore, second harmonic distortion is improved. Second
harmonics tend to cancel because of the symmetrical output.
15
THS4120
THS4121
www.ti.com
SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
PRINCIPLES OF OPERATION (continued)
a
VOD= 1-0 = 1
VDD
VINVIN+
_
+
+
_
VOCM
VSS
+1
VO+
0
VO-
+1
0
VOD = 0-1 = -1
b
Figure 27. Fully Differential Amplifier With Two 1-VPP Signals
CIRCUIT LAYOUT CONSIDERATIONS
To achieve the levels of high-frequency performance of the THS412x, follow proper printed-circuit board high
frequency design techniques. A general set of guidelines is given below. In addition, a THS412x evaluation board
is available to use as a guide for layout or for evaluating the device performance.
•
•
•
•
•
Ground planes - It is highly recommended that a ground plane be used on the board to provide all components with a
low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be
removed to minimize the stray capacitance.
Proper power supply decoupling - Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor on each
supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a
0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-µF
capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the
connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inch
between the device power terminals and the ceramic capacitors.
Sockets - Sockets are not recommended for high-speed operational amplifiers. The additional lead inductance in the
socket pins often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the
best implementation.
Short trace runs/compact part placements - Optimum high-frequency performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby
minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length
should be kept as short as possible. This helps to minimize stray capacitance at the input of the amplifier.
Surface-mount passive components - Using surface-mount passive components is recommended for high-frequency
amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components,
the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components
naturally leads to a more compact layout thereby minimizing both stray inductance and capacitance. If leaded
components are used, it is recommended that the lead lengths be kept as short as possible.
POWER-DOWN MODE
The THS4120 features a power-down pin (PD) which lowers the quiescent current from 11 mA down to 120 µA,
ideal for reducing system power. The power-down pin of the amplifier must be pulled high via a 10-kΩ pullup
resistor between the PD pin and the positive supply (see Figure 28) in the absence of an applied voltage, putting
the amplifier in the power-on mode of operation. To turn off (disable) the amplifier in an effort to conserve power,
the power-down pin can be driven towards the negative rail or ground. The threshold voltages for power-on and
power-down are relative to the supply rails and given in the specification tables. Above the Enable Threshold
Voltage, the device is on. Below the Disable Threshold Voltage, the device is off. Behavior in between these
threshold voltages is not specified.
Note that this power-down functionality is just that; the amplifier consumes less power in power-down mode. The
power-down mode is not intended to provide a high-impedance output. The power-down functionality is not
intended to allow use as a 3-state bus driver. When in power-down mode, the impedance looking back into the
output of the amplifier is dominated by the feedback and gain-setting resistors, but the output impedance of the
device itself varies depending on the voltage applied to the outputs.
The time delays associated with turning the device on and off are specified as the time it takes for the amplifier to
reach 50% of the nominal quiescent current. The enable time delay is in the order of microseconds due to the
amplifier moving in and out of the linear mode of operation.
16
THS4120
THS4121
www.ti.com
SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
PRINCIPLES OF OPERATION (continued)
3.3 V
PD
10 k
+
THS4120
_
VIN
VOCM
Figure 28.
Due to the similarity of the standard inverting amplifier configuration, the output impedance appears to be low
while in the power-down state. This is because the feedback resistor (Rf) and the gain resistor (R(g)) are still
connected to the circuit. Therefore, a current path is allowed between the input of the amplifier and the output of
the amplifier. An example of the closed-loop output impedance is shown in Figure 29.
zos − Single-Ended Output Impedance (in Power Down) − Ω
THS4120
SINGLE-ENDED OUTPUT IMPEDANCE
(IN POWER DOWN)
vs
FREQUENCY
10000
VCC = 3.3 V
1000
100
10
100 k
1M
10 M
100 M
f − Frequency − Hz
1G
Figure 29.
17
THS4120
THS4121
www.ti.com
SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004
GENERAL PowerPAD DESIGN CONSIDERATIONS (APPLICABLE TO DIFFERENTIAL AMPLIFIER
FAMILY)
The THS412x is available packaged in a thermally enhanced DGN package, which is a member of the
PowerPAD family of packages. This package is constructed using a downset leadframe on which the die is
mounted [see Figure 30(a) and Figure 30(b)]. This arrangement results in the leadframe being exposed as a
thermal pad on the underside of the package [see Figure 30(c)]. Because this thermal pad has direct thermal
contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from
the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat-dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of the
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
More complete details of the PowerPAD installation process and thermal management techniques can be found
in the Texas Instruments Technical Brief, PowerPAD Thermally Enhanced Package (SLMA002). This document
can be found at the TI Web site (www.ti.com) by searching on the key word PowerPAD. The document can also
be ordered through your local TI sales office. Refer to literature number SLMA002 when ordering.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
A.
Bottom View (c)
The thermal pad is electrically isolated from all terminals in the package.
Figure 30. Views of Thermally Enhanced DGN Package
18
THERMAL PAD MECHANICAL DATA
www.ti.com
DGN (S-PDSO-G8)
THERMAL INFORMATION
This PowerPAD™ package incorporates an exposed thermal pad that is designed to be attached directly to an
external heatsink. When the thermal pad is soldered directly to the printed circuit board (PCB), the PCB can be
used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to a
ground plane or special heatsink structure designed into the PCB. This design optimizes the heat transfer from
the integrated circuit (IC).
For additional information on the PowerPAD package and how to take advantage of its heat dissipating abilities,
refer to Technical Brief, PowerPAD Thermally Enhanced Package, Texas Instruments Literature No. SLMA002
and Application Brief, PowerPAD Made Easy , Texas Instruments Literature No. SLMA004. Both documents are
available at www.ti.com.
The exposed thermal pad dimensions for this package are shown in the following illustration.
8
5
Exposed Thermal Pad
1,73
MAX
1
4
1,78
MAX
Top View
NOTE: All linear dimensions are in millimeters
PPTD041
Exposed Thermal Pad Dimensions
PowerPAD is a trademark of Texas Instruments
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