TPD2EUSB30, TPD4EUSB30 www.ti.com SLVSAC2 – AUGUST 2010 2, 4-CHANNEL ESD SOLUTION FOR SUPER-SPEED (6 GBPS) USB 3.0 INTERFACE Check for Samples: TPD2EUSB30, TPD4EUSB30 FEATURES 1 • • • • • • • • Single and Dual-Pair Differential Lines to Protect the Differential Data and Clock Lines of the USB3.0, eSATA, or LVD Interface Flow-Through Pin Mapping for the High-Speed Lines Ensures Zero Additional Skew Due to Board Layout While Placing ESD-Protection Chip Near the Connector Supports Data Rates in Excess of 6 Gbps ESD Protection Meets or Exceeds IEC61000-4-2 (Level 4) Low Capacitance 0.05pF (IO to IO) 5-A Peak Pulse Current (per 8/20 ms Pulse) Industrial Temperature Range: –40°C to 85°C Space-Saving DRT, DQA Packages APPLICATIONS • • • • • Notebooks Set-Top Boxes DVD Players Media Players Portable Computers TPD2EUSB30DRTR PACKAGE (TOP VIEW) D+ 1 3 D– GND 2 TPD4EUSB30DQAR PACKAGE (TOP VIEW) D1+ 1 10 N.C. D1– 2 9 N.C. GND 3 8 GND D2+ 4 7 N.C. D2– 5 6 N.C. DESCRIPTION/ORDERING INFORMATION The TPD2EUSB30 and TPD4EUSB30 provide 2 and 4 channel ESD clamp circuits with flow-through pin mapping for ease of board layout. These devices have been designed to protect sensitive components which are connected to ultra high-speed data and transmission lines. The TPDxEUSB30 offer protection from stress caused by ESD (electrostatic discharge). These devices also offer 5 A (8/20 ms) peak pulse current ratings per IEC 61000-4-5 (lightning) specification. The monolithic silicon technology allows matching between the differential signal pairs. The differential 0.05-pF capacitance ensures that the signal distortion due to added ESD clamp remains minimal at high-speed differential data transmission. The TPD2EUSB30 and TPD4EUSB30 conform to IEC61000-4-2 (Level 4) ESD protection. The TPD2EUSB30 is offered in space saving DRT (1 mm × 1 mm) package. The TPD4EUSB30 is offered in space saving DQA (1 mm × 2.5 mm) package. The TPD2EUSB30 and TPD4EUSB30 are characterized for operation over ambient air temperature range of –40°C to 85°C. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated TPD2EUSB30, TPD4EUSB30 SLVSAC2 – AUGUST 2010 www.ti.com ORDERING INFORMATION PACKAGE (1) TA –40°C to 85°C (1) (2) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING SOT – DRT Tape and reel TPD2EUSB30DRTR 5PX SON – DQA Tape and reel TPD4EUSB30DQAR 66R Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. CIRCUIT DIAGRAMS TPD4EUSB30DQA Circuit D1+ D2+ D1D2- GND TPD2EUSB30DRT Circuit D– D+ GND TERMINAL FUNCTIONS TERMINAL DRT PIN NO. DQA PIN NO. Dx+, Dx– 1, 2 1,2, 4, 5 ESD port GND 3 3, 8 GND N.C. 2 TYPE NAME 6, 7, 9, 10 Submit Documentation Feedback DESCRIPTION High-speed ESD clamp, provides ESD protection to the high-speed differential data lines Ground Not normally connected Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPD2EUSB30, TPD4EUSB30 TPD2EUSB30, TPD4EUSB30 www.ti.com SLVSAC2 – AUGUST 2010 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) IO voltage tolerance D+, D– pins MIN MAX 0 6 UNIT TA Operating free-air temperature range –40 85 Tstg Storage temperature range –65 125 °C ESD protection (1) °C IEC 61000-4-2 Contact Discharge D+, D– pins ±8 kV IEC 61000-4-2 Air-Gap Discharge (TPD2EUSB30) D+, D– pins ±8 kV IEC 61000-4-2 Air-Gap Discharge (TPD4EUSB30) D+, D– pins ±9 kV Peak pulse current (tp = 8/20 ms) D+, D– pins 5 A Peak pulse power (tp = 8/20 ms) D+, D– pins 45 W Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VRWM Reverse stand-off voltage D+,D– pins to ground Vclamp Clamp voltage D+,D– pins to ground, IIO = 1 A IIO Current from IO port to supply pins VIO = 2.5 V, ID = 8 mA VD Diode forward voltage D+,D– pins, lower clamp diode, VIO = 2.5 V, ID = 8 mA Rdyn Dynamic resistance D+,D– pins I=1A CIO-IO Capacitance IO to IO D+,D– pins VIO = 2.5 V MIN 0.6 D+,D– pins (DRT) CIO-GND Capacitance IO to GND D1+, D1-, D2+, D2- (DQA ) VBR IIO = 1 mA Break-down voltage TYP MAX UNIT 5.5 V 8 V 0.01 0.1 mA 0.8 0.95 V 1 Ω 0.05 pF 0.7 VIO = 2.5 V Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPD2EUSB30, TPD4EUSB30 0.8 7 Submit Documentation Feedback pF V 3 TPD2EUSB30, TPD4EUSB30 SLVSAC2 – AUGUST 2010 www.ti.com TYPICAL OPERATING CHARACTERISTICS 1.20E-12 10 TA = 25°C 5 1.10E-12 Leakage Current (pA) Capacitnace (Farads) 0 1.00E-12 9.00E-13 DQA Package 8.00E-13 DRT Package 7.00E-13 –5 –10 –15 D– –20 D+ –25 –30 6.00E-13 VIO = 2.5 V –35 5.00E-13 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 –40 Figure 1. IO Capacitance vs IO Voltage 85 Figure 2. Leakage Current vs Temperature 6.0 Measured at one IO, the other IO open 5.5 55 25 Temperature (°C) –40 Voltage (V) 60 11 55 10 5.0 50 4.5 45 9 40 3.5 35 3.0 30 2.5 25 Current (A) 2.0 20 1.5 15 1.0 10 7 Current (A) 4.0 PPP (W) IPP (A) 8 6 5 4 3 2 Power (W) 5 0.5 1 0 0.0 5 0 10 15 20 25 30 Time (ms) 35 40 45 50 0 0 100 20 90 10 80 0 70 -10 60 -20 50 40 30 -70 0 -80 -10 -90 -20 -100 75 100 Time (ns) 125 150 175 Figure 5. IEC Clamping Waveforms (8 kV Contact) 4 Submit Documentation Feedback 25 30 35 40 -50 -60 50 20 Voltage (V) -40 10 25 15 -30 20 0 10 Figure 4. D+,D– Transmission Line Pulser Plot (100 ns Pulse, 10 ns Rise Time) Amplitude (V) Amplitude (V) Figure 3. Peak Pulse Waveforms 5 200 0 25 50 75 100 Time (ns) 125 150 175 200 Figure 6. IEC Clamping Waveforms (–8 kV Contact) Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPD2EUSB30, TPD4EUSB30 TPD2EUSB30, TPD4EUSB30 www.ti.com SLVSAC2 – AUGUST 2010 APPLICATION INFORMATION Layout Guide with TPDxEUSB30DRTR Refer to Figure 7, the TPD2EUSB30DRTR is offered in space saving DRT package. The DRT package is a 1mm* 1mm package with flow-through pin-mapping for the high-speed differential lines. The TPD4EUSB30DRTR is offered in space saving DQA package. The DQA is a 1mm* 2.5mm package with flow-through pin-mapping for the high-speed differential lines. It is recommended to place the package right next to the USB 3.0 connector. The GND pin should connected to GND plane of the board through a large VIA. If a dedicated GND plane is not present right underneath, it is recommended to route to the GND plane through a wide trace. The current associated with IEC ESD stress can be in the range of 30Amps or higher momentarily. A good, low impedance GND path ensures the system robustness against IEC ESD stress. The TPDxEUSB30 can provide system level ESD protection to the high-speed differential ports (>6 Gbps data rate). The flow-through package offers flexibility for board routing with traces up to 15 mills wide. It allows the differential signal pairs couple together right after they touch the ESD ports of the TPDxEUSB30. TX+ VBUS TXTPD2EUSB30DRTR D- USB 3.0 Host/ Controller 1-mm DGND GND D+ 8-mm D+ RX+ GND 1-mm RX- Three TPD2EUSB30 to Protect USB3.0 Class A connector (One Layer Routing) TPD4EUSB30 D1+ TX+ VBUS N.C. TXD1- N.C. GND D2+ N.C. D2- N.C. D- 2.5-mm GND USB 3.0 Host/ Controller GND D+ 8-mm RX+ GND RX- 1-mm One TPD4EUSB30 & One TPD2EUSB30 to Protect USB3.0 Class A connec tor (Two Layer Routing) Figure 7. Layout Guide with the TPDxEUSB30 at the USB3.0 Class A Connector TPDxEUSB30 Eye Pattern Test See Figure 9 for a demonstration of the TPDxEUSB30 performance the lab set-up. Figure 8 shows a lab board that was designed to demonstrate the degradation of the eye pattern quality with and without the TPD2EUSB30 in the USB 3.0 signal path. Figure 10 shows that there is only ~2 ps jitter penalty to the differential signal when the TPD2EUSB30 device was added in the signal path. Similar setup was employed to measure eye pattern for the TPD4EUSB30. Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPD2EUSB30, TPD4EUSB30 Submit Documentation Feedback 5 TPD2EUSB30, TPD4EUSB30 SLVSAC2 – AUGUST 2010 www.ti.com Eye Pattern Measurement Point Pattern Generator 36” Lossy Transmission Line USB3.0 Receiver PHY Figure 8. Measurement Setup to collect the Eye Pattern on a Reference Board with TPD2EUSB30 Eye Pattern Measurement Point Pattern Generator 36” Lossy Transmission Line TPD2EUSB30 USB3.0 Receiver PHY Figure 9. Measurement Setup to collect the Eye Pattern on a Reference Board with TPD2EUSB30 Figure 10. Lab Setup for the Eye-Pattern Measurement with TPDxEUSB30 6 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPD2EUSB30, TPD4EUSB30 TPD2EUSB30, TPD4EUSB30 www.ti.com SLVSAC2 – AUGUST 2010 Figure 11. Output Eye Diagram Without TPD2EUSB30 (Figure 8 Setup, 5 Gbps Data Rate) Figure 12. Output Eye Diagram with the TPD2EUSB30 (Figure 8 Setup, 5 Gbps Data Rate) Figure 13. Output Eye Diagram Without the TPD4EUSV30 (5 Gbps Data Rate) Figure 14. Output Eye Diagram with the TPD4EUSV30 (5 Gbps Data Rate) Figure 15. TPDxEUSV30 EVM – TPD4EUSB30 Side Figure 16. TPDxEUSV30 EVM – TPD2EUSB30 Side Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPD2EUSB30, TPD4EUSB30 Submit Documentation Feedback 7 PACKAGE OPTION ADDENDUM www.ti.com 25-Aug-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) TPD2EUSB30DRTR ACTIVE SOT DRT 3 3000 Green (RoHS & no Sb/Br) TPD4EUSB30DQAR PREVIEW SON DQA 10 3000 TBD Lead/ Ball Finish MSL Peak Temp Samples (Requires Login) CU NIPDAU Level-1-260C-UNLIM Call TI (3) Call TI Request Free Samples Samples Not Available (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPD2EUSB30DRTR Package Package Pins Type Drawing SOT DRT 3 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 180.0 8.4 Pack Materials-Page 1 1.16 B0 (mm) K0 (mm) P1 (mm) 1.16 0.63 4.0 W Pin1 (mm) Quadrant 8.0 Q3 PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPD2EUSB30DRTR SOT DRT 3 3000 202.0 201.0 28.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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