TI SN75LBC241DB

SN75LBC241
LOW-POWER LinBiCMOS MULTIPLE DRIVERS AND RECEIVERS
SLLS137E – MAY 1992 – REVISED JANUARY 1999
D
D
D
D
D
D
D
D
D
D
D
D
DB OR DW PACKAGE
(TOP VIEW)
Operates With Single 5-V Power Supply
Meets or Exceeds the Requirements of
TIA/EIA-232-F and ITU Recommendation
V.28
Improved Performance Replacement for
MAX241
Operates at Data Rates up to 100 kbit/s
Over a 3-m Cable
Low-Power Shutdown Mode . . . ≤1 µA Typ
LinBiCMOS Process Technology
Four Drivers and Five Receivers
±30-V Input Levels
3-State TTL/CMOS Receiver Outputs
±9-V Output Swing With a 5-V Supply
Applications
– TIA/EIA-232-F Interface
– Battery-Powered Systems
– Terminals
– Modems
– Computers
Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages
TOUT3
TOUT1
TOUT2
RIN2
ROUT2
TIN2
TIN1
ROUT1
RIN1
GND
VCC
C1+
VDD
C1–
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
TOUT4
RIN3
ROUT3
SHUTDOWN
EN
RIN4
ROUT4
TIN4
TIN3
ROUT5
RIN5
VSS
C2–
C2+
description
The SN75LBC241† is a low-power LinBiCMOS line-interface device containing four independent drivers and
five receivers. It is designed as a plug-in replacement for the Maxim MAX241. The SN75LBC241 provides a
capacitive-charge-pump voltage generator to produce RS-232 voltage levels from a 5-V supply. The
charge-pump oscillator frequency is 20 kHz. Each receiver converts RS-232 inputs to 5-V TTL/CMOS levels.
The receivers have a typical threshold of 1.2 V and a typical hysteresis of 0.5 V and can accept ±30-V inputs.
Each driver converts TTL/CMOS input levels into RS-232 levels.
The SN75LBC241 includes a receiver, a 3-state control line, and a low-power shutdown control line. When the
EN line is high, receiver outputs are placed in the high-impedance state. When EN is low, normal operation is
enabled.
The shutdown mode reduces power dissipation to less than 5 µW typically. In this mode, receiver outputs have
high impedance, driver outputs are turned off, and the charge-pump circuit is turned off. When SHUTDOWN
is high, the shutdown mode is enabled. When SHUTDOWN is low, normal operation is enabled.
This device has been designed to conform to TIA/EIA-232-F and ITU Recommendation V.28.
The SN75LBC241 has been designed using LinBiCMOS technology and cells contained in the Texas
Instruments LinASIC library. Use of LinBiCMOS circuitry increases latch-up immunity in this device over an
all-CMOS design.
The SN75LBC241 is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† Patent pending
LinBiCMOS and LinASIC are trademarks of Texas Instruments Incorporated.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
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1
SN75LBC241
LOW-POWER LinBiCMOS MULTIPLE DRIVERS AND RECEIVERS
SLLS137E – MAY 1992 – REVISED JANUARY 1999
logic symbol†
VCC
11
SHUTDOWN
DRV/RCV
EN2
25
24
EN1
EN
C1+
C1–
C2+
C2–
RIN1
RIN2
RIN3
RIN4
RIN5
TOUT1
TOUT2
TOUT3
TOUT4
12
13
VDD
CX
14
CX
15
17
CX
16
VSS
VSS
CX
9
8
1,2
4
5
1,2
27
26
1,2
23
22
1,2
18
19
1,2
2
7
2
3
6
2
1
20
2
28
21
2
10
GND
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
EN
RIN1
TOUT1
RIN2
TOUT2
RIN3
TOUT3
RIN4
TOUT4
RIN5
2
VDD
24
9
8
2
7
4
5
3
6
27
26
1
20
23
22
28
21
18
19
POST OFFICE BOX 655303
ROUT1
TIN1
ROUT2
TIN2
ROUT3
TIN3
ROUT4
TIN4
ROUT5
• DALLAS, TEXAS 75265
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
TIN1
TIN2
TIN3
TIN4
SN75LBC241
LOW-POWER LinBiCMOS MULTIPLE DRIVERS AND RECEIVERS
SLLS137E – MAY 1992 – REVISED JANUARY 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Input supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
Positive output supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC – 0.3 V to 15 V
Negative output supply voltage range, VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to –15 V
Input voltage range, VI: Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 V
Output voltage range, VO: TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V
ROUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
Short-circuit duration: TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
OPERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
DB
1348 mW
10.8 mW/°C
862 mW
DW
1603 mW
12.8 mW/°C
1026 mW
recommended operating conditions
Supply voltage, VCC
TIN
High level input voltage,
High-level
voltage VIH
EN, SHUTDOWN
MIN
NOM
MAX
4.5
5
5.5
2
TIN, EN, SHUTDOWN
External charge-pump capacitor
C1–C4 (see Figure 1)
1
C1, C3 (see Figure 1)
6.3
C2, C4 (see Figure 1)
16
External charge
charge-pump
pump capacitor voltage rating
0.8
Receiver input voltage, VI
Operating free-air temperature, TA
0
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V
V
2.4
Low-level input voltage, VIL
UNIT
V
µF
V
±30
V
70
°C
3
SN75LBC241
LOW-POWER LinBiCMOS MULTIPLE DRIVERS AND RECEIVERS
SLLS137E – MAY 1992 – REVISED JANUARY 1999
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
9
TOUT
RL = 3 kΩ to GND, See Note 2
5
ROUT
IOH = –1 mA
RL = 3 kΩ to GND, See Note 3
3.5
VOH
High level output voltage
High-level
VOL
Low level output voltage
Low-level
VIT+
VIT–
Receiver positive-going input threshold voltage
RIN
Receiver negative-going input threshold voltage
RIN
Vhys
ri
Input hysteresis voltage (VIT+ – VIT–)
RIN
Receiver input resistance
RIN
ro
Output resistance
TOUT
IOS
Short circuit output current§
TOUT
VCC = 5.5 V,
IIS
Short circuit input current
TIN
ICC
Supply current
VI = 0
VCC = 5.5 V, TA = 25°C,
All outputs open
TOUT
ROUT
IOL = 3.2 mA
VCC = 5 V,
VCC = 5 V,
VCC = 5 V
–9‡
MAX
V
–5
0.4
TA = 25°C
TA = 25°C
VCC = 5 V,
TA = 25°C
VDD = VSS = VCC = 0,
VO = ±2 V
1.7
0.8
3
2.4
1.2
V
V
1
V
5
7
kΩ
Ω
±10
All outputs open, TA = 25°C,
SHUTDOWN high
V
0.5
300
VO = 0
UNIT
mA
200
µA
4
8
mA
1
10
mA
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for logic voltage
levels only.
§ Not more than one output should be shorted at one time.
NOTES: 2. Total IOH drawn from TOUT1, TOUT2, TOUT3, TOUT4, and VDD terminals should not exceed 12 mA.
3. Total IOL drawn from TOUT1, TOUT2, TOUT3, TOUT4, and VSS terminals should not exceed –12 mA.
switching characteristics, VCC = 5 V, TA = 25°C
PARAMETER
4
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH(R)
Receiver propagation-delay time,
low- to high-level output
See Figure 2
500
ns
tPHL(R)
Receiver propagation-delay time,
high- to low-level output
See Figure 2
500
ns
tPZH
tPZL
Receiver output-enable time to high level
See Figure 5
100
ns
Receiver output-enable time to low level
See Figure 5
100
ns
tPHZ
tPLZ
Receiver output-disable time from high level
See Figure 5
50
ns
Receiver output-disable time from low level
See Figure 5
50
ns
SR
Driver slew rate
RL = 3 kΩ to 7 kΩ, CL = 2500 pF,
See Figure 4
SR(tr)
Driver transition region slew rate
RL = 3 kΩ to 7 kΩ, CL = 2500 pF,
See Figure 4
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4
6
V/µs
V/µs
SN75LBC241
LOW-POWER LinBiCMOS MULTIPLE DRIVERS AND RECEIVERS
SLLS137E – MAY 1992 – REVISED JANUARY 1999
APPLICATION INFORMATION
5-V Input
11
12
C1
1 µF
6.3 V
+
14
15
C2
1 µF
16 V
+
16
VCC
C1+
C1–
C2+
5-V to 10-V
Voltage Doubler
VDD
10-V to –10-V
Voltage Inverter
VSS
13
C3
1 µF
+ 6.3 V
17
C4
1 µF
+
16 V
C2–
VCC
400 kΩ
TIN1
2
7
VCC
TOUT1
T1
400 kΩ
TIN2
3
6
VCC
TTL/CMOS
Inputs
TOUT2
T2
RS-232
Outputs
400 kΩ
TIN3
1
20
VCC
TOUT3
T3
400 kΩ
TIN4
21
28
TOUT4
T4
ROUT1
8
R1
9
RIN1
5 kΩ
ROUT2
5
R2
4
RIN2
5 kΩ
TTL/CMOS
Outputs
ROUT3
26
R3
27
RIN3
RS-232
Inputs
5 kΩ
ROUT4
22
R4
23
RIN4
5 kΩ
ROUT5
EN
19
R5
18
5 kΩ
24
25
RIN5
SHUTDOWN
10
GND
Figure 1. Typical Operating Circuit
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SN75LBC241
LOW-POWER LinBiCMOS MULTIPLE DRIVERS AND RECEIVERS
SLLS137E – MAY 1992 – REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
VCC
≤10 ns
≤10 ns
90%
50%
Input
RL = 1.3 kΩ
Generator
(see Note A)
10%
ROUT
RIN
90%
50%
3V
10%
0V
500 ns
tPLH(R)
tPHL(R)
See Note C
CL = 50 pF
(see Note B)
VOH
Output
1.5 V
TEST CIRCUIT
1.5 V
VOL
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: ZO = 50 Ω, duty cycle ≤ 50%.
B. CL includes probe and jig capacitance.
C. All diodes are 1N3064 or equivalent.
Figure 2. Receiver Test Circuit and Waveforms for tPHL and tPLH Measurement
≤10 ns
≤10 ns
90%
50%
Input
Generator
(see Note A)
TIN
TOUT
RL
10%
RS-232
Output
90%
50%
3V
10%
0V
5 µs
tPHL
CL = 10 pF
(see Note B)
tPLH
tTHL
tTLH
VOH
90%
10%
VOL
90%
10%
Output
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: ZO = 50 Ω, duty cycle ≤ 50%.
B. CL includes probe and jig capacitance.
Figure 3. Driver Test Circuit and Waveforms for tPHL and tPLH Measurement (5-µs Input)
≤10 ns
≤10 ns
90%
1.5 V
Input
10%
RS-232
Output
Generator
(see Note A)
RL
TEST CIRCUIT
10%
0V
tTHL
Output
+t
3V
20 µs
CL
(see Note B)
SR
90%
1.5 V
6 V
THL or t TLH
3V
–3 V
tTLH
3V
–3 V
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: ZO = 50 Ω, duty cycle ≤ 50%.
B. CL includes probe and jig capacitance.
Figure 4. Test Circuit and Waveforms for tTHL and tTLH Measurement (20-µs Input)
6
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VOH
VOL
SN75LBC241
LOW-POWER LinBiCMOS MULTIPLE DRIVERS AND RECEIVERS
SLLS137E – MAY 1992 – REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
3V
EN
0V
tPZH
3.5 V
Generator
(see Note A)
RIN
ROUT
RL = 1 kΩ
0.8 V
2.5 V
tPZL
3V
CL = 150 pF
(see Note B)
EN
0V
tPHZ
TEST CIRCUIT
VOH – 0.1 V
2.5 V
VOL + 0.1 V
tPLZ
NOTES: A. The pulse generator has the following characteristics: ZO = 50 Ω, duty cycle ≤ 50%.
B. CL includes probe and jig capacitance.
Figure 5. Receiver Output Enable and Disable Timing
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Copyright  1999, Texas Instruments Incorporated