CXP83120A/83124A CMOS 8-bit Single Chip Microcomputer Description The CXP83120A/83124A is a CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time base timer, 32kHz timer/counter, capture timer counter, LCD controller/driver, remote control reception circuit and 14-bit PWM output besides the basic configurations of 8-bit CPU, ROM, RAM, and I/O port. The CXP83120A/83124A also provides a sleep/stop function that enables lower power consumption. 100 pin QFP (Plastic) 100 pin LQFP (Plastic) Features • Wide-range instruction system (213 instructions) to cover various types of data. — 16-bit arithmetic/multiplication and division/boolean bit operation instructions • Minimum instruction cycle 400ns at 10MHz operation 8µs at 500kHz 122µs at 32kHz operation • Incorporated ROM capacity 20Kbytes (CXP83120A) 24Kbytes (CXP83124A) • Incorporated RAM capacity 644bytes (includes LCD display data area) • Peripheral functions — A/D converter 8-bit, 8-channel, successive approximation method (Conversion time of 32µs/10MHz) — Serial interface 8-bit, 8-stage FIFO incorporated (Auto transfer for 1 to 8 bytes), 1 channel 8-bit clock synchronized type, 1 channel — Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 16-bit capture timer/counter, 32kHz timer/counter — LCD controller/driver Maximum 160 segment display possible (during 1/4 duty) 4 common output, 40 segment output Display method static, 1/2, 1/3, 1/4 duty Bias method 1/2, 1/3 bias — Remote control reception circuit 8-bit pulse measuring counter, 6-stage FIFO — PWM output circuit 14 bits, 1 channel • Interruption 15 factors, 15 vectors, multi-interruption possible • Standby mode SLEEP/STOP • Package 100-pin plastic QFP/LQFP • Piggyback/evaluation chip CXP83200A 100-pin ceramic QFP/LQFP Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94843-PK –2– 40 4 SEG0 to SEG39 COM0 to COM3 VL VLC1 VLC2 VLC3 AVREF ADJ TO CINT EC1 16 BIT CAPTURE TIMER/COUNTER 2 8 BIT TIMER 1 8 BIT TIMER/COUNTER 0 EC0 FIFO SERIAL INTERFACE UNIT 1 SERIAL INTERFACE UNIT 0 CS0 SI0 SO0 SCK0 FIFO SI1 SO1 SCK1 REMOCON 14 BIT PWM GENERATOR LCD CONTROLLER/ DRIVER A/D CONVERTER 2 2 INT0 INT1 INT2 NMI/INT3 2 2 INTERRUPT CONTROLLER AVSS RMC PWM 8 PRESCALER/ TIME BASE TIMER ROM 20K/24K BYTES SPC 700 CPU CORE TEX TX EXTAL2 XTAL2 EXTAL1 XTAL1 RST VDD VSS 32KHz TIMER/COUNTER RAM 644 BYTES CLOCK GEN/ SYSTEM CONTROL PB0 to PB7 PC0 to PC7 PD0 to PD7 PE0 to PE4 PE5 to PE6 PF0 to PF7 8 8 8 5 2 8 8 8 PH0 to PH7 PG0 to PG7 PA0 to PA7 8 PORT B PORT E AN0 to AN7 PORT A PORT C PORT D PORT F PORT G PORT H Block Diagram CXP83120A/83124A CXP83120A/83124A SEG27/PF3 SEG29/PF5 SEG28/PF4 SEG30/PF6 SEG31/PF7 SEG33/PG1 SEG32/PG0 SEG34/PG2 VDD VSS NC TEX TX SEG35/PG3 SEG36/PG4 SEG38/PG6 SEG37/PG5 SEG39/PG7 PE0/INT0/EC0 PE1/INT1/EC1 Pin Assignment (Top View) (QFP package) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PE3/INT2 1 80 SEG26/PF2 PE3/INT3/NMI 2 79 SEG25/PF1 PE4/RMC 3 78 SEG24/PF0 PE5/PWM 4 77 SEG23/PD7 PE6/TO/ADJ 5 76 SEG22/PD6 PB0/CINT 6 75 SEG21/PD5 PB1/CS0 7 74 SEG20/PD4 PB2/SCK0 8 73 SEG19/PD3 PB3/SI0 9 72 SEG18/PD2 PB4/SO0 10 71 SEG17/PD1 PB5/SCK1 11 70 SEG16/PD0 PB6/SI1 12 69 SEG15 PB7/SO1 13 68 SEG14 PC0 14 67 SEG13 PC1 15 66 SEG12 PC2 16 65 SEG11 PC3 17 64 SEG10 PC4 18 63 SEG9 PC5 19 62 SEG8 PC6 20 61 SEG7 PC7 21 60 SEG6 PH0 22 59 SEG5 PH1 23 58 SEG4 PH2 24 57 SEG3 PH3 25 56 SEG2 PH4 26 55 SEG1 PH5 27 54 SEG0 PH6 28 53 COM3 PH7 29 52 COM2 PA0/AN0 30 51 COM1 Note) 1. NC (Pin 90) is always connected to VDD. 2. VSS (Pin 41 and 91) are both connected to GND. –3– COM0 VLC1 VLC2 VLC3 VL AVSS AVREF EXTAL2 XTAL2 VSS XTAL1 EXTAL1 RST PA7/AN7 PA6/AN6 PA5/AN5 PA4/AN4 PA3/AN3 PA2/AN2 PA1/AN1 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CXP83120A/83124A SEG24/PF0 SEG25/PF1 SEG26/PF2 SEG28/PF4 SEG27/PF3 SEG29/PF5 SEG31/PF7 SEG30/PF6 SEG32/PG0 SEG33/PG1 SEG34/PG2 NC VDD TX VSS SEG35/PG3 TEX SEG36/PG4 SEG37/PG5 SEG39/PG7 SEG38/PG6 PE0/INT0/EC0 PE1/INT1/EC1 PE2/INT2 PE3/INT3/NMI Pin Assignment (Top View) (LQFP package) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PE4/RMC 1 75 SEG23/PD7 PE5/PWM 2 74 SEG22/PD6 PE6/TO/ADJ 3 73 SEG21/PD5 PB0/CINT 4 72 SEG20/PD4 PB1/CS0 5 71 SEG19/PD3 PB2/SCK0 6 70 SEG18/PD2 PB3/SI0 7 69 SEG17/PD1 PB4/SO0 8 68 SEG16/PD0 PB5/SCK1 9 67 SEG15 PB6/SI1 10 66 SEG14 PB7/SO1 11 65 SEG13 PC0 12 64 SEG12 PC1 13 63 SEG11 PC2 14 62 SEG10 PC3 15 61 SEG9 PC4 16 60 SEG8 PC5 17 59 SEG7 PC6 18 58 SEG6 PC7 19 57 SEG5 PH0 20 56 SEG4 PH1 21 55 SEG3 PH2 22 54 SEG2 PH3 23 53 SEG1 PH4 24 52 SEG0 PH5 25 51 COM3 Note) 1. NC (Pin 88) is always connected to VDD. 2. VSS (Pin 39 and 89) are both connected to GND. –4– COM2 COM0 COM1 VLC2 VLC1 VLC3 VL AVSS AVREF XTAL2 EXTAL2 VSS XTAL1 RST EXTAL1 PA7/AN7 PA6/AN6 PA5/AN5 PA4/AN4 PA3/AN3 PA2/AN2 PA1/AN1 PA0/AN0 PH7 PH6 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CXP83120A/83124A Pin Description Symbol I/O PA0/AN0 to PA7/AN7 I/O/Analog input PB0/CINT I/O/Input PB1/CS0 I/O/Input PB2/SCK0 I/O/I/O PB3/SI0 I/O/Input PB4/SO0 I/O/Output PB5/SCK1 I/O/I/O PB6/SI1 I/O/input PB7/SO1 I/O/Output Functions (Port A) 8-bit I/O port. I/O can be set in a single bit unit. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) Analog inputs to A/D converter. (8 pins) External capture input to 16-bit timer/counter. (Port B) 8-bit I/O port. I/O can be set in a single bit unit. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1). (Port C) 8-bit I/O port. I/O can be set in a single bit unit. Capable of driving 12mA sync current. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) PC0 to PC7 I/O PE0/INT0/ EC0 Input/Input/Input PE1/INT1/ EC1 Input/Input/Input PE2/INT2 Input/Input PE3/INT3/ NMI Input/Input/Input PE4/RMC Input/Input PE5/PWM Output/Output 14-bit PWM output. PE6/TO/ ADJ Output/Output/ Output Rectangular wave output for 16-bit timer/counter (duty output 50%). PH0 to PH7 I/O External event inputs for timer/counter. (2 pins) (Port E) 7-bit port. lower 5 bits are for inputs; upper 2 bits are for outputs. (7 pins) External interruption request inputs. (4 pins) Non-maskable interruption request input. Remote control reception circuit input. Output for 32kHz oscillation frequency division. (Port H) 8-bit I/O port. I/O can be set in a single bit unit. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) –5– CXP83120A/83124A Symbol I/O Functions PD0/SEG16 to PD7/SEG23 Output/Output (Port D) 8-bit output port. (8 pins) PF0/SEG24 to PF7/SEG31 Output/Output (Port F) 8-bit output port. (8 pins) PG0/SEG32 to PG7/SEG39 Output/Output (port G) 8-bit output port. (8 pins) SEG0 to SEG15 Output LCD segment signal output. COM0 to COM3 Output LCD common signal output. VLC1 to VLC3 LCD bias power supply. LCD segment signal output. Control pin to cut off the current flowing to external LCD bias resistor during standby. VL Output EXTAL1 Input Crystal connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL1; opposite phase clock should be input to XTAL1. System clock oscillation of EXTAL1 and XTAL1 is used for normal operation mode (Max. 10MHz). Input Crystal connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL2; opposite phase clock should be input to XTAL2. System clock oscillation of EXTAL2 and XTAL2 is used for sub clock mode (Typ. 500kHz). TEX Input TX Output Crystal connectors for 32kHz timer/counter clock generation circuit. Connect a 32.768kHz crystal oscillator between TEX and TX. For usage as event input, connect clock oscillation source to TEX, and leave TX open. RST Input Low-level active system reset. XTAL1 EXTAL2 XTAL2 NC AVREF NC. Under normal operating conditions, connect to VDD. Input Reference voltage input for A/D converter. AVSS A/D converter GND. VDD Positive power supply. VSS GND. Two VSS are connected to GND. –6– CXP83120A/83124A I/O Circuit Format for Pins Pin When reset Circuit format Port A ∗ Pull-up resistor "0" when reset Port A data PA0/AN0 to PA7/AN7 Port A direction IP Input protection circuit "0" when reset Hi-Z Data bus RD (Port A) Port A input selection Input multiplexer "0" when reset A/D converter ∗ Pull-up transistors approx. 100kΩ 8 pins Port B ∗ Pull-up resistor "0" when reset Port B data PB0/CINT PB1/CS0 PB3/SI0 PB6/SI1 Port B direction IP Hi-Z "0" when reset Schmitt input Data bus RD (Port B) CINT CS0 SI0 SI1 4 pins ∗ Pull-up transistors approx. 100kΩ Port B ∗ Pull-up resistor "0" when reset SCK OUT Output enable Port B output selection PB2/SCK0 PB5/SCK1 "0" when reset Hi-Z Port B data IP Port B direction "0" when reset Data bus Schmitt input RD (Port B) 2 pins ∗ Pull-up transistors approx. 100kΩ SCK in –7– CXP83120A/83124A Pin When reset Circuit format Port B ∗ Pull-up resistor "0" when reset SO Output enable Port B output selection PB4/SO0 PB7/SO1 "0" when reset Hi-Z Port B data IP Port B direction "0" when reset Data bus RD (Port B) ∗ Pull-up transistors approx. 100kΩ 2 pins Port C ∗2 Pull-up resistor "0" when reset Port C data PC0 to PC7 ∗1 Port C direction IP Hi-Z "0" when reset Data bus ∗1 High current drive of 12mA possible ∗2 Pull-up transistors approx. 100k Ω RD (Port C) 8 pins Port E PE0/INT0/EC0 PE1/INT1/EC1 PE2/INT2 PE3/INT3/NMI PE4/RMC Schmitt input IP RD (Port E) 5 pins –8– INT0/EC0 INT1/EC1 INT2 INT3/NMI RMC Data bus Hi-Z CXP83120A/83124A P in When reset Circuit format Port E PWM Port E output selection "0" when reset PE5/PWM High level Reset E data "1" when reset Data bus RD (Port E) 1 pin Port E ∗1 Internal reset signal Port E data "1" when reset TO PE6/TO/ADJ MPX High level ∗2 ADJ16K (High level with 150kΩ resistor when reset) ADJ2K Port E output selection Port E output selection ∗1 Pull-up transistors approx. 150kΩ. ∗2 ADJ signals are frequency divider outputs for 32kHz oscillation frequency adjustment. ADJ2K provides usage as buzzer output. "00" when reset TO Output enable 1 pin Port H ∗ Pull-up resistor "0" when reset Port H data PH0 to PH7 Hi-Z Port H direction IP "0" when reset Data bus RD (Port H) ∗ Pull-up transistors approx. 100kΩ 8 pins –9– CXP83120A/83124A Pin When reset Circuit format Port D Port F PD0 to PD7 PF0 to PF7 PG0 to PG7 Port data Port G PD7 to PD4 by a single bit unit PD3 to PD0 by 4-bit unit PF7 to PF0 PG7 to PG0 by 8-bit unit Segment output (VDD level) Port/segment output selection "0" when reset Segment data 24 pins Segment driver Segment VCH SEG0 to SEG15 VDD level VCL 16 pins Common VDD COM0 to COM3 VLC1 VDD level VLC2 4 pins VLC3 VL LCD control (DSP bit) 1 pin Hi-Z "0" when reset – 10 – CXP83120A/83124A Pin EXTAL1 XTAL1 2 pins EXTAL2 XTAL2 2 pins TEX TX When reset Circuit format EXTAL1 IP IP • Feedback resistor is removed during stop. XTAL1 becomes "High" level. XTAL1 IP EXTAL2 • Diagram shows circuit composition during oscillation. IP • Diagram shows circuit composition during oscillation. • Feedback resistor is removed during stop. XTAL2 becomes "High" level. Oscillation EXTAL2 Hi-Z XTAL2 High level XTAL2 TEX IP IP • Diagram shows circuit composition during oscillation. • When the operation of the oscillation circuit is stopped by the software, the feedback resistor is removed and TEX and TX become "Low" level and "High" level respectively. TX 2 pins Oscillation Pull-up resistor RST OP Low level Mask option IP Schmitt input 1 pin – 11 – CXP83120A/83124A Absolute Maximum Ratings Item Supply voltage (Vss = 0V) Symbol Rating Unit VDD –0.3 to +7.0 V AVSS –0.3 to +0.3 V V Remarks LCD bias voltage VLC1, VLC2, VLC3 –0.3 to +7.0∗1 Input voltage VIN –0.3 to +7.0∗1 V Output voltage VOUT –0.3 to +7.0∗1 V High level output current IOH –5 mA Output per pin –50 mA Total for all output pins IOL 15 mA IOLC 20 mA Value per pin, excluding high current outputs Value per pin∗2 for high current outputs Low level total output current ∑IOL 100 mA Total for all output pins Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +150 °C High level total output current ∑IOH Low level output current Allowable power dissipation PD 600 380 mW QFP package LQFP package ∗1 VIN and VOUT must not exceed VDD + 0.3V. ∗2 The high current drive transistor is the N-ch transistor of Port C (PC) Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI. – 12 – CXP83120A/83124A Recommended Operating Conditions Item Supply voltage Symbol (Vss = 0V) Min. Max. 4.5 5.5 3.5 5.5 3.0 5.5 2.7 5.5 Guaranteed operation range with TEX clock 2.5 5.5 Guaranteed data hold range during STOP Vss VDD V LCD power supply range∗5 VIH 0.7VDD VDD V ∗2 VIHS 0.8VDD VDD V VDD Unit Remarks High-speed mode guaranteed operation range∗1 Low-speed mode guaranteed operation range∗1 V Guaranteed operation range during EXTAL2 clock (sub clock mode) VLC1 LCD bias voltage VLC2 VLC3 High level input voltage VIHEX Low level input voltage Operating temperature VDD – 0.4 VDD + 0.3 V Hysteresis input∗3 EXTAL∗4 ∗2 VIL 0 0.3VDD V VILS 0 0.2VDD V VILEX –0.3 0.4 V Topr –20 +75 °C Hysteresis input∗3 EXTAL∗4 ∗1 During EXTAL1 clock (main clock mode), high-speed mode is 1/2 frequency division clock selection; lowspeed mode is 1/16 frequency division clock selection. ∗2 Value for each pin of normal input ports (PA, PB4, PB7, PC and PH). ∗3 Value of the following pins; RST, CINT CS0, SI0, SI1, SCK0, SCK1, EC0/INT0, EC1/INT1, INT2, NMI/INT3, and RMC. ∗4 Specifies only during external clock input. ∗5 Optimal values are determined by LCD used. – 13 – CXP83120A/83124A Electrical Characteristics (Ta = –20 to +75°C, Vss = 0V) DC Characteristics Item High level output voltage Symbol VOH Low level output voltage VOL Pins Input current IILR IIH IIL I/O leakage current IIZ Common output impedance RCOM Segment output impedance RSEG Unit VDD = 4.5V, IOH = –0.5mA 4.0 V VDD = 4.5V, IOH = –1.2mA 3.5 V V VDD = 4.5V, IOL = 3.6mA 0.6 V PC VDD = 4.5V, IOL = 12.0mA 1.5 V VDD = 5.5V, VIH = 5.5V 0.5 40 µA VDD = 5.5V, VIL = 0.4V –0.5 –40 µA VDD = 5.5V, VIH = 5.5V 0.3 30 µA VDD = 5.5V, VIL = 0.4V –0.3 –30 µA VDD = 5.5V, VIH = 5.5V 0.1 10 µA VDD = 5.5V, VIL = 0.4V –0.1 –10 µA VDD = 5.5V, VIL = 0.4V –1.5 –400 µA VDD = 4.5V, VIH = 4.0V PA to PC∗3, VDD = 5.5V, VIL = 0.4V PH∗3 PE0 to PE4, VDD = 5.5V, RST∗2 VI = 0, 5.5V –3.33 EXTAL1 EXTAL2 TEX RST∗2 COM0 to COM3 SEG0 to SEG15 SEG16 to SEG39∗1 VDD = 5V, VLC1 = 3.75V VLC2 = 2.5V VLC3 = 1.25 High-speed mode operation (1/2 frequency division clock) IDD1 Supply current∗4 Max. 0.4 IIHT IILT Typ. VDD = 4.5V, IOL = 1.8mA IIHE2 IILE2 Min. PA, PB, PC, PD∗1, PE5, PE6 PF to PG∗1 VL (only VOL) IIHE1 IILE1 Conditions µA –50 µA ±10 µA 3 5 kΩ 5 15 kΩ 18 40 mA VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) IDD2 VDD = 3.5V, 500kHz crystal oscillation (C1 = C2 = 22pF) 0.8 2 mA IDD3 VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) 35 100 µA 1.1 8 mA SLEEP mode IDDS1 VDD VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) IDDS2 VDD = 3.5V, 500kHz crystal oscillation (C1 = C2 = 22pF) 400 800 µA IDDS3 VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) 9 30 µA IDDSS STOP mode VDD = 5.5V, 10MHz, 500kHz crystal oscillation and termination of 32kHz oscillation 10 µA – 14 – CXP83120A/83124A Item Input capacity Symbol Pins CIN Pins other than PB7, PE5, PE6 VLC1 to VLC3 COM0 to COM3 SEG0 to SEG15 PD0/SEG16 to PD7/SEG23 PF0/SEG24 to PF7/SEG31 PG0/SEG32 to PG7/SEG39 AVREF, AVSS, VDD, VSS Conditions Clock 1MHz 0V for all pins excluding measured pins Min. Typ. Max. Unit 10 20 pF ∗1 Common pins of PD0/SEG16 to PD7/SEG23, PF0/SEG24 to PF7/SEG31, PG0/SEG32 to PG7/SEG39, PD, PF and PG is the case when the common pin is selected as port; SEG16 to SEG39 is when the common pin is selected as segment output. ∗2 RST specifies the input current when pull-up resitor has been selected; leakage current when no resistor has been selected. ∗3 Pins PA to PC, and PH specifies the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. (PE0 to PE4 specifies the leakage current.) ∗4 When all output pins are left open. – 15 – CXP83120A/83124A AC Characteristics (1) Clock timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Item Symbol Conditions Pin Min. XTAL1 EXTAL1 Fig. 1, Fig. 2 EXTAL1 Fig. 1, Fig. 2 external clock drive EXTAL1 Fig. 1, Fig. 2 external clock drive fC XTAL2 EXTAL2 VDD = 3.0 to 5.5V Fig. 1, Fig. 2 0.3 System clock input pulse width tXL, tXH EXTAL2 VDD = 3.0 to 5.5V Fig. 1, Fig. 2 external clock drive 450 System clock input rise and fall time tCR, tCF EXTAL2 VDD = 3.0 to 5.5V Fig. 1, Fig. 2 external clock drive Event count input clock pulse width EC0 EC1 Fig. 3 Event count input clock rise and fall time tEH, tEL tER, tEF EC0 EC1 Fig. 3 System clock frequency fC TEX TX VDD = 2.7 to 5.5V Fig. 2 (32kHz clock applied condition) Event count input clock input pulse width tTL, tTH tTR, tTF TEX Fig. 3 TEX Fig. 3 System clock frequency fC System clock input pulse width System clock input rise and fall time tXL, tXH tCR, tCF System clock frequency Event count input clock rise and fall time Typ. 1 Max. Unit 10 MHz ns 37.5 0.5 200 ns 0.7 MHz ns 200 tsys +50∗ ns ns 20 ms kHz 32.768 µs 10 20 ms ∗ tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock control register (address: 00FEH). tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11"). Fig. 1. Clock timing 1/fc VDD – 0.4V EXTAL1 EXTAL2 0.4V tCF tXH tXL tCR AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA Fig. 2. Clock applied conditions Crystal oscillation Ceramic oscillation EXTAL C1 XTAL C2 External clock EXTAL 32kHz clock applied condition Crystal oscillation TEX XTAL 74HC04 – 16 – C1 TX C2 CXP83120A/83124A Fig. 3. Event count clock timing 0.8VDD TEX EC0 EC1 0.2VDD tEH tTH tEF tTF (2) Serial transfer (CH0) Item tEL tTL tER tTR (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Symbol Conditions Pin Min. Max. Unit CS0 ↓ → SCK0 delay time tDCSK SCK0 Chip select transfer mode (SCK0 = output mode) tsys + 200 ns CS0 ↑ → SCK0 float delay time tDCSKF SCK0 Chip select transfer mode (SCK0 = output mode) tsys + 200 ns CS0 ↓ → SO0 delay time tDCSO SO0 Chip select transfer mode tsys + 200 ns CS0 ↑ → SO0 float delay time tDCSOF SO0 Chip select transfer mode tsys + 200 ns CS0 high level width tWHCS CS0 Chip select transfer mode SCK0 cycle time tKCY SCK0 SCK0 high and low level widths tKH tKL SCK0 SI0 input setup time (for SCK0 ↑) tSIK SI0 SI0 input hold time (for SCK0 ↑) tKSI SI0 SCK0 ↓ → SO0 delay time tKSO SO0 tsys + 200 2tsys + 200 ns 16000/fc ns Input mode tsys + 100 ns Output mode 8000/fc – 50 ns SCK0 input mode 100 ns SCK0 output mode 200 ns tsys + 200 ns 100 ns Input mode Output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode ns tsys + 200 ns 100 ns Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock control register (address: 00FEH). tsys ( ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL. – 17 – CXP83120A/83124A Fig. 4. Serial transfer CH0 timing tWHCS CS0 0.8VDD 0.2VDD tKCY tDCSK tKL tDCSKF tKH 0.8VDD 0.8VDD SCK0 0.2VDD tSIK tKSI 0.8VDD SI0 Input data 0.2VDD tDCSO tKSO tDCSOF 0.8VDD SO0 Output data 0.2VDD – 18 – CXP83120A/83124A Serial Transfer (CH1) Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Symbol Pin Conditions tKCY SCK1 SCK1 high and low level widths tKH tKL SCK1 SI1 input setup time (for SCK1 ↑) tSIK SI1 SI1 input hold time (for SCK1 ↑) tKSI SI1 SCK1 ↓ → SO1 delay time tKSO SO1 SCK1 cycle time Min. Max. 1000 ns 16000/fc ns 400 ns 8000/fc – 50 ns SCK1 input mode 100 ns SCK1 output mode 200 ns SCK1 input mode 200 ns SCK1 output mode 100 ns Input mode Output mode input mode Output mode SCK1 input mode 200 ns SCK1 output mode 100 ns Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL. Fig. 5. Serial transfer CH1 timing tKCY tKL tKH 0.8VDD SCK1 0.2VDD tSIK tKSI 0.8VDD SI1 Unit Input data 0.2VDD tKSO 0.8VDD SO1 Output data 0.2VDD – 19 – CXP83120A/83124A (3) A/D converter characteristics Item Symbol (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = AVSS = 0V) Pin Conditions Max. Unit Resolution 8 Bits Linearity error ±3 LSB Ta = 25°C VDD = AVREF = 5.0V VSS = AVSS = 0V Zero transition voltage VZT∗1 Full-scale transition voltage VFT∗2 Conversion time Sampling time tCONV tSAMP Reference input voltage VREF AVREF Analog input voltage VIAN AN0 to AN7 Typ. –10 10 70 mV 4910 4970 5030 mV 160/fADC∗3 12/fADC∗3 IREF AVREF current Min. AVREF µs VDD – 0.5 VDD V 0 AVREF V 1.0 mA 10 µA 0.6 Operation mode IREFS µs SLEEP mode STOP mode 32kHz operation mode Fig. 6. Definition of A/D converter terms Digital conversion value FFH FEH ∗1 VZT:Value at which the digital conversion value changes from 00 H to 01H and vice versa. ∗2 VFT:Value at which the digital conversion value changes from FE H to FFH and vice versa. ∗3 fADC indicates the below values due to the Bit 6 (CKS) of A/D control register (address: 00F9H )and the Bit 7 (PCK1) and Bit 6 (PCK0) of clock control register (address: 00FFH). Linearity error 01H 00H CKS VFT VZT Analog input PCK1, PCK0 0 (φ/2 selection) 1 (φ selection) 00 (φ = fEX/2) fADC = fC/2 fADC = fC 01 (φ = fEX/4) fADC = fC/4 fADC = fC/2 11 (φ = fEX/16) fADC = fC/16 fADC = fC/8 – 20 – CXP83120A/83124A (4) Interruption, reset input Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Symbol Pin External interruption high and low level widths tIH tIL INT0 INT1 INT2 NMI/INT3 Reset input low level width tRSL RST Conditions Min. Max. Unit 1 µs 32/fc µs Fig. 7. Interruption input timing tIH tIL 0.8VDD INT0 INT1 INT2 NMI / INT3 (NMI specifies only for the falling edge) 0.2VDD tIL tIH Fig. 8. RST input timing tRSL RST 0.2VDD – 21 – CXP83120A/83124A Appendix Fig. 9. SPC700 series recommended oscillation circuit AAAA AAAA AAAA (i) Main clock 500kHz sub clock EXTAL XTAL Rd C1 C2 AAAA AAAAA AAAA AAAAA AAAA AAAAA (iii) 32kHz sub clock (ii) Main clock 500kHz sub clock EXTAL EXTAL TEX XTAL XTAL TX Rd Rd C1 C2 C 1 C2 Manufacturer MURATA MFG CO., LTD. Model fc (MHz) CSA4.19MG 4.19 CSA8.00MG 8.00 CSA10.0MT 10.00 CST4.19MGW∗ 4.19 CST8.00MTW∗ 8.00 CST10.00MTW∗ 10.00 C1 (pF) C2 (pF) Rd (Ω) Circuit example (i) 30 30 0 (ii) 4.19 RIVER ELETEC CO., LTD. HC-49/U03 8.00 15 15 470 10.00 4.19 KINSEKI LTD. HC-49/U (-S) 8.00 2.2k 22 22 560 18 18 0 10.00 Those marked with an asterisk (∗) signify types with built-in ground capacitance (C1, C2). Mask Option Table Item Reset pin pull-up resistor Content Non-existent Existent – 22 – (i) CXP83120A/83124A Characteristics Curves IDD vs. VDD IDD vs. fc (fc = 10MHz main clock, Ta = 25°C, typical) (VDD = 5V, Ta = 25°C, typical) 1/2 frequency dividing mode 20.0 20 5.0 Main clock 1/2 frequency dividing mode fc = 500kHz sub clock 1/2 frequency dividing mode fc = 10MHz main clock SLEEP mode 1.0 fc = 500kHz sub clock SLEEP mode 0.5 32kHz mode (Instruction) 0.1 (100µA) 0.05 (50µA) 32kHz SLEEP mode IDD – Supply current [mA] IDD – Supply current [mA] 10.0 15 10 5 Main clock SLEEP mode 0.01 (10µA) 2 3 4 5 6 7 0 VDD – Supply voltage [ V ] – 23 – 5 10 fc – System clock [MHz] 15 CXP83120A/83124A Unit: mm 100PIN QFP (PLASTIC) + 0.4 14.0 – 0.01 17.9 ± 0.4 15.8 ± 0.4 + 0.1 0.15 – 0.05 23.9 ± 0.4 + 0.4 20.0 – 0.1 A 0.65 + 0.35 2.75 – 0.15 ±0.12 M 0.8 ± 0.2 (16.3) 0.15 0° to 15° DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING SONY CODE QFP-100P-L01 LEAD TREATMENT EIAJ CODE ∗QFP100-P-1420-A LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 1.4g JEDEC CODE 100PIN LQFP (PLASTIC) 16.0 ± 0.2 ∗ 14.0 ± 0.1 75 51 76 (15.0) 50 0.5 ± 0.2 A 26 (0.22) 100 1 0.5 ± 0.08 + 0.08 0.18 – 0.03 25 + 0.2 1.5 – 0.1 + 0.05 0.127 – 0.02 0.1 0.1 ± 0.1 0° to 10° 0.5 ± 0.2 Package Outline DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY/PHENOL RESIN SONY CODE LQFP-100P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE ∗QFP100-P-1414-A LEAD MATERIAL 42 ALLOY JEDEC CODE PACKAGE WEIGHT – 24 –