TI TLV5510IPW

TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
D
D
D
D
D
D
D
8-Bit Resolution
Integral Linearity Error
± 0.75 LSB Max (25°C)
± 1 LSB Max (– 35°C to 85°C)
Differential Linearity Error
± 0.5 LSB (25°C)
± 0.75 LSB Max (– 35°C to 85°C)
Maximum Conversion Rate
10 Mega-Samples per Second
(MSPS) Min
2.7-V to 3.6-V Single-Supply Operation
Low Power Consumption . . . 42 mW Typ at
3V
Low Voltage Replacement for CXD1175
OE
DGND
D1(LSB)
D2
D3
D4
D5
D6
D7
D8(MSB)
VDDD
CLK
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
DGND
REFB
REFBS
AGND
AGND
ANALOG IN
VDDA
REFT
REFTS
VDDA
VDDA
VDDD
† Also available in tape and reel and
ordered as the TLV5510INSR.
Applications
D
D
D
D
PW OR NS PACKAGE†
(TOP VIEW)
Communications
Digital Imaging
Video Conferencing
High-Speed Data Conversion
AVAILABLE OPTIONS
PACKAGE
TA
– 35°C to 85°C
TSSOP (PW)
SOP (NS)
TLV5510IPW
TLV5510INS
description
The TLV5510 is a CMOS 8-bit resolution semiflash analog-to-digital converter (ADC) with a 2.7-V to 3.6-V single
power supply and an internal reference voltage source. It converts a wide band analog signal (such as a video
signal) to a digital signal at a sampling rate of dc to 10 MHz.
functional block diagram
Resistor
Reference
Divider
OE
REFB
200 Ω
NOM
Lower Sampling
Comparators
(4 Bit)
REFT
REFBS
Lower Encoder
(4 Bit)
D1(LSB)
Lower Data
Latch
60 Ω
NOM
AGND
D3
D4
Lower Sampling
Comparators
(4 Bit)
AGND
VDDA
Lower Encoder
(4 Bit)
D5
40 Ω
NOM
REFTS
ANALOG IN
CLK
D2
Upper Sampling
Comparators
(4 Bit)
Upper Data
Latch
Upper Encoder
(4 Bit)
D6
D7
D8(MSB)
Clock
Generator
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
schematics of inputs and outputs
EQUIVALENT OF ANALOG INPUT
EQUIVALENT OF EACH DIGITAL INPUT
VDDA
EQUIVALENT OF EACH DIGITAL OUTPUT
VDDD
VDDD
D1 – D8
OE, CLK
ANALOG IN
AGND
DGND
DGND
Terminal Functions
TERMINAL
NAME
AGND
ANALOG IN
CLK
NO.
I/O
20, 21
DESCRIPTION
Analog ground
19
I
Analog input
12
I
Clock input
DGND
2, 24
D1 – D8
3 – 10
O
Digital data out. D1:LSB, D8:MSB
1
I
Output enable. When OE = low, data is enabled. When OE = high, D1 – D8 is high impedance.
OE
Digital ground
VDDA
VDDD
14, 15, 18
Analog supply voltage
11, 13
Digital supply voltage
REFB
23
REFBS
22
REFT
17
REFTS
16
I
Reference voltage in (bottom)
Reference voltage (bottom). When using the internal voltage divider to generate a nominal 2-V reference,
this terminal is shorted to the REFB terminal and the REFTS terminal is shorted to the REFT terminal (see
Figure 21).
I
Reference voltage in (top)
Reference voltage (top). When using the internal voltage divider to generate a nominal 2-V reference, this
terminal is shorted to the REFT terminal and the REFBS terminal is shorted to the REFB terminal (see
Figure 21).
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDDA, VDDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Reference voltage input range, REFT, REFB, REFBS, REFTS . . . . . . . . . . . . . . . . . . . . . . . . . AGND to VDDA
Analog input voltage range, VI(ANLG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to VDDA
Digital input voltage range, VI(DGTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to VDDD
Digital output voltage range, VO(DGTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to VDDD
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 35°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
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TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
recommended operating conditions
Supply voltage
MIN
NOM
MAX
VDDA – AGND
VDDD – DGND
2.7
3
3.6
2.7
3
3.6
AGND – DGND
– 100
0
100
Reference input voltage (top), REFT
REFB+2
Reference input voltage (bottom), REFB
0
Analog input voltage range, VI(ANLG) (see Note 1)
0.6
V
mV
VDDA–0.3
V
REFT– 2
V
REFT
V
REFB
2.5
High-level input voltage, VIH
UNIT
V
Low-level input voltage, VIL
0.5
Pulse duration, clock high, tw(H)
10
Pulse duration, clock low, tw(L)
10
V
ns
ns
Clock frequency, f(CLK)
Sampling frequency, fs
NOTE 1: REFT – REFB ≤ 2.4 V maximum
10
MHz
10
MSPS
electrical characteristics at VDDD = VDDA = 3 V, REFT = 2.5 V, REFB = 0.5 V, f(CLK) = 10 MHz,
TA = 25°C (unless otherwise noted)
digital I/O
TEST CONDITIONS†
PARAMETER
MIN
TYP
MAX
IIH
IIL
High-level input current
Low-level input current
VDDD = MAX,
VDDD = MAX,
VIH = VDDD
VIL = 0
5
IOH
IOL
High-level output current
OE = GND,
Low-level output current
OE = GND,
VDDD = MIN,
VDDD = MIN,
VOH = VDDD – 0.5 V
VOL = 0.4 V
IOZH
High-level high-impedance-state
output leakage current
OE = VDDD,
VDDD = MAX
VOH = VDDD
15
IOZL
Low-level high-impedance-state
output leakage current
OE = VDDD,
VDDD = MIN
VOL = 0
15
5
– 1.6
UNIT
µA
mA
2.6
µA
† Conditions marked MIN or MAX are as stated in recommended operating conditions.
power
PARAMETER
IDD
Supply current
TEST CONDITIONS†
MIN
fsin = 1 MHz sine wave, reference resistor dissipation is separate
Iref
Reference voltage current ∆REF = REFT – REFB = 2 V
† Conditions marked MIN or MAX are as stated in recommended operating conditions.
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6
TYP
MAX
4
10
UNIT
mA
10
14
mA
3
TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
electrical characteristics at VDDD = VDDA = 3 V, REFT = 2.5 V, REFB = 0.5 V, f(CLK) = 10 MHz,
TA = 25°C (unless otherwise noted) (continued)
static performance
TEST CONDITIONS†
PARAMETER
Self-bias (1), at REFB
Short REFB to REFBS,
REFBS
Short REFT to REFTS
Self-bias (2), at REFT
Short REFB to AGND,
Short REFT to REFTS
Rref
Reference voltage resistor
Between REFT and REFB
Ci
Analog input capacitance
VI(ANLG) = 1.5 V + 0.07 Vrms
TA = 25°C
f(CLK) = 10 MHz,,
VI = 0.5 V to 2.5 V
TA = – 35°C to 85°C
Self-bias (1), REFT – REFB
Integral nonlinearity (INL)
TYP
MAX
0.54
0.60
0.72
1.8
2
2.4
2.25
2.5
3
140
200
260
16
EZS
Zero-scale error
∆REF = REFT – REFB = 2 V
EFS
Full-scale error
∆REF = REFT – REFB = 2 V
† Conditions marked MIN or MAX are as stated in recommended operating conditions.
UNIT
V
Ω
pF
± 0.3
± 0.75
± 0.2
± 0.5
±1
TA = 25°C
TA = – 35°C to 85°C
f(CLK) = 10 MHz,,
VI = 0.5 V to 2.5 V
Differential nonlinearity (DNL)
MIN
LSB
± 0.75
– 18
– 43
– 68
mV
– 20
0
20
mV
operating characteristics at VDDD = VDDA = 3 V, REFT = 2.5 V, REFB = 0.5 V, f(CLK) = 10 MHz,
TA = 25°C (unless otherwise noted)
PARAMETER
fconv
Maximum conversion rate
BW
Analog input bandwidth
td(D)
tAJ
Digital output delay time
td(s)
Sampling delay time
ten
Enable time, OE↓ to valid data
tdis
Disable time, OE↑ to high impedance
TEST CONDITIONS
fI = 1-kHz ramp wave form,
VI(ANLG) = 0.5 V – 2.5 V
At – 3 dB
36
CL ≤ 10 pF (see Note 1 and Figure 1)
18
MAX
UNIT
10
MSPS
MHz
MHz
30
ns
30
ps
4
ns
CL = 10 pF
15
ns
CL = 10 pF
10
ns
Input tone = 1 MHz
TA = 25°C
Full range
41
Input tone = 1.4
1 4 MHz
TA = 25°C
Full range
38
Input tone = 1.4
1 4 MHz
TA = 25°C
Full range
38
NOTE 2: CL includes probe and jig capacitance.
4
0.2
17
Aperture jitter time
Signal to noise ratio
Signal-to-noise
TYP
At – 1 dB
Spurious free dynamic range (SFDR)
SNR
MIN
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41
dB
38
37
dB
TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
PARAMETER MEASUREMENT INFORMATION
tw(H)
tw(L)
CLK (Clock)
ANALOG IN
(Input Signal)
D1 – D8
(Output Data)
N+2
N+1
N
N+4
N+3
N–3
N–2
N–1
N
N+1
tpd
Figure 1. I/O Timing Diagram
TYPICAL CHARACTERISTICS
POWER DISSIPATION
vs
SAMPLING FREQUENCY
ANALOG INPUT BANDWIDTH
0
12
TA = 25°C
VDDA = 2.7 V,
VREFB = 0.5 V,
VREFT = 2.5 V,
Fclk = 10 MHz
–1
–2
8
Gain – dB
Power Dissipation – mW
10
6
–3
–4
–5
4
–6
2
–7
0
0
2
4
6
8
10
12
TA = 25°C
VDDA = 2.7 V,
VREFB = 0.5 V,
VREFT = 2.5 V,
Fclk = 10 MHz
–8
100
Sampling Frequency – MHz
Figure 2
101
fI – Input Frequency – MHz
102
Figure 3
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TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
TYPICAL CHARACTERISTICS
SIGNAL-TO-NOISE RATIO
vs
INPUT FREQUENCY
60
TA = 25°C
VDDA = 3 V,
VREFB = 0.5 V,
VREFT = 2.5 V,
Fclk = 10 MHz
Signal-To-Noise Ratio – dB
50
40
30
20
10
0
0
0.5
1
1.5
2
2.5
3
Input Frequency – MHz
DNL – Differential Nonlinearity – LSB
Figure 4
DIFFERENTIAL NONLINEARITY
vs
SAMPLES
(Under Recommended Operating Conditions)
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
20
40
60
80
100
120
140
160
Samples
Figure 5
6
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180
200
220
240 253
TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
TYPICAL CHARACTERISTICS
EFFECTIVE NUMBER OF BITS
vs
TEMPERATURE
6.5
VDDA = 3 V,
VREFB = 0.5 V,
VREFT = 2.5 V,
Fclk = 10 MHz,
fsin = 1 MHz
Effective Number Of Bits
6.45
6.4
6.35
6.3
6.25
–40
–20
40
0
20
Ambient Temperature – °C
60
80
Figure 6
INL – Integral Nonlinearity – LSB
INTEGRAL NONLINEARITY
vs
SAMPLES
(Under Recommended Operating Conditions)
0.75
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.75
0
20
40
60
80
100
120
140
160
180
200
220
240 254
Samples
Figure 7
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TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
TYPICAL CHARACTERISTICS
Fast Fourier Transformer – dB
FAST FOURIER TRANSFORMER
vs
FREQUENCY
(Under Recommended Operating Conditions)
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200
0
0.5
1
1.5
2
2.5
3.5
3
4
4.5
5
f – Frequency – MHz
Figure 8
INTEGRAL LINEARITY ERROR
vs
FREQUENCY
DIFFERENTIAL LINEARITY ERROR
vs
FREQUENCY
1.8
1.8
INL – Integral Linearity – LSB
1.6
1.4
TA = 25°C
1.2
1
TA = –35°C
0.8
VDDD = 2.7 V,
VDDA = 2.7 V,
VREFT = 2.5 V,
VREFB = 0.5 V
1.6
DNL – Differential Linearity – LSB
VDDD = 2.7 V,
VDDA = 2.7 V,
VREFT = 2.5 V,
VREFB = 0.5 V
TA = 85°C
0.6
0.4
0.2
1.4
1.2
TA = 25°C
1
0.8
0.6
TA = 85°C
0.4
0.2
0
0
5
7
15
17
9
11
13
fCLK – Frequency – MHz
19
21
5
7
Figure 9
8
TA = –35°C
15
17
9
11
13
fCLK – Frequency – MHz
Figure 10
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19
21
TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
TYPICAL CHARACTERISTICS
INTEGRAL LINEARITY ERROR
vs
FREQUENCY
DIFFERENTIAL LINEARITY ERROR
vs
FREQUENCY
1.8
1.4
1.2
TA = 25°C
1
0.8
0.6
VDDD = 3 V,
VDDA = 3 V,
VREFT = 2.5 V,
VREFB = 0.5 V
1.6
DNL – Differential Linearity – LSB
1.6
INL – Integral Linearity – LSB
1.8
VDDD = 3 V,
VDDA = 3 V,
VREFT = 2.5 V,
VREFB = 0.5 V
TA = 85°C
0.4
TA = –35°C
0.2
1.4
1.2
1
TA = 25°C
0.8
0.6
TA = 85°C
0.4
TA = –35°C
0.2
0
5
7
15
17
9
11
13
fCLK – Frequency – MHz
19
0
21
5
7
Figure 11
19
21
Figure 12
INTEGRAL LINEARITY ERROR
vs
FREQUENCY
DIFFERENTIAL LINEARITY ERROR
vs
FREQUENCY
1.8
1.8
VDDD = 3.3 V,
VDDA = 3.3 V,
VREFT = 2.5 V,
VREFB = 0.5 V
1.4
1.2
1
TA = 25°C
0.8
TA = 85°C
0.6
VDDD = 3.3 V,
VDDA = 3.3 V,
VREFT = 2.5 V,
VREFB = 0.5 V
1.6
DNL – Differential Linearity – LSB
1.6
INL – Integral Linearity – LSB
15
17
9
11
13
fCLK – Frequency – MHz
0.4
TA = –35°C
0.2
1.4
1.2
1
TA = 25°C
0.8
0.6
TA = 85°C
0.4
0.2
0
5
7
9
11
13
15
17
fCLK – Frequency – MHz
19
21
TA = –35°C
0
5
7
Figure 13
15
17
9
11
13
fCLK – Frequency – MHz
19
21
Figure 14
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TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
TYPICAL CHARACTERISTICS
EFFECTIVE NUMBER OF BITS
vs
INPUT SINEWAVE FREQUENCY
EFFECTIVE NUMBER OF BITS
vs
INPUT SINEWAVE FREQUENCY
8
VDDD = 2.7 V,
VDDA = 2.7 V
VDDD = 3 V,
VDDA = 3 V
ENOB – Effective Number of Bits – Bits
ENOB – Effective Number of Bits – Bits
8
7.5
7
TA = –35°C
6.5
6
TA = 25°C
5.5
TA = 85°C
7.5
7
TA = –35°C
6.5
TA = 85°C
5.5
5
0
0.2
0.4
0.6
0.8
1
1.2
TA = 25°C
6
5
1.4
0
0.2
f – Input Sinewave Frequency – MHz
0.4
Figure 15
Figure 16
EFFECTIVE NUMBER OF BITS
vs
INPUT SINEWAVE FREQUENCY
ENOB – Effective Number of Bits – Bits
8
VDDD = 3.3 V,
VDDA = 3.3 V
7.5
TA = –35°C
7
TA = 25°C
TA = 85°C
6.5
6
5.5
5
0
0.2
0.4
0.6
0.8
1
1.2
f – Input Sinewave Frequency – MHz
Figure 17
10
0.6
0.8
1
1.2
f – Input Sinewave Frequency – MHz
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1.4
1.4
TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
APPLICATION INFORMATION
The following notes are design recommendations that should be used with the TLV5510.
D
D
D
D
D
D
External analog and digital circuitry should be physically separated and shielded as much as possible to
reduce system noise.
RF breadboarding or printed-circuit-board (PCB) techniques should be used throughout the evaluation and
production process. Breadboards should be copper clad for bench evaluation.
Since AGND and DGND are connected internally, the ground lead in must be kept as noise free as possible.
A good method to use is twisted-pair cables for the supply lines to minimize noise pickup. An analog and
digital ground plane should be used on PCB layouts when additional logic devices are used. The AGND
and DGND terminals of the device should be tied to the analog ground plane.
VDDA to AGND and VDDD to DGND should be decoupled with 1-µF and 0.01-µF capacitors, respectively,
placed as close as possible to the appropriate device terminals. A ceramic chip capacitor is recommended
for the 0.01-µF capacitor. Care should be exercised to assure a solid noise-free ground connection for the
analog and digital grounds.
VDDA, AGND, and ANALOG IN terminals should be shielded from the higher frequency terminals, CLK and
D0–D7. If possible, AGND traces should be placed on both sides of the ANALOG IN traces on the PCB for
shielding.
In testing or application of the device, the resistance of the driving source connected to the analog input
should be 10 Ω or less within the analog frequency range of interest.
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TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
APPLICATION INFORMATION
VDDA
3.3 V
VDDD
3.3 V
FB2
+
C10
FB3
C3
FB1
14
VDDA
DVDDD
C4
15 VDDA
DVDDD
C5
18
16
C6
From Clamp
Output
17
REFTS
REFT
D8
D7
D6
D4
C1
19
Buffer
D3
ANALOG IN
C2
R1
D2
D1
A
22
C7
23
20
21
C8
11
C9
VDDA
D5
Video Input
(2VPP)
13
REFBS
CLK
REFB
OE
AGND
DGND
AGND
DGND
10
9
8
7
6
5
4
3
12
1
2
24
D
Output Enable
Clock
LOCATION
DESCRIPTION
C1, C3, C4 – C9
0.1 µF Capacitor
C2
10 pF Capacitor
C10
47 µF Capacitor
FB1, FB2, FB3
R1
Ferrite bead
75 Ω Resistor
Figure 18. Application and Test Schematic Using Internal Reference
12
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TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
PRINCIPLES OF OPERATION
functional description
The TLV5510 is a semiflash ADC featuring two lower comparator blocks of four bits each.
As shown in Figure 19, input voltage VI(1) is sampled with the falling edge of CLK1 to the upper comparators
block and the lower comparators block(A), S(1). The upper comparators block finalizes the upper data UD(1)
with the rising edge of CLK2, and simultaneously, the lower reference voltage generates the voltage RV(1)
corresponding to the upper data. The lower comparators block (A) finalizes the lower data LD(1) with the rising
edge of CLK3. UD(1) and LD(1) are combined and output as OUT(1) with the rising edge of CLK4. According
to the above internal operation described, output data is delayed 2.5 clocks from the analog input voltage
sampling point.
Input voltage VI(2) is sampled with the falling edge of CLK2. UD(2) is finalized with the rising edge of CLK3, and
LD(2) is finalized with the rising edge of CLK4 at the lower comparators block(B). OUT(2) is output with the rising
edge of CLK5.
VI(1)
VI(2)
VI(3)
VI(4)
ANALOG IN
(Sampling Points)
CLK1
CLK2
CLK3
CLK4
CLK (Clock)
Upper Comparators Block
S(1)
C(1)
S(2)
C(2)
S(3)
C(3)
S(4)
C(4)
Upper Data
UD(0)
UD(1)
UD(2)
UD(3)
Lower Reference Voltage
RV(0)
RV(1)
RV(2)
RV(3)
S(1)
Lower Comparators Block (A)
H(1)
Lower Data (B)
D1 – D8 (Data Output)
S(3)
H(3)
LD(– 1)
Lower Data (A)
Lower Comparators Block (B)
C(1)
H(0)
C(0)
LD(1)
S(2)
LD(– 2)
OUT(– 2)
C(3)
H(2)
C(2)
LD(0)
OUT(–1)
S(4)
H(4)
LD(2)
OUT(0)
OUT(1)
Figure 19. Internal Functional Timing Diagram
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13
TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
PRINCIPLES OF OPERATION
functional description (continued)
The MSB comparator block converts on the falling edge of each applied clock cycle. The LSB comparator blocks
CB-A and CB-B convert on the falling edges of the first and second following clock cycles, respectively. The
timing diagram of the conversion algorithm is shown in Figure 19.
analog input operation
The analog input stage to the TLV5510 is a chopper-stabilized comparator and is equivalently shown below:
φ2
S2
φ1
To Encoder Logic
VDDA
Cs
φ2
S3
φ1
φ1
ANALOG IN
S1
Vref(N)
To Encoder Logic
φ2
Cs
φ2
S(N)
φ1
To Encoder Logic
Cs
Figure 20. External Connections for Using the Internal Reference Resistor Divider
Figure 20 depicts the analog input for the TLV5510. The switches shown are controlled by two internal clocks,
φ1 and φ2. These are nonoverlapping clocks that are generated from the CLK input. During the sampling period,
φ1, S1 is closed and the input signal is applied to one side of the sampling capacitor, Cs. Also during the sampling
period, S2 through S(N) are closed. This sets the comparator input to approximately 2.5 V. The delta voltage
is developed across Cs. During the comparison phase, φ2, S1 is switched to the appropriate reference voltage
for the bit value N, i.e., Vref(N). S2 is opened and Vref(N) – VCs toggles the comparator output to the appropriate
digital 1 or 0. The small resistance values for the switch, S1, and small value of the sampling capacitor combine
to produce the wide analog input bandwidth of the TLV5510. The source impedance driving the analog input
of the TLV5510 should be less than 100 Ω across the range of input frequency spectrum.
reference inputs – REFB, REFT, REFBS, REFTS
The range of analog inputs that can be converted are determined by REFB and REFT, REFT being the
maximum reference voltage and REFB being the minimum reference voltage. The TLV5510 is tested with
REFT = 2.5 V or 2 V and REFB = 0.5 V or 0 V producing a 2-V full-scale range. The TLV5510 can operate with
REFT – REFB = 2.4 V, but the power dissipation in the reference resistor increases significantly (49 mW at 3.3 V
nominally). It is recommended that a 0.1 µF capacitor be attached to REFB and REFT whether using externally
or internally generated voltages.
14
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TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
PRINCIPLES OF OPERATION
internal reference voltage conversion
Three internal resistors allow the device to generate an internal reference voltage. These resistors are brought
out on terminals VDDA, REFTS, REFT, REFB, REFBS, and AGND. Two different bias voltages are possible
without the use of external resistors.
The internal resistors are provided to develop REFT and REFB as listed in Table 1 (bias option 1) with only two
external connections. This is developed with a 3-resistor network connected to VDDA. When using this feature,
connect REFT to REFTS and connect REFB to REFBS. For applications where the variance associated with
VDDA is acceptable, this internal voltage reference saves space and cost (see Figure 21).
A second internal bias option (bias two option) is shown in Figure 22. Using this scheme REFB = AGND and
REFT is as shown in Table 1 (bias option 2). These bias voltage options can be used to provide the values listed
in the following table.
Table 1. Bias Voltage Options for Different VDDA
BIAS OPTION
BIAS VOLTAGE
VDDA
2.7 V
1
2
VREFB
0.54
VREFT
2.34
VREFT – VREFB
1.8
3V
0.6
2.60
2
3.3 V
0.66
2.86
2.2
3.6 V
0.72
3.12
2.4
2.7 V
AGND
2.25
2.25
3V
AGND
2.5
2.5
3.3 V
AGND
2.75
2.75
3.6 V
AGND
3
3
To use the internally-generated reference voltage, terminal connections should be made as shown in
Figure 21 or Figure 22.
TLV5510
VDDA
18
R1
40 Ω NOM
REFTS
16
17
0.1 µF
REFT
REFB
2.63 V dc
Rref
200 Ω NOM
23
22
0.1 µF
REFBS
AGND
R2
60 Ω NOM
21
Figure 21. External Connections Using the Internal Bias One Option
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15
TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
PRINCIPLES OF OPERATION
TLV5510
18
VDDA
(Analog Supply)
R1
40 Ω NOM
REFTS
16
17
0.1 µF
REFT
REFB
Rref
200 Ω NOM
23
22
REFBS
R2
60 Ω NOM
AGND
21
Figure 22. External Connections for Using the Internal Reference Resistor Divider
functional operation
The TLV5510 functions as shown in the Table 2.
Table 2. Functional Operation
16
DIGITAL OUTPUT CODE
INPUT SIGNAL
VOLTAGE
STEP
REFT
255
1
1
1
1
1
1
1
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
128
1
0
0
0
0
0
0
0
•
127
0
1
1
1
1
1
1
1
•
•
•
•
•
•
•
•
•
•
MSB
LSB
•
•
•
•
•
•
•
•
•
•
REFB
0
0
0
0
0
0
0
0
0
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TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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17
TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
MECHANICAL DATA
NS (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
PINS **
14
16
20
24
A MAX
10,50
10,50
12,90
15,30
A MIN
9,90
9,90
12,30
14,70
DIM
0,51
0,35
1,27
14
0,25 M
8
0,15 NOM
5,60
5,00
8,20
7,40
Gage Plane
1
7
0,25
0°– 10°
A
1,05
0,55
Seating Plane
2,00 MAX
0,05 MIN
0,10
4040062 / B 2/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15.
18
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