TPS53126 www.ti.com........................................................................................................................................................................................................ SLUS909 – MAY 2009 DUAL SYNCHRONOUS STEP-DOWN CONTROLLER FOR LOW VOLTAGE POWER RAILS FEATURES APPLICATIONS • D-CAP2™ Mode Control – Fast Transient Response – No External Parts Required For Loop Compensation – Compatible with Ceramic Output Capacitors • High Initial Reference Accuracy (±1%) • Low Output Ripple • Wide Input Voltage Range: 4.5 V to 24 V • Output Voltage Range: 0.76 V to 5.5 V • Low-Side RDS(on) Loss-Less Current Sensing • Adaptive Gate Drivers with Integrated Boost Diode • Internal 1.2 ms Voltage-Servo Soft Start • Pre-Biased Soft Start • Selectable Switching Frequency: 350 kHz / 700 kHz • Cycle-by-Cycle Over-Current Limiting Control • 30 mV to 300 mV OCP Threshold Voltage • Thermally Compensated OCP by 4000 ppm/C° at ITRIP • 1 2 Point-of-Load Regulation in Low Power Systems for Wide Range of Applications – Digital TV Power Supply – Networking Home Terminal – Digital Set Top Box (STB) – DVD Player/Recorder – Gaming Consoles and Other DESCRIPTION The TPS53126 is a dual, adaptive on-time, D-CAP2™ mode synchronous Buck controller. The TPS53126 enables system designers to complete the suite of various end equipment's power bus regulators with a cost effective, low external component count, and low standby current solution. The main control loop for the TPS53126 uses the D-CAP2™ mode control which provides a very fast transient response with no external components. The TPS53126 also has a proprietary circuit that enables the device to adapt to both low equivalent series resistance (ESR) output capacitors, such as POSCAP or SP-CAP, and ultra-low ESR ceramic capacitors. The device provides convenient and efficient operation with input voltages from 4.5 V to 24 V and output voltages from 0.76 V to 5.5 V. The TPS53126 is available in 4mm x 4mm 24 pin QFN (RGE) or 24 pin TSSOP (PW) packages and is specified from –40°C to 85°C ambient temperature range. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. D-CAP2 is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated TPS53126 SLUS909 – MAY 2009........................................................................................................................................................................................................ www.ti.com QFN APPLICATION DIAGRAM Input Voltage 4.5V to 24V C9 10mF SGND Q3 FDS8878 4 3 2 1 TEST1 GND VFB1 VO1 7 EN2 C5 0.1mF VBST1 23 8 VBST2 PowerPAD 9 DRVH2 PGND TRI P1 PGND1 19 VIN 12 PGND2 VREG5 DRVL1 20 13 14 15 16 17 18 C8 1 mF Q1 FDS8878 L1 SPM6530T 1.5mH SW1 21 11 DRVL2 R6 3.3kW C2 0.1mF DRVH1 22 TPS53126 RGE (QFN) 10 SW2 Q4 FDS8690 EN1 24 V5FILT C4 22mF ´ 4 5 TEST2 VO2 1.05V/4A L2 SPM6530T 1.5mH 6 TRIP2 C6 10mF R2 R1 10kW 13kW VFB2 PGND R5 10kW VO2 R4 3.52kW C7 4.7mF R3 4.7kW Q2 FDS8690 C3 10mF VO1 1.8V/4A C1 22mF ´ 4 PGND PGND SGND 2 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53126 TPS53126 www.ti.com........................................................................................................................................................................................................ SLUS909 – MAY 2009 TSSOP APPLICATION DIAGRAM Q1 FDS8878 C2 0.1mF R1 13kW R2 10kW 1 DRVH1 SW1 24 2 VBST1 DRVL1 23 3 EN1 PGND1 22 4 VO1 TRIP1 21 5 VFB1 C3 10mF L1 SPM6530T 1.5mH Q2 FDS8690 R3 3.3kW PGND Input Voltage VIN 20 C7 4.7mF 6 GND R5 10kW VO1 1.8V/4A C1 22mF ´ 4 TPS53126 PW (TSSOP) VREG5 19 7 TEST1 V5FILT 18 8 VFB2 TEST2 17 SGND 4.5V to 24V C9 10mF C8 1 mF PGND R6 4.3kW R4 3.52kW 9 VO2 TRIP2 16 SGND 10 EN2 PGND2 15 11 VBST2 DRVL2 14 12 DRVH2 SW2 13 Q4 FDS8690 C5 0.1mF C4 22mF ´ 4 L2 SPM6530T 1.5mH Q3 FDS8878 C6 10mF PGND VO2 1.05V/4A ORDERING INFORMATION (1) (2) TA PACKAGE Plastic Quad Flat Pack (QFN) –40°C to 85°C TSSOP (1) (2) ORDERING PART NUMBER PINS TPS53126RGET TPS53126RGER TPS53126PWR OUTPUT SUPPLY ECO PLAN Tape-and-Reel 24 TPS53126PW Tape-and-Reel Tape-and-Reel Green (RoHS and no Sb/Br) Tube For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. All packaging options have Cu NIPDAU lead/ball finish. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53126 3 TPS53126 SLUS909 – MAY 2009........................................................................................................................................................................................................ www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE Input voltage range Output voltage range VIN, EN1, EN2 –0.3 to 26 VBST1, VBST2 –0.3 to 32 VBST1, VBST2 (wrt SWx) –0.3 to 6 V5FILT, VFB1, VFB2, TRIP1, TRIP2, VO1, VO2, TEST1, TEST2 –0.3 to 6 SW1, SW2 –2 to 26 DRVH1, DRVH2 –1 to 32 DRVH1, DRVH2 (wrt SWx) –0.3 to 6 DRVL1, DRVL2, VREG5 –0.3 to 6 PGND1, PGND2 UNIT V V –0.3 to 0.3 TA Operating ambient temperature range –40 to 85 °C TSTG Storage temperature range –55 to 150 °C TJ Junction temperature range –40 to 150 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE (2 OZ. TRACE AND COPPER PAD WITH SOLDER) PACKAGE TA < 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 85°C POWER RATING 24 pin QFN 2.33 W 23.3 mW/°C 0.93 W 24 pin TSSOP 0.778 W 7.8 mW/°C 0.31 W RECOMMENDED OPERATING CONDITIONS Supply input voltage range Input voltage range Output voltage range MIN MAX VIN 4.5 24 V5FILT 4.5 5.5 VBST1, VBST2 –0.1 30 VBST1, VBST2 (wrt SWx) –0.1 5.5 VFB1, VFB2, VO1, VO2, TEST1, TEST2 –0.1 5.5 TRIP1, TRIP2 –0.1 0.3 EN1, EN2 –0.1 24 SW1, SW2 –1.8 24 DRVH1, DRVH2 –0.1 30 VBST1, VBST2 (wrt SWx) –0.1 5.5 DRVL1, DRVL2, VREG5 –0.1 5.5 PGND1, PGND2 –0.1 0.1 UNIT V V V TA Operating free-air temperature –40 85 °C TJ Operating junction temperature –40 125 °C ELECTRICAL CHARACTERISTICS over recommended free-air temperature range, VIN = 12 V (Unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT 450 800 µA 30 60 µA SUPPLY CURRENT IIN VIN supply current VIN current, TA = 25°C, VREG5 tied to V5FLT, EN1 = EN2 = 5V, VFB1 = VFB2 = 0.8V, SW1 = SW2 = 0.5V IVINSDN VIN shutdown current VIN current, TA = 25°C, No load, EN1 = EN2 = 0 V, VREG5 = ON 4 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53126 TPS53126 www.ti.com........................................................................................................................................................................................................ SLUS909 – MAY 2009 ELECTRICAL CHARACTERISTICS (continued) over recommended free-air temperature range, VIN = 12 V (Unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT VFB VOLTAGE and DISCHARGE RESISTANCE VBG Bandgap initial regulation accuracy VVFBTHLx VFBx threshold voltage VVFBTHHx VFBx threshold voltage IVFB VFB input current VFBx = 0.8 V, TA = 25°C RDischg VO discharge resistance ENx = 0 V, VOx = 0.5 V, TA = 25°C TA = 25°C -1.0% TA = 25°C, TEST2 = 0 V, SWinj = OFF 755 TA = –40°C to 85°C, TEST2 = 0 V, SWinj = OFF (1) 752 TA = 25°C, TEST2 = V5FILT, SWinj = OFF 748 TA = –40°C to 85°C, TEST2 = V5FILT, SWinj = OFF (1) 745 1.0% 765 775 778 758 768 771 mV mV –0.01 ±0.1 µA 40 80 Ω 5.0 5.2 V VREG5 OUTPUT VVREG5 VREG5 output voltage TA = 25°C, 5.5 V < VIN < 24 V, 0 < IVREG5 < 10 mA VLN5 Line regulation 5.5 V < VIN < 24 V, IVREG5 = 10 mA 20 mV VLD5 Load regulation 1 mA < IVREG5 < 10 mA 40 mV IVREG5 Output current VIN = 5.5 V, VVREG5 = 4 V, TA = 25°C 4.8 170 mA OUTPUT: N-CHANNEL MOSFET GATE DRIVERS RDRVH DRVH resistance RDRVL DRVL resistance TD Dead time Source, IDRVHx = –100 mA 5.5 11 Sink, IDRVHx = 100 mA 2.5 5 Source, IDRVLx = –100 mA 4 8 Sink, IDRVLx = 100 mA 2 4 DRVHx-low to DRVLx-on 20 50 80 DRVLx-low to DRVHx-on 20 40 80 0.7 Ω Ω ns INTERNAL BOOST DIODE VFBST Forward voltage VVREG5-VBSTx, IF = 10 mA, TA = 25°C 0.8 0.9 V IVBSTLK VBST leakage current VBSTx = 29 V, SWx = 24 V, TA = 25°C 0.1 1 µA ON-TIME TIMER CONTROL TON1L CH1 on time SW1 = 12 V, VO1 = 1.8 V, TEST2 = 0 V 490 ns TON2L CH2 on time SW2 = 12 V, VO2 = 1.8 V, TEST2 = 0 V 390 ns TOFF1L CH1 min off time SW1 = 0.7 V, TA = 25°C, VFB1 = 0.7 V, TEST2 = 0 V 285 ns TOFF2L CH2 min off time SW2 = 0.7 V, TA = 25°C, VFB2 = 0.7 V, TEST2 = 0 V 285 ns TON1H CH1 on time SW1 = 12 V, VO1 = 1.8 V, TEST2 = V5FILT 165 ns TON2H CH2 on time SW2 = 12 V, VO2 = 1.8 V, TEST2 = V5FILT 140 ns TOFF1H CH1 min off time SW1 = 0.7 V, TA = 25°C, VFB1 = 0.7 V, TEST2 = V5FILT 216 ns TOFF2H CH2 min off time SW2 = 0.7 V, TA = 25°C, VFB2 = 0.7 V, TEST2 = V5FILT 216 ns SOFT START Tss Internal SS time Internal soft start VFBx = 0.735 V 0.85 1.2 1.4 Wake up 3.7 4.0 4.3 Hysteresis 0.2 0.3 0.4 2.0 ms UVLO VUV5VFILT V5FILT UVLO threshold V LOGIC THRESHOLD VENH ENx H-level input voltage EN VENL ENx L-level input voltage EN V 0.3 V 11.5 µA CURRENT SENSE ITRIP (1) TRIP source current VTRIPx = 0.1 V, TA = 25°C 8.5 10 Ensured by design. Not production tested. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53126 5 TPS53126 SLUS909 – MAY 2009........................................................................................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS (continued) over recommended free-air temperature range, VIN = 12 V (Unless otherwise noted) PARAMETER TCITRIP CONDITIONS VOCLoff OCP compensation offset Current limit threshold setting range VRtrip MIN On the basis of 25°C (2) ITRIP temperature coefficient TYP MAX 4000 (VTRIPx-GND-VPGNDx-SWx) voltage, VTRIPx-GND = 60 mV, TA = 25°C –15 (VTRIPx-GND-VPGNDx-SWx) voltage, VTRIPx-GND = 60 mV –20 20 30 300 0 UNIT ppm/°C 15 mV VTRIPx-GND voltage mV OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION VOVP Output OVP trip threshold TOVPDEL Output OVP prop delay time VUVP Output UVP trip threshold TUVPDEL Output UVP delay time TUVPEN Output UVP enable delay time OVP detect 110% 115% UVP detect 65% 70% 120% µs 1.5 Hysteresis (recovery < 20 µs) 75% 10% UVP enable delay 17 30 40 µs 1.2 2 2.5 ms THERMAL SHUTDOWN TSDN (2) (3) Shutdown temperature (3) Thermal shutdown threshold Hysteresis 150 (3) 20 °C Ensured by design. Not production tested. Ensured by design. Not production tested. DEVICE INFORMATION PIN FUNCTIONS PIN NAME QFN 24 TSSOP 24 I/O DESCRIPTION VBST1, VBST2 23, 8 2, 11 I Supply input for high-side NFET driver (Boost Terminal). Bypass to SWx with a high-quality 0.1µF ceramic capacitor. An external schottky diode can be added if forward drop is critical to drive the high-side FET. EN1, EN2 24, 7 3, 10 I Channel 1 and channel 2 high level enable pins. VO1, VO2 1, 6 4, 9 I Output voltage inputs for on-time adjustment and output discharge. Connect directly to the output voltage. VFB1, VFB2 2, 5 5, 8 I D-CAP2 feedback inputs. Connect to output voltage with resistor divider. GND 3 6 I Signal ground pin. Connect to PGND1, PGND2 and system ground at a single point. DRVH1, DRVH2 22, 9 1, 12 O High-side MOSFET gate driver outputs. SWx referenced drivers switch between SWx (OFF) and VBSTx (ON). SW1, SW2 21, 10 24, 13 I/O Switch node connections for both the high-side drivers and the current comparators. DRVL1, DRVL2 20, 11 23, 14 O Low-side MOSFET gate driver outputs. PGND referenced drivers switch between PGNDx (OFF) and VREG5 (ON). PGND1, PGND2 19, 12 22, 15 I/O Power ground connections for both the low-side drivers and the current comparators. Connect PGND1, PGND2 and GND strongly together near the IC. TRIP1, TRIP2 18, 13 21, 16 I Over current trip point programming pin. Connect to GND with a resistor to GND to set threshold for low-side RDS(on) current limit. VIN 17 20 I Supply Input for 5V linear regulator. V5FILT 15 18 I 5V supply input for the entire control circuit except the MOSFET drivers. Bypass to GND with a minimum 1.0µF, high-quality ceramic capacitor. V5FILT is connected to VREG5 via an internal 10Ω resistor. VREG5 16 19 O Output of 5V linear regulator and supply for MOSFET drivers. Bypass to GND with a minimum 4.7µF high-quality ceramic capacitor. VREG5 is connected to V5FILT via an internal 10Ω resistor. 6 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53126 TPS53126 www.ti.com........................................................................................................................................................................................................ SLUS909 – MAY 2009 PIN FUNCTIONS (continued) PIN NAME QFN 24 TSSOP 24 I/O DESCRIPTION TEST1 4 7 O Test interface pin, not used during application. Connect directly to GND. TEST2 14 17 I Frequency select pin. Connect to GND for 350kHz switching. Connect to V5FILT for 700kHz switching. TSSOP (PW) Package (Top View) PGND1 DRVL1 VO1 1 18 VFB1 2 17 VIN GND 3 16 VREG5 TRIP1 TEST1 4 15 V5FILT VFB2 5 14 TEST2 13 12 10 SW2 DRVL2 9 DRVH2 PGND2 8 VBST2 11 7 6 EN2 VO2 DRVH1 VBST1 EN1 VO1 VFB1 GND TEST1 VFB2 VO2 EN2 VBST2 DRVH2 19 SW1 21 20 DRVH1 22 VBST1 23 24 EN1 QFN (RGE) Package (Top View) TRIP2 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 SW1 DRVL1 PGND1 TRIP1 VIN VREG5 V5FILT TEST2 TRIP2 PGND2 DRVL2 SW2 FUNCTIONAL BLOCK DIAGRAM VREG5 4V/3.7V TSD V5FILT VO1 VO2 VBST1 VBST2 Ref DRVH1 Ref BGR Switcher Controller DRVH2 Switcher Controller Fault SW2 DRVL1 Sdn Sdn DRVL2 PGND1 ON2 Fault ON1 SW1 PGND2 TRIP2 VFB2 TEST2 GND EN2 EN1 TEST1 VFB1 TRIP1 EN/SS Control Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53126 7 TPS53126 SLUS909 – MAY 2009........................................................................................................................................................................................................ www.ti.com –30% UV V5FILT GND OV 15% Ref SSx ERR COMP V5OK VFBx VREG5 GND Control Logic TRIPx VBSTx OCP LL DRVHx SWx 1 Shot PGNDx XCON VREG5 DRVLx PGNDx LLx VOx VOx PGNDx 8 ENx On/Off Time Minimun On/Off OVP/UVP, Discharge Control Submit Documentation Feedback Fault Sdn Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53126 TPS53126 www.ti.com........................................................................................................................................................................................................ SLUS909 – MAY 2009 DETAILED DESCRIPTION PWM OPERATION The main control loop of the TPS53126 is an adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2 mode control. D-CAP2 Mode control combines constant on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one shot timer expires. This one shot timer is set by the converter input voltage ,VIN, and the output voltage ,VO, to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the reference voltage. An internal ramp is added to the reference voltage to simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP mode control. DRIVERS Each SMPS of the TPS53126 contains 2 high-current resistive MOSFET drivers. The Low-side driver is a ground referenced, VREG5 powered driver designed to drive the gate of a high-current, low RDS(on) N-channel MOSFET whose source is connected to PGND. The High-side Driver is a floating SW referenced VBST powered driver designed to drive the gate of a high-current, low RDS(on) N-channel MOSFET. To maintain the BST voltage during the high-side driver ON time, a capacitor is placed from SW to VBST. Each driver draws average current equal to Gate Charge (Qg AT Vgs = 5V) times Switching Frequency (fsw). To prevent cross-conduction, there is a narrow dead-time when both high-side and low-side drivers are OFF between each driver transition. During this time the inductor current is carried by one of the MOSFETs body diodes. PWM FREQUENCY AND ADAPTIVE ON-TIME CONTROL The TPS53126 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The TPS53126 runs with pseudo-constant frequency by using the input voltage and output voltage to set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage, therefore, when the duty ratio is VOUT/VIN, the frequency is constant. 5 VOLT REGULATOR The TPS53126 has an internal 5V Low-Dropout (LDO) Regulator to provide a regulated voltage for all four drivers and the ICs internal logic. A capacitor from VREG5 to GND is required to stabilize the internal regular. An internal 10Ω resistor from VREG5 filters the regulator output to the IC’s analog and logic input voltage, V5FILT. An additional capacitor is required from V5FILT to GND to filter switching noise from VREG5. SOFT START The TPS53126 has an internal, 1.2ms, voltage servo soft-start for each channel. When the ENx pin becomes high, an internal DAC begins ramping up the reference voltage to the PWM comparator. Smooth control of the output voltage is maintained during start up. As the TPS53126 shares one DAC with both channels, if ENx pin is set to high while another channel is starting up, soft start is postponed until another channel soft start has completed. If both of EN1 and EN2 are set high at a same time, both channels start up at same time. PRE-BIAS SUPPORT The TPS53126 supports pre-bias start-up without sinking current from the output capacitor. When enabled, the low-side driver is held off until the soft-start commands a voltage higher than the pre-bias level (internal soft-start becomes greater than feedback voltage [VFB]), then the TPS53126 slowly activates synchronous rectification by limiting the first DRVL pulses with a narrow on-time. This limited on-time is then incremented on a cycle-by-cycle basis until it coincides with the full 1-D off-time. This scheme prevents the initial sinking of current from the pre-bias output, and ensure that the output voltage (VOUT) starts and ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to normal mode operation. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53126 9 TPS53126 SLUS909 – MAY 2009........................................................................................................................................................................................................ www.ti.com SWITCHING FREQUENCY SELECTION The TPS53126 allows the user to select from 2 different switching frequencies by connecting the TEST2 pin to either GND or V5FILT. Connect TEST2 to GND for a switching frequency (fsw) of 350KHz. Connect TEST2 to V5FILT for a switching frequency of 700KHz. OUTPUT DISCHARGE CONTROL The TPS53126 discharges the outputs when ENx is low, or when the controller is turned off by the protection functions (OVP, UVP, UVLO, and thermal shutdown). The device discharges an output using an internal 40-Ω MOSFET which is connected to VOx and PGNDx. The external low-side MOSFET is not turned on during the output discharge operation to avoid the possibility of causing negative voltage at the output. This discharge ensures that, on start, the regulated voltage always initializes from zero volts. OVERCURRENT LIMIT The TPS53126 has a cycle-by-cycle over current limit feature. The over current limits the inductor valley current by monitoring the voltage drop across the low-side MOSFET RDS(on) during the low-side driver on-time. If the inductor current is larger than the over current limit (OCL), the TPS53126 delays the start of the next switching cycle until the sensed inductor current falls below the OCL current. MOSFET RDS(on) current sensing is used to provide an accuracy and cost effective solution without external devices. To program the OCL, the TRIPx pin should be connected to GND through a trip voltage setting resistor, according to the following equations. V (VIN - Vo) ´ O Vtrip = IOCL ´ RDS(on) 2 ´ L1 ´ ¦ sw VIN (1) R trip (kW) = Vtrip (mV) Itrip (mA) (2) The trip voltage should be between 30mV to 300mV over all operational temperature, including the 4000ppm/°C temperature slope compensation for the temperature dependency of the RDS(on). If the load current exceeds the over-current limit, the voltage will begin to drop. If the over-current conditions continues the output voltage will fall below the under voltage protection threshold and the TPS53126 will shut down. OVER/UNDER VOLTAGE PROTECTION The TPS53126 monitors the output voltage via the feedback voltage to detect over and under voltage. When the feedback voltage becomes higher than 115% of the reference voltage, the TPS53126 turns off the high-side MOSFET driver, turns on the low-side MOSFET driver and latches off. When the feedback voltage becomes lower than 70% of the reference voltage, the TPS53126 begins an internal UVP delay counter. After 30µs, the TPS53126 turns off both top and bottom MOSFET drivers and latches off. The UVP function is enabled approximately 2.0ms after power-on to prevent detecting UVP during soft-start. Both OVP and UVP latch conditions are reset when V5FILT triggers UVLO or the ENx pin goes low. UVLO PROTECTION The TPS53126 has under voltage lock out protection (UVLO) that monitors the voltage of V5FILT pin. When the V5FILT voltage is lower than UVLO threshold voltage, the device is shut off. During shut-off, VREG5 and all output drivers are OFF and output discharge is ON. The UVLO is non-latch protection. THERMAL SHUTDOWN The TPS53126 includes an over temperature protection shut-down feature. If the TPS53126 die temperature exceeds the OTP threshold (typically 150°C), both the high-side and low-side drivers are shut off, the output voltage discharge function is enabled and then the device is shut off until the die temperature drops. Thermal shutdown is a non-latch protection. 10 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53126 TPS53126 www.ti.com........................................................................................................................................................................................................ SLUS909 – MAY 2009 TYPICAL CHARACTERISTICS VIN SUPPLY CURRENT vs JUNCTION TEMPERATURE VIN SHUTDOWN CURRENT vs JUNCTION TEMPERATURE 60 800 IVINSDN − VIN Shutdown Current − µA IVIN − VIN Supply Current − µA 700 600 500 400 300 200 50 40 30 20 10 100 0 −50 0 50 100 0 −50 150 TJ − Junction Temperature − °C 0 50 100 TJ − Junction Temperature − °C G001 Figure 1. Figure 2. TRIP SOURCE CURRENT vs JUNCTION TEMPERATURE VREG5 VOLTAGE vs JUNCTION TEMPERATURE 20 150 G002 5.07 VVREG5 − VREG5 Voltage − V ITRIP − TRIP Source Current − µA 5.06 15 10 5 5.05 5.04 5.03 5.02 5.01 0 −50 0 50 100 TJ − Junction Temperature − °C 150 5.00 −50 G003 Figure 3. 0 50 100 TJ − Junction Temperature − °C 150 G004 Figure 4. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53126 11 TPS53126 SLUS909 – MAY 2009........................................................................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) VREG5 VOLTAGE vs INPUT VOLTAGE VFB1 VOLTAGE (CH1 = 1.8 V, IO = 4 A) vs JUNCTION TEMPERATURE 5.5 0.800 0.795 0.790 VVFB1 − VFB1 Voltage − V VVREG5 − VREG5 Voltage − V 5.3 IOUT = 4A VO1 = 1.8V 5.1 4.9 4.7 0.785 TEST2 = GND 0.780 0.775 0.770 0.765 0.760 0.755 4.5 0 5 10 15 20 VIN − Input Voltage − V 0.750 −50 25 G005 VFB2 VOLTAGE (CH2 = 1.05 V, IO = 4 A) vs JUNCTION TEMPERATURE VFB1 VOLTAGE (CH1 = 1.8 V, IO = 4 A) vs JUNCTION TEMPERATURE IOUT = 4A VO2 = 1.05V 0.795 G006 IOUT = 4A VO1 = 1.8V 0.790 VVFB1 − VFB1 Voltage − V VVFB2 − VFB2 Voltage − V 150 0.800 0.785 0.780 TEST2 = GND 0.775 0.770 0.765 0.785 0.780 0.775 0.770 TEST2 = V5FILT 0.765 0.760 0.760 0.755 0.755 0 50 100 150 TJ − Junction Temperature − °C 0.750 −50 G007 Figure 7. 12 100 Figure 6. 0.790 0.750 −50 50 Figure 5. 0.800 0.795 0 TJ − Junction Temperature − °C 0 50 100 TJ − Junction Temperature − °C 150 G008 Figure 8. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53126 TPS53126 www.ti.com........................................................................................................................................................................................................ SLUS909 – MAY 2009 TYPICAL CHARACTERISTICS (continued) VFB2 VOLTAGE (CH2 = 1.05 V, IO = 4 A) vs JUNCTION TEMPERATURE VFB1 VOLTAGE (CH1 = 1.8 V) vs INPUT VOLTAGE 0.800 0.800 IOUT = 4A VO2 = 1.05V 0.795 0.790 VVFB1 − VFB1 Voltage − V VVFB2 − VFB2 Voltage − V 0.790 0.785 0.780 0.775 TEST2 = V5FILT 0.770 0.765 0.785 0.780 TEST2 = GND 0.775 0.770 0.765 0.760 0.760 0.755 0.755 0.750 −50 0.750 0 50 100 150 TJ − Junction Temperature − °C 0 5 10 15 20 VIN − Input Voltage − V G009 25 G010 Figure 9. Figure 10. VFB2 VOLTAGE (CH2 = 1.05 V) vs INPUT VOLTAGE VFB1 VOLTAGE (CH1 = 1.8 V) vs INPUT VOLTAGE 0.800 0.800 VO2 = 1.05V 0.795 VO1 = 1.8V 0.795 0.790 VVFB1 − VFB1 Voltage − V 0.790 VVFB2 − VFB2 Voltage − V VO1 = 1.8V 0.795 0.785 0.780 TEST2 = GND 0.775 0.770 0.765 0.785 0.780 0.775 0.770 0.765 0.760 0.760 0.755 0.755 0.750 TEST2 = V5FILT 0.750 0 5 10 15 VIN − Input Voltage − V 20 25 0 G011 Figure 11. 5 10 15 20 VIN − Input Voltage − V 25 G012 Figure 12. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53126 13 TPS53126 SLUS909 – MAY 2009........................................................................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) VFB2 VOLTAGE (CH2 = 1.05 V) vs INPUT VOLTAGE 0.800 VO2 = 1.05V 0.795 VVFB2 − VFB2 Voltage − V 0.790 0.785 0.780 0.775 TEST2 = V5FILT 0.770 0.765 0.760 0.755 0.750 0 5 10 15 20 25 VIN − Input Voltage − V G013 Figure 13. TYPICAL APPLICATION PERFORMANCE SWITCHING FREQUENCY (IO1 = 3A) vs INPUT VOLTAGE (CH1) SWITCHING FREQUENCY (IO2 = 3A) vs INPUT VOLTAGE (CH2) 800 800 700 TEST2 = V5FILT fSW − Switching Frequency − kHz fSW − Switching Frequency − kHz 700 600 500 400 TEST2 = GND 300 200 IOUT = 3A VO1 = 1.8V 100 600 TEST2 = V5FILT 500 400 300 TEST2 = GND 200 IOUT = 3A VO2 = 1.05V 100 0 0 0 5 10 15 VIN − Input Voltage − V 20 25 0 G014 Figure 14. 14 5 10 15 VIN − Input Voltage − V 20 25 G015 Figure 15. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53126 TPS53126 www.ti.com........................................................................................................................................................................................................ SLUS909 – MAY 2009 TYPICAL APPLICATION PERFORMANCE (continued) OUTPUT VOLTAGE (VIN = 12V) vs OUTPUT CURRENT (CH2) 1.85 1.10 1.84 1.09 1.83 1.08 1.82 VOUT − Output Voltage − V VOUT − Output Voltage − V OUTPUT VOLTAGE (VIN = 12V) vs OUTPUT CURRENT (CH1) TEST2 = V5FILT 1.81 1.80 TEST2 = GND 1.79 1.78 1.75 0.0 1.06 TEST2 = V5FILT 1.05 TEST2 = GND 1.04 1.03 1.02 1.77 1.76 1.07 VIN = 12V VO1 = 1.8V 0.5 1.01 1.0 1.5 2.0 2.5 3.0 3.5 4.0 IOUT − Output Current − A VIN = 12V VO2 = 1.05V 1.00 0.0 0.5 1.0 1.5 2.0 G016 Figure 16. 3.0 3.5 4.0 G017 Figure 17. VO1 (50mV/div) VO1 (50mV/div) TEST2 = V5FILT 700kHz Selection TEST2 = GND 350kHz Selection Iout1 (2A/div) Iout1 (2A/div) t − time − 100µs/div 2.5 IOUT − Output Current − A COUT = 22µF × 4 t − time − 100µs/div COUT = 22µF × 2 G018 Figure 18. 1.8V LOAD TRANSIENT RESPONSE (CH1,TEST2 = GND) G019 Figure 19. 1.8V LOAD TRANSIENT RESPONSE (CH1,TEST2 = V5FILT) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53126 15 TPS53126 SLUS909 – MAY 2009........................................................................................................................................................................................................ www.ti.com TYPICAL APPLICATION PERFORMANCE (continued) VO2 (50mV/div) VO2 (50mV/div) TEST2 = GND 350kHz Selection TEST2 = V5FILT 700kHz Selection Iout2 (2A/div) t − time − 100µs/div Iout2 (2A/div) COUT = 22µF × 4 t − time − 100µs/div G020 Figure 20. 1.05V LOAD TRANSIENT RESPONSE (CH2,TEST2 = V5FILT) COUT = 22µF × 2 G021 Figure 21. 1.05V LOAD TRANSIENT RESPONSE (CH2,TEST2 = V5FILT) EN2 (5V/div) EN1 (10V/div) VO2 (0.2V/div) VO1 (0.5V/div) TEST2 = GND 350kHz Selection TEST2 = V5FILT 700kHz Selection G022 Figure 22. 1.8V START-UP WAVEFORMS 16 G023 Figure 23. 1.05V START-UP WAVEFORMS Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53126 TPS53126 www.ti.com........................................................................................................................................................................................................ SLUS909 – MAY 2009 TYPICAL APPLICATION PERFORMANCE (continued) 1.8V EFFICIENCY (VIN = 12V) vs OUTPUT CURRENT (CH1) 1.05V EFFICIENCY (VIN = 12V) vs OUTPUT CURRENT (CH2) 100 100 TEST2 = GND 350kHz Selection 80 TEST2 = V5FILT 700kHz Selection η − Efficiency − % η − Efficiency − % 80 60 40 20 60 40 20 VIN = 12V VO1 = 1.8V VIN = 12V VO2 = 1.05V 0 0 0 1 2 3 4 0 1 2 3 4 IOUT − Output Current − A G024 G025 Figure 24. Figure 25. 1.8V OUTPUT VOLTAGE (IO = 3A) vs INPUT VOLTAGE 1.05V OUTPUT VOLTAGE (IO = 3A) vs INPUT VOLTAGE 1.90 1.15 1.88 1.13 1.86 1.11 VOUT − Output Voltage − V VOUT − Output Voltage − V IOUT − Output Current − A 1.84 TEST2 = V5FILT 1.82 1.80 TEST2 = GND 1.78 1.76 1.09 TEST2 = V5FILT 1.07 1.05 TEST2 = GND 1.03 1.01 0.99 1.74 IOUT = 3A VO1 = 1.8V 1.72 IOUT = 3A VO2 = 1.05V 0.97 0.95 1.70 0 5 10 15 VIN − Input Voltage − V 20 25 0 G026 Figure 26. 5 10 15 20 VIN − Input Voltage − V 25 G027 Figure 27. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53126 17 TPS53126 SLUS909 – MAY 2009........................................................................................................................................................................................................ www.ti.com TYPICAL APPLICATION PERFORMANCE (continued) VO1 (20mV/div) VO1 = 1.8V VO2 (20mV/div) TEST2 = GND 350kHz Selection VO2 = 1.05V G028 Figure 28. 1.8V OUTPUT RIPPLE VOLTAGE 18 TEST2 = V5FILT 700kHz Selection G029 Figure 29. 1.05V OUTPUT RIPPLE VOLTAGE Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53126 TPS53126 www.ti.com........................................................................................................................................................................................................ SLUS909 – MAY 2009 APPLICATION INFORMATION Input Voltage 4.5V to 24V C9 10mF SGND Q3 FDS8878 4 3 2 1 TEST1 GND VFB1 VO1 7 EN2 C5 0.1mF VBST1 23 8 VBST2 PowerPAD 9 DRVH2 PGND Q1 FDS8878 L1 SPM6530T 1.5mH C3 10mF SW1 21 PGND1 19 TRI P1 12 PGND2 VIN DRVL1 20 VREG5 11 DRVL2 13 14 15 16 17 18 R6 3.3kW C2 0.1mF DRVH1 22 TPS53126 RGE (QFN) 10 SW2 Q4 FDS8690 EN1 24 V5FILT C4 22mF ´ 4 5 TEST2 VO2 1.05V/4A L2 SPM6530T 1.5mH 6 TRIP2 C6 10mF R2 R1 10kW 13kW VFB2 PGND R5 10kW VO2 R4 3.52kW C7 4.7mF R3 4.7kW Q2 FDS8690 VO1 1.8V/4A C1 22mF ´ 4 PGND C8 1 mF PGND SGND Figure 30. Typical Application Circuit at 350kHz Switching Frequency Selection (TEST2 Pin = GND) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53126 19 TPS53126 SLUS909 – MAY 2009........................................................................................................................................................................................................ www.ti.com Input Voltage 4.5V to 24V C9 10mF SGND 6 5 4 3 2 1 TEST1 GND VFB1 VO1 7 EN2 Q3 FDS8878 C6 10mF R2 R1 10kW 13kW VFB2 PGND R5 10kW VO2 R4 3.52kW C5 0.1mF L2 SPM6530T 1.5mH VBST1 23 8 VBST2 PowerPAD 9 DRVH2 TRI P1 PGND1 19 VIN 12 PGND2 VREG5 DRVL1 20 V5FILT 11 DRVL2 TEST2 C4 22mF ´ 4 13 14 15 16 17 18 R6 3.3kW PGND Q1 FDS8878 L1 SPM6530T 1.5mH SW1 21 TRIP2 Q4 FDS8690 C2 0.1mF DRVH1 22 TPS53126 RGE (QFN) 10 SW2 VO2 1.05V/4A EN1 24 C7 4.7mF R3 4.7kW Q2 FDS8690 C3 10mF VO1 1.8V/4A C1 22mF ´ 4 PGND C8 1 mF PGND SGND Figure 31. Typical Application Circuit at 700 kHz Switching frequency Selection (TEST2 Pin = V5FILT) Component Selection: 1. Choose inductor. The inductance value is selected to provide approximately 30% peak to peak ripple current at maximum load. Larger ripple current increases output ripple voltage, improve S/N ratio and contribute to stable operation. Equation 3 can be used to calculate L1. L1 = (VIN(max) )´ - Vo1 IL1(ripple) ´ ƒsw Vo1 VIN(max) = 3 ´ (VIN(max) - Vo1) ´ Io1 ´ ¦ sw Vo1 VIN(max) (3) The inductors current ratings needs to support both the RMS (thermal) current and the Peak (saturation) current. The RMS and peak inductor current can be estimated as follows: VIN(max) - Vo1 Vo1 ´ IL1(ripple) = L1 ´ ¦ sw VIN(max) (4) IL1(peak) = Vtrip RDS(on) + IL1(ripple) (5) ( IL1(RMS) = Io12 + 112 IL1(ripple) 2 ) (6) Note: The calculation above shall serve as a general reference. To further improve transient response, the output inductance could be reduced further. This needs to be considered along with the selection of the output capacitor. 2. Choose output capacitor. 20 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53126 TPS53126 www.ti.com........................................................................................................................................................................................................ SLUS909 – MAY 2009 The capacitor value and ESR determines the amount of output voltage ripple and load transient response. Recommend to use ceramic output capacitor. DIload2 ´ L1 2 ´ Vo1 ´ DVos C1 = (7) 2 ΔIload ´ L1 2 ´ K ´ DVus C1 = (8) Where: Tmin(off) Ton1 æ ö K = ç (VIN - Vo1) ´ Vo1÷ ´ Ton1 Ton1 + Tmin(off) è ø C1 = IL1(ripple) 8 Vo1(ripple) ´ (9) 1 ¦ sw (10) Select the capacitance value greater than the largest value calculated from Equation 7, Equation 8 and Equation 10. The capacitance for C1 should be greater than 66 µF. Where: ΔVos = the allowable amount of overshoot voltage in load transition ΔVus = the allowable amount of undershoot voltage in load transition Tmin(off) = Min-off time 3. Choose input capacitor. The TPS53126 requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. A minimum 10-µF high-quality ceramic capacitor is recommended for the input capacitor. The capacitor voltage rating needs to be greater than the maximum input voltage. 4. Choose bootstrap capacitor. The TPS53126 requires a bootstrap capacitor from SWx to VBSTx to provide the floating supply for the high-side drivers. A minimum 0.1-µF high-quality ceramic capacitor is recommended. The voltage rating should be greater than 6 V. 5. Choose VREG5 and V5FILT capacitors. The TPS53126 requires both the VREG5 regulator and V5FILT input are bypassed. A minimum 4.7-µF high-quality ceramic capacitor must be connected between the VREG5 and GND for proper operation. A minimum 1.0-µF high-quality ceramic capacitor must be connected between the V5FILT and GND for proper operation. Both of these capacitors’ voltage ratings should be greater than 6 V. 6. Choose output voltage divide resistors. The output voltage is set with a resistor divider from output voltage node to the VFBx pin. It is recommended to use 1% tolerance or better resisters. Select R2 between 10 kΩ and 100 kΩ and use Equation 11 and Equation 12 to calculate R1. æ ö ç ÷ Vo1 - 1÷ ´ R2 R1 = ç VFB1(ripple) ç ÷ ç 0.765 + ÷ 2 è ø (TEST2=GND) (11) æ ö ç ÷ Vo1 R1 = ç - 1÷ ´ R2 ç 0.758 + VFB1(ripple) ÷ ç ÷ 2 è ø (TEST2 = V5FILT) (12) Where: VFB1(ripple) = Ripple Voltage at VFB1 7. Choose resister setting for over current limit. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53126 21 TPS53126 SLUS909 – MAY 2009........................................................................................................................................................................................................ www.ti.com æ V ö (VIN - Vo) ´ O ÷ ´ RDS(on) Vtrip = ç IOCL + 2 ´ L1 ´ ¦ sw VIN ø è Vtrip (mV) R trip (kW) = Itrip (mA) (13) (14) Where: RDS(on) = Low Side FET on-resistance Itrip = TRIP pin source current （= 10 µA） IOCL = Over current limit LAYOUT SUGGESTIONS • • • • • • 22 Keep the input switching current loop as small as possible. Place the input capacitor (C3,C6) close to the top switching FET. The output current loop should also be kept as small as possible. Keep the SW node as physically small and short as possible as to minimize parasitic capacitance and inductance and to minimize radiated emissions Kelvin connections should be brought from the output to the feedback pin (FBx) of the device. Keep analog and non-switching components away from switching components Make a single point connection from the signal ground to power ground Do not allow switching current to flow under the device Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53126 PACKAGE OPTION ADDENDUM www.ti.com 4-Jun-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS53126PW ACTIVE TSSOP PW 24 TPS53126PWR ACTIVE TSSOP PW TPS53126RGER ACTIVE VQFN TPS53126RGET ACTIVE VQFN 60 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR RGE 24 250 CU NIPDAU Level-2-260C-1 YEAR Green (RoHS & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 2-Jun-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS53126PWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 TPS53126RGER VQFN RGE 24 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 TPS53126RGET VQFN RGE 24 250 180.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 2-Jun-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS53126PWR TSSOP PW 24 2000 346.0 346.0 33.0 TPS53126RGER VQFN RGE 24 3000 346.0 346.0 29.0 TPS53126RGET VQFN RGE 24 250 190.5 212.7 31.8 Pack Materials-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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