Not Recommended for New Designs ISO7240A ISO7241A ISO7242A www.ti.com SLLS905E – MAY 2008 – REVISED JANUARY 2010 1-Mbps QUAD DIGITAL ISOLATORS Check for Samples: ISO7240A, ISO7241A, ISO7242A FEATURES 1 • • • • • • 4000-Vpeak Isolation, 560-Vpeak VIORM – UL 1577 , IEC 60747-5-2 (VDE 0884, Rev 2), IEC 61010-1, IEC 60950-1 and CSA Approved 4 kV ESD Protection Operate With 3.3-V or 5-V Supplies Typical 25-Year Life at Rated Working Voltage (See Application Note (SLLA197 ) and Figure 10) High Electromagnetic Immunity (See Application Report (SLLA181)) –40°C to 125°C Operating Range APPLICATIONS • • • • Industrial Fieldbus Computer Peripheral Interface Servo Control Interface Data Acquisition DESCRIPTION See the Product Notification section. The ISO7240A, ISO7241A and ISO7242A are quad-channel digital isolators with multiple channel configurations and output enable functions. These devices have logic input and output buffers separated by TI’s silicon dioxide (SiO2) isolation barrier. Used in conjunction with isolated power supplies, these devices block high voltage, isolate grounds, and prevent noise currents from entering the local ground and interfering with or damaging sensitive circuitry. The ISO7240A has all four channels in the same direction while the ISO7241A has three channels the same direction and one channel in opposition. The ISO7242A has two channels in each direction. The devices have TTL input thresholds and a noise-filter at the input that prevents transient pulses from being passed to the output of the device. A periodic update pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh pulse is not received, the input is assumed to be unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state. (See ISO7240CF (SLLS869) or contact TI for a logic low failsafe option). These devices may be powered from either 3.3-V or 5-V supplies on either side in any 3.3-V / 3.3-V, 5-V / 5-V, 5-V / 3.3-V, or 3.3-V / 5-V combination. Note that the signal input pins are 5-V tolerant regardless of the voltage supply level being used. These devices are characterized for operation over the ambient temperature range of –40°C to 125°C. ISO7240A VCC1 GND1 INA INB INC IND NC GND1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ISO7241A VCC2 GND2 OUTA OUTB OUTC OUTD EN GND2 VCC1 GND1 INA INB INC OUTD EN1 GND1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ISO7242A VCC2 GND2 OUTA OUTB OUTC IND EN2 GND2 VCC1 GND1 INA INB OUTC OUTD EN1 GND1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 GND2 OUTA OUTB INC IND EN2 GND2 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2010, Texas Instruments Incorporated ISO7240A ISO7241A ISO7242A Not Recommended for New Designs SLLS905E – MAY 2008 – REVISED JANUARY 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. FUNCTION DIAGRAM Galvanic Isolation Barrier DC Channel Filter OSC + PWM Pulse Width Demodulation Vref Carrier Detect EN IN Input + Filter Data MUX AC Detect Vref OUT Output Buffer AC Channel Table 1. Device Function Table ISO724x INPUT VCC PU (1) OUTPUT VCC PU (1) INPUT (IN) OUTPUT ENABLE (EN) OUTPUT (OUT) H H or Open H L H or Open L X L Z Open H or Open H PD PU X H or Open H PD PU X L Z PU = Powered Up; PD = Powered Down ; X = Irrelevant; H = High Level; L = Low Level AVAILABLE OPTIONS (1) 2 PRODUCT SIGNALING RATE INPUT THRESHOLD CHANNEL CONFIGURATION MARKED AS ISO7240ADW 1 Mbps ~1.5 V (TTL) (CMOS compatible) 4/0 ISO7240A ISO7241ADW 1 Mbps ~1.5 V (TTL) (CMOS compatible) 3/1 ISO7241A ISO7242ADW 1 Mbps ~1.5 V (TTL) (CMOS compatible) 2/2 ISO7242A ORDERING NUMBER (1) ISO7240ADW (rail) ISO7240ADWR (reel) ISO7241ADW (rail) ISO7241ADWR (reel) ISO7242ADW (rail) ISO7242ADWR (reel) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ISO7240A ISO7241A ISO7242A ISO7240A ISO7241A ISO7242A Not Recommended for New Designs www.ti.com SLLS905E – MAY 2008 – REVISED JANUARY 2010 ABSOLUTE MAXIMUM RATINGS (1) VALUE UNIT VCC Supply voltage (2), VCC1, VCC2 –0.5 to 6 V VI Voltage at IN, OUT, EN –0.5 to 6 V IO Output current ±15 mA Human Body Model JEDEC Standard 22, Test Method A114-C.01 ESD Electrostatic Field-Induced-Charged Device discharge Model TJ Maximum junction temperature JEDEC Standard 22, Test Method C101 Machine Model (1) (2) ±4 All pins kV ±1 ANSI/ESDS5.2-1996 ±200 V 170 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal and are peak voltage values. RECOMMENDED OPERATING CONDITIONS MIN VCC Supply voltage (1), VCC1, VCC2 IOH High-level output current IOL Low-level output current tui Input pulse width 1/tui Signaling rate VIH High-level input voltage (IN) (EN on all devices) VIL Low-level input voltage (IN) (EN on all devices) MAX UNIT 5.5 V 4 mA –4 mA ISO724xA 1 ms ISO724xA 0 1000 kbps 2 VCC V 0 0.8 V 150 °C 1000 A/m ISO724xA TJ Junction temperature H External magnetic field-strength immunity per IEC 61000-4-8 and IEC 61000-4-9 certification (1) TYP 3.15 For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V. IEC 60747-5-2 INSULATION CHARACTERISTICS (1) over recommended operating conditions (unless otherwise noted) PARAMETER VIORM VPR Maximum working insulation voltage Input to output test voltage VIOTM RS TEST CONDITIONS Transient overvoltage Insulation resistance UNIT 560 V After Input/Output Safety Test Subgroup 2/3 VPR = VIORM × 1.2, t = 10 s, Partial discharge < 5 pC 672 V Method a, VPR = VIORM × 1.6, Type and sample test with t = 10 s, Partial discharge < 5 pC 896 V Method b1, VPR = VIORM × 1.875, 100 % Production test with t = 1 s, Partial discharge < 5 pC 1050 V t = 60 s 4000 V 9 Ω VIO = 500 V at TS Pollution degree (1) SPECIFICATIONS >10 2 Climatic Classification 40/125/21 Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ISO7240A ISO7241A ISO7242A Submit Documentation Feedback 3 ISO7240A ISO7241A ISO7242A Not Recommended for New Designs SLLS905E – MAY 2008 – REVISED JANUARY 2010 www.ti.com ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 5-V (1) OPERATION , over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT ISO7240A ICC1 ISO7241A ISO7242A ISO7240A ICC2 ISO7241A ISO7242A Quiescent 1 3 1 3 6.5 11 10 16 10 16 15 22 16 22 VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V 13 20 13 20 VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V 10 16 10 16 VI = VCC or 0 V, All channels, no load, EN2 at 3 V 1 Mbps Quiescent VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V 1 Mbps Quiescent VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V 1 Mbps Quiescent VI = VCC or 0 V, All channels, no load, EN2 at 3 V 1 Mbps Quiescent 1 Mbps Quiescent 1 Mbps mA mA mA mA mA mA ELECTRICAL CHARACTERISTICS IOFF Sleep mode output current EN at 0 V, Single channel 0 IOH = –4 mA, See Figure 1 VCC – 0.8 IOH = –20 mA, See Figure 1 VCC – 0.1 VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6pt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 4 (1) mA V IOL = 4 mA, See Figure 1 0.4 IOL = 20 mA, See Figure 1 0.1 150 mV 10 IN from 0 V to VCC –10 25 V mA 2 pF 50 kV/ms For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V. SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 5-V OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP Propagation delay PWD Pulse-width distortion (1) |tPHL – tPLH| tsk(o) Channel-to-channel output skew tr Output signal rise time tf Output signal fall time tPHZ Propagation delay, high-level-to-high-impedance output 15 20 tPZH Propagation delay, high-impedance-to-high-level output 15 20 tPLZ Propagation delay, low-level-to-high-impedance output 15 20 tPZL Propagation delay, high-impedance-to-low-level output 15 20 tfs Failsafe output delay time from input power loss (1) (2) 4 40 MAX tPLH, tPHL See Figure 1 95 10 (2) 2 2 See Figure 1 See Figure 3 12 ns ns ns 2 See Figure 2 UNIT ns ms Also referred to as pulse skew. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ISO7240A ISO7241A ISO7242A ISO7240A ISO7241A ISO7242A Not Recommended for New Designs www.ti.com SLLS905E – MAY 2008 – REVISED JANUARY 2010 ELECTRICAL CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V (1) OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT ISO7240A ICC1 ISO7241A ISO7242A ISO7240A ICC2 ISO7241A ISO7242A Quiescent 1 3 1 3 6.5 11 10 16 10 16 9.5 15 10 15 VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V 8 13 8 13 VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V 6 10 6 10 VI = VCC or 0 V, All channels, no load, EN2 at 3 V 1 Mbps Quiescent VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V 1 Mbps Quiescent VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V 1 Mbps Quiescent VI = VCC or 0 V, All channels, no load, EN2 at 3 V 1 Mbps Quiescent 1 Mbps Quiescent 1 Mbps mA mA mA mA mA mA ELECTRICAL CHARACTERISTICS IOFF Sleep mode output current VOH EN at 0 V, Single channel IOH = –4 mA, See Figure 1 High-level output voltage 0 ISO7240A VCC – 0.4 ISO724x (5-V side) VCC – 0.8 IOH = –20 mA, See Figure 1 VOL Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IIL Low-level input current V VCC – 0.1 IOL = 4 mA, See Figure 1 0.4 IOL = 20 mA, See Figure 1 0.1 150 IN from 0 V to VCC –10 Input capacitance to ground CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 4 IN at VCC, VI = 0.4 sin (4E6pt) 25 V mV 10 CI (1) mA mA 2 pF 50 kV/ms For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V. SWITCHING CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS tPLH, tPHL Propagation delay PWD Pulse-width distortion (1) |tPHL – tPLH| tsk(o) Channel-to-channel output skew tr Output signal rise time tf Output signal fall time tPHZ Propagation delay, high-level-to-high-impedance output tPZH Propagation delay, high-impedance-to-high-level output tPLZ Propagation delay, low-level-to-high-impedance output tPZL Propagation delay, high-impedance-to-low-level output tfs Failsafe output delay time from input power loss (1) (2) See Figure 1 MIN TYP 40 MAX 100 11 3 (2) 0 See Figure 1 See Figure 2 See Figure 3 1 2 UNIT ns ns ns 2 15 20 15 20 15 20 15 20 18 ns ms Also known as pulse skew tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ISO7240A ISO7241A ISO7242A Submit Documentation Feedback 5 ISO7240A ISO7241A ISO7242A Not Recommended for New Designs SLLS905E – MAY 2008 – REVISED JANUARY 2010 www.ti.com ELECTRICAL CHARACTERISTICS: VCC1 at 3.3-V, VCC2 at 5-V (1) OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT ISO7240A ICC1 ISO7241A ISO7242A ISO7240A ICC2 ISO7241A ISO7242A Quiescent 1 Mbps Quiescent 1 Mbps Quiescent 1 Mbps Quiescent 1 Mbps Quiescent 1 Mbps Quiescent 1 Mbps VI = VCC or 0 V, All channels, no load, EN2 at 3 V 0.5 1 1 2 4 7 4 7 6 10 6 10 15 22 16 22 13 20 13 20 10 16 10 16 VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V VI = VCC or 0 V, All channels, no load, EN2 at 3 V VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V mA mA mA mA mA mA ELECTRICAL CHARACTERISTICS IOFF Sleep mode output current EN at VCC, Single channel VOH High-level output voltage IOH = –4 mA, See Figure 1 0 ISO7240A VCC – 0.4 ISO724x (5-V side) VCC – 0.8 IOH = –20 mA, See Figure 1 VOL Low-level output voltage V VCC – 0.1 IOL = 4 mA, See Figure 1 0.4 IOL = 20 mA, See Figure 1 0.1 VI(HYS) Input voltage hysteresis IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6pt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 4 (1) mA 150 mV 10 IN from 0 V to VCC –10 2 25 V mA pF 50 kV/ms For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V. SWITCHING CHARACTERISTICS: VCC1 at 3.3-V and VCC2 at 5-V OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 40 100 tPLH, tPHL Propagation delay PWD Pulse-width distortion (1) |tPHL – tPLH| tsk(o) Channel-to-channel output skew tr Output signal rise time tf Output signal fall time tPHZ Propagation delay, high-level-to-high-impedance output 15 20 tPZH Propagation delay, high-impedance-to-high-level output 15 20 tPLZ Propagation delay, low-level-to-high-impedance output 15 20 tPZL Propagation delay, high-impedance-to-low-level output 15 20 tfs Failsafe output delay time from input power loss (1) (2) 6 See Figure 1 11 2.5 (2) 0 1 2 See Figure 1 See Figure 3 12 ns ns ns 2 See Figure 2 UNIT ns ms Also known as pulse skew tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ISO7240A ISO7241A ISO7242A ISO7240A ISO7241A ISO7242A Not Recommended for New Designs www.ti.com SLLS905E – MAY 2008 – REVISED JANUARY 2010 ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3 V (1) OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT ISO7240A ICC1 ISO7241A ISO7242A ISO7240A ICC2 ISO7241A ISO7242A Quiescent VI = VCC or 0 V, all channels, no load, EN2 at 3 V 1 Mbps Quiescent 0.5 1 1 2 4 7 VI = VCC or 0 V, all channels, no load, EN1 at 3 V, EN2 at 3 V 1 Mbps Quiescent VI = VCC or 0 V, all channels, no load, EN1 at 3 V, EN2 at 3 V 1 Mbps Quiescent VI = VCC or 0 V, all channels, no load, EN2 at 3 V 1 Mbps Quiescent Quiescent 10 6 10 15 10 15 VI = VCC or 0 V, all channels, no load, EN1 at 3 V, EN2 at 3 V 1 Mbps 7 6 9.5 VI = VCC or 0 V, all channels, no load, EN1 at 3 V, EN2 at 3 V 1 Mbps 4 8 13 8 13 6 10 6 10 mA mA mA mA ELECTRICAL CHARACTERISTICS IOFF Sleep mode output current EN at 0 V, single channel 0 IOH = –4 mA, See Figure 1 VCC – 0.4 IOH = –20 mA, See Figure 1 VCC – 0.1 VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6pt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 4 (1) mA V IOL = 4 mA, See Figure 1 0.4 IOL = 20 mA, See Figure 1 0.1 150 mV 10 IN from 0 V or VCC –10 25 V mA 2 pF 50 kV/ms For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V. SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 3.3-V OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 45 110 tPLH, tPHL Propagation delay PWD Pulse-width distortion |tPHL – tPLH| (1) tsk(o) Channel-to-channel output skew tr Output signal rise time tf Output signal fall time tPHZ Propagation delay, high-level-to-high-impedance output 15 20 tPZH Propagation delay, high-impedance-to-high-level output 15 20 tPLZ Propagation delay, low-level-to-high-impedance output 15 20 tPZL Propagation delay, high-impedance-to-low-level output 15 20 tfs Failsafe output delay time from input power loss (1) (2) See Figure 1 12 UNIT ns 3.5 (2) 0 See Figure 1 See Figure 2 See Figure 3 1 2 ns 2 18 ns ms Also referred to as pulse skew. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ISO7240A ISO7241A ISO7242A Submit Documentation Feedback 7 ISO7240A ISO7241A ISO7242A Not Recommended for New Designs SLLS905E – MAY 2008 – REVISED JANUARY 2010 www.ti.com ISOLATION BARRIER PARAMETER MEASUREMENT INFORMATION IN Input Generator VI 50 W NOTE A VCC1 VI VCC1/2 VCC1/2 OUT 0V tPHL tPLH CL NOTE B VO VO VOH 90% 50% 50% 10% tr VOL tf A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50Ω. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms Vcc Vcc ISOLATION BARRIER 0V RL = 1 kW ±1% IN Input Generator VI OUT EN Vcc/2 VI t PZL VO VO CL Vcc/2 0V t PLZ Vcc 0.5 V 50% NOTE B 50 W VOL 3V ISOLATION BARRIER NOTE A IN Input Generator VI Vcc OUT VO Vcc/2 VI Vcc/2 0V EN 50 W t PZH CL NOTE B VOH RL = 1 kW ±1% 50% VO 0.5 V t PHZ 0V NOTE A A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50Ω. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 2. Enable/Disable Propagation Delay Time Test Circuit and Waveform 8 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ISO7240A ISO7241A ISO7242A ISO7240A ISO7241A ISO7242A Not Recommended for New Designs www.ti.com SLLS905E – MAY 2008 – REVISED JANUARY 2010 PARAMETER MEASUREMENT INFORMATION (continued) VI 0V or VCC1 IN VCC1 ISOLATION BARRIER VCC1 2.7 V VI OUT 0V VO tfs VOH CL NOTE B VO 50% fs low VOL A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50Ω. Figure 3. Failsafe Delay Time Test Circuit and Voltage Waveforms VCC1 VCC2 S1 IN ISOLATION BARRIER C = 0.1 mF± 1% GND1 C = 0.1 mF± 1% OUT NOTE B Pass-fail criteria: Output must remain stable VOH or VOL GND2 VCM A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50Ω. Figure 4. Common-Mode Transient Immunity Test Circuit and Voltage Waveform Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ISO7240A ISO7241A ISO7242A Submit Documentation Feedback 9 ISO7240A ISO7241A ISO7242A Not Recommended for New Designs SLLS905E – MAY 2008 – REVISED JANUARY 2010 www.ti.com DEVICE INFORMATION PACKAGE CHARACTERISTICS PARAMETER L(I01) TEST CONDITIONS MIN TYP MAX UNIT Minimum air gap (Clearance) Shortest terminal-to-terminal distance through air 8.34 mm L(I02) Minimum external tracking (Creepage) Shortest terminal-to-terminal distance across the package surface 8.1 mm CTI Tracking resistance (comparative tracking index) DIN IEC 60112/VDE 0303 Part 1 ≥ 175 V Minimum Internal Gap (Internal Clearance) Distance through the insulation 0.008 mm Isolation resistance Input to output, VIO = 500 V, all pins on each side of the barrier tied together creating a two-terminal device RIO >1012 Ω CIO Barrier capacitance Input to output VI = 0.4 sin (4E6pt) 2 pF CI Input capacitance to ground VI = 0.4 sin (4E6pt) 2 pF IEC 60664-1 RATINGS TABLE PARAMETER TEST CONDITIONS Basic isolation group Installation classification SPECIFICATION Material group IIIa Rated mains voltage ≤150 VRMS I-IV Rated mains voltage ≤300 VRMS I-III REGULATORY INFORMATION VDE CSA UL Certified according to IEC 60747-5-2 Approved under CSA Component Acceptance Notice Recognized under 1577 Component Recognition Program (1) File Number: 40016131 File Number: 1698195 File Number: E181974 (1) Production tested ≥ 3000 Vrms for 1 second in accordance with UL 1577. DEVICE I/O SCHEMATICS Enable VCC Output Input VCC VCC VCC VCC VCC 1 MW 1 MW 500 W EN VCC IN 8W 500 W OUT 13 W 10 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ISO7240A ISO7241A ISO7242A ISO7240A ISO7241A ISO7242A Not Recommended for New Designs www.ti.com SLLS905E – MAY 2008 – REVISED JANUARY 2010 THERMAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX Low-K Thermal Resistance (1) 168 High-K Thermal Resistance 96.1 UNIT qJA Junction-to-air qJB Junction-to-Board Thermal Resistance 61 °C/W qJC Junction-to-Case Thermal Resistance 48 °C/W PD (1) °C/W VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 50% duty cycle square wave Device Power Dissipation 220 mW Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages. Spacer Spacer TYPICAL CHARACTERISTIC CURVES INPUT VOLTAGE THRESHOLD vs FREE-AIR TEMPERATURE VCC1 FAILSAFE THRESHOLD vs FREE-AIR TEMPERATURE 1.4 3 5 V Vth+ 1.3 2.9 VCC1 - Failsafe Threshold - V Input Voltage Threshold - V 1.35 3.3 V Vth+ 1.25 1.2 Air Flow at 7 cf/m, Low_K Board 1.15 5 V Vth1.1 2.8 VCC at 5 V or 3.3 V, Load = 15 pF, Air Flow at 7/cf/m, Low-K Board 2.7 Vfs+ 2.6 2.5 Vfs- 2.4 2.3 2.2 1.05 1 -40 3.3 V Vth-25 -10 2.1 5 20 35 50 65 80 TA - Free-Air Temperature - °C 95 110 2 -40 125 -10 5 20 35 50 65 80 95 110 125 TA - Free-Air Temperature - °C Figure 5. Figure 6. HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 50 50 Load = 15 pF, TA = 25°C VCC = 5 V Load = 15 pF, TA = 25°C 45 40 IO - Output Current - mA 40 IO - Output Current - mA -25 VCC = 3.3 V 30 20 35 VCC = 3.3 V 30 25 VCC = 5 V 20 15 10 10 5 0 0 0 2 4 VO - Output Voltage - V 6 0 1 Figure 7. 2 3 VO - Output Voltage - V 4 5 Figure 8. Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ISO7240A ISO7241A ISO7242A Submit Documentation Feedback 11 ISO7240A ISO7241A ISO7242A Not Recommended for New Designs SLLS905E – MAY 2008 – REVISED JANUARY 2010 www.ti.com APPLICATION INFORMATION 2 mm max. from VCC1 VCC1 2 mm max. from VCC2 VCC2 0.1 mF 0.1 mF 1 16 2 15 IN A 3 14 OUT A IN B 4 13 OUT B IN C 5 12 OUT C IN D 6 11 GND2 GND1 OUT D EN NC 7 10 8 9 GND2 GND1 ISO7240A Figure 9. Typical ISO7240A Application Circuit Spacer LIFE EXPECTANCY vs. WORKING VOLTAGE WORKING LIFE -- YEARS 100 VIORM at 560-V 28 Years 10 0 120 250 500 750 880 1000 WORKING VOLTAGE (VIORM) -- V Figure 10. Time-Dependant Dielectric Breakdown Testing Results 12 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ISO7240A ISO7241A ISO7242A Not Recommended for New Designs www.ti.com ISO7240A ISO7241A ISO7242A SLLS905E – MAY 2008 – REVISED JANUARY 2010 PRODUCT NOTIFICATION An ISO724xA anomaly occurs when a negative-going pulse below the specified 1 ms minimum bit width is input to the device. The output locks in a logic-low condition until the next rising edge occurs after a 1 ms period. Positive noise edges in pulses of less than the minimum specified 1 ms have no effect on the device, and are properly filtered. To prevent noise from interfering with ISO724xA performance, it is recommended that an appropriately sized capacitor be placed on each input of the device Figure 11. ISO724xA Anomaly REVISION HISTORY Changes from Original (May 2008) to Revision A • Page Changed In the PACKAGE CHARACTERISTICS table, line 1, change L(IO1) MIN value from 7.7mm to 8.34mm. ........... 10 Changes from Revision A (July 2008) to Revision B Page • Added information to the 1st Feature bullet to include CSA and IEC 60950-1 certification ................................................. 1 • Changed Figure 9 From: 20mm max.from VCCx To: 2mm max. from VCCx. ........................................................................ 12 Changes from Revision B (December 2008) to Revision C Page • Changed ICC1 for Quiescent and 1Mbps From: 10mA To: 11mA ......................................................................................... 4 • Changed ICC1 for Quiescent and 1Mbps From: 10mA To: 11mA ......................................................................................... 5 Changes from Revision C (March 2009) to Revision D • Page Changed The Input circuit in the DEVICE I/O SCHEMATICS illustration. ......................................................................... 10 Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ISO7240A ISO7241A ISO7242A Submit Documentation Feedback 13 ISO7240A ISO7241A ISO7242A Not Recommended for New Designs SLLS905E – MAY 2008 – REVISED JANUARY 2010 www.ti.com Changes from Revision D (December 2009) to Revision E Page • Added the IEC 60747-5-2 INSULATION CHARACTERISTIC table ..................................................................................... 3 • Added CTI - Tracking resistance (comparative tracking index to the PACKAGE CHARACTERISTICS table ................... 10 • Added the IEC 60664-1 RATINGS TABLE ......................................................................................................................... 10 14 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): ISO7240A ISO7241A ISO7242A PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) ISO7240ADW NRND SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ISO7240A ISO7240ADWG4 NRND SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ISO7240A ISO7240ADWR NRND SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ISO7240A ISO7240ADWRG4 NRND SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ISO7240A ISO7241ADW NRND SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ISO7241A ISO7241ADWG4 NRND SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ISO7241A ISO7241ADWR NRND SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ISO7241A ISO7241ADWRG4 NRND SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ISO7241A ISO7242ADW NRND SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ISO7242A ISO7242ADWG4 NRND SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ISO7242A ISO7242ADWR NRND SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ISO7242A ISO7242ADWRG4 NRND SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ISO7242A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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OTHER QUALIFIED VERSIONS OF ISO7241A : • Enhanced Product: ISO7241A-EP NOTE: Qualified Version Definitions: • Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ISO7240ADWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 ISO7241ADWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 ISO7242ADWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ISO7240ADWR SOIC DW 16 2000 367.0 367.0 38.0 ISO7241ADWR SOIC DW 16 2000 367.0 367.0 38.0 ISO7242ADWR SOIC DW 16 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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