TI TM16ER72HP

SMMS694 − AUGUST 1997
D
D
D
D
D
D
− TM16ER72HP-xx . . . 16 777 216 × 72 Bits
− TM16ER72LP-xx . . . 16 777 216 × 72 Bits
Single 3.3-V Power Supply
(±10% Tolerance)
JEDEC 168-Pin Dual-In-Line Memory
Module (DIMM) With Buffer for Use With
Socket
TM16ER72xP-xx — Uses 18 64M-Bit
High-Speed (16M × 4-Bit) Dynamic RAMs
High-Speed, Low-Noise LVTTL Interface
High-Reliability 32-Lead 400-Mil-Wide
Surface-Mount Thin Small-Outline Package
(TSOP) (DGE Suffix)
Intended for Workstation / Server
Applications
D Long Refresh Periods:
D
D
D
D
D
− TM16ER72HP: 64 ms (4 096 Cycles)
− TM16ER72LP: 64 ms (8 192 Cycles)
3-State Output
Extended-Data-Out (EDO) Operation With
CAS-Before-RAS (CBR), RAS-Only, and
Hidden Refresh
Ambient Temperature Range
0°C to 70°C
Gold-Plated Contacts
Performance Ranges
’16ER72xx-40
’16ER72xx-50
’16ER72xx-60
ACCESS
TIME
tRAC
(MAX)
40 ns
50 ns
60 ns
ACCESS ACCESS EDO
TIME
TIME CYCLE
tCAC
tAA
tHPC
(MAX)
(MAX)
(MIN)
11 ns
20 ns
16 ns
13 ns
25 ns
20 ns
15 ns
30 ns
25 ns
description
The TM16ER72HP is a 128M-byte, 168-pin, buffered dual-in-line memory module (DIMM). The DIMM is
composed of eighteen TMS465409, 16 777 216 × 4-bit 4K-refresh EDO dynamic random-access memories
(DRAMs), each in a 400-mil, 32-pin plastic thin small-outline package (TSOP) (DGE suffix), and two
SN74LVC162244 16-bit buffers, each in a 48-lead plastic TSOP package mounted on a substrate with
decoupling capacitors. See the TMS465409 data sheet (literature number SMKS895).
The TM16ER72LP is a 128M-byte, 168-pin, buffered DIMM. The DIMM is composed of eighteen TMS464409,
16 777 216 × 4-bit 8K-refresh EDO DRAMs, each in a 400-mil, 32-pin plastic TSOP (DGE suffix), and two
SN74LVC162244 16-bit buffers, each in a 48-lead plastic TSOP package mounted on a substrate with
decoupling capacitors. See the TMS465409 data sheet (literature number SMKS895).
These modules are intended for multimodule workstation / server applications where buffering is needed for
address and control signals. Two copies of address 0 (A0 and B0) are defined to allow maximum performance
for 4-byte applications that interleave between two 4-byte banks. A0 is common to the DRAMs used for
DQ0−DQ31, while B0 is common to the DRAMs used for DQ32−DQ63.
operation
The TM16ER72xP operates as eighteen TMS46x409s that are connected as shown in the TM16ER72xP
functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1997, Texas Instruments Incorporated
!"#$ %%&!' (!)*%$' $+& !"#$,& !
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'(&%%#$' #!& )&'- -#.'/ &0#' '$!*"&$' !&'&!,&' $+& !-+$ $
%+#-& ! )'%$*& $+&'& (!)*%$' 1$+*$ $%&/
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
1
PRODUCT PREVIEW
D Organization
SMMS694 − AUGUST 1997
DUAL-IN-LINE MEMORY MODULE
( TOP VIEW )
TM16ER72xP
( SIDE VIEW )
A[0:11]
A[0:11]
B0
DQ[0:63]
CB[0:7]
CAS0 and CAS4
ID[0:1]
RAS0 and RAS2
WE0 and WE2
OE0 and OE2
NC
PD[1:8]
PDE
VDD
VSS
1
10
11
PRODUCT PREVIEW
PIN NOMENCLATURE − TM16ER72HP
Row Address Inputs
Column Address Inputs
Addr0 for Bank 2 Devices
Data In / Data Out
Check Bit In / Check Bit Out
Column-Address Strobe
ID Pins
Row-Address Strobe
Write Enable
Output Enable
No-Connect Pin
Presence Detect
Presence Detect Enable
3.3-V Supply
Ground
PIN NOMENCLATURE − TM16ER72LP
A[0:12]
A[0:10]
B0
DQ[0:63]
CB[0:7]
CAS0 and CAS4
ID[0:1]
RAS0 and RAS2
WE0 and WE2
OE0 and OE2
NC
PD[1:8]
PDE
VDD
VSS
40
41
Row Address Inputs
Column Address Inputs
Addr0 for Bank 2 Devices
Data In / Data Out
Check Bit In / Check Bit Out
Column-Address Strobe
ID Pins
Row-Address Strobe
Write Enable
Output Enable
No-Connect Pin
Presence Detect
Presence Detect Enable
3.3-V Supply
Ground
PRESENCE DETECT
84
2
POST OFFICE BOX 1443
PIN
- 40
-50
- 60
PD1
1
1
1
PD2
1
1
1
PD3
1
1
1
PD4
1
1
1
PD5
1
1
1
PD6
1
0
1
PD7
0
0
1
PD8
0
0
0
ID0
0
0
0
ID1
0
0
0
• HOUSTON, TEXAS 77251−1443
SMMS694 − AUGUST 1997
Pin Assignments
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PIN
NAME
NO.
PIN
NAME
NO.
PIN
NAME
NAME
NO.
1
VSS
DQ0
43
86
VSS
DQ32
127
44
VSS
OE2
85
2
128
VSS
NC
3
DQ1
45
RAS2
87
DQ33
129
NC
4
DQ2
46
CAS4
88
DQ34
130
NC
5
DQ3
47
NC
89
DQ35
131
NC
6
VDD
DQ4
48
WE2
90
PDE
49
91
133
8
DQ5
50
VDD
NC
VDD
DQ36
132
7
92
DQ37
134
VDD
NC
9
DQ6
51
NC
93
DQ38
135
NC
10
DQ7
52
CB2
94
DQ39
136
CB6
11
DQ8
53
CB3
95
DQ40
137
CB7
12
54
97
VSS
DQ41
138
55
VSS
DQ16
96
13
VSS
DQ9
139
VSS
DQ48
14
DQ10
56
DQ17
98
DQ42
140
DQ49
15
DQ11
57
DQ18
99
DQ43
141
DQ50
16
DQ12
58
DQ19
100
DQ44
142
DQ51
17
DQ13
59
101
DQ45
143
18
60
102
VDD
DQ52
61
NC
103
VDD
DQ46
144
19
VDD
DQ14
VDD
DQ20
145
NC
20
DQ15
62
NC
104
DQ47
146
NC
21
CB0
63
NC
105
CB4
147
NC
22
CB1
64
NC
106
CB5
148
NC
23
65
DQ21
107
DQ53
66
DQ22
108
VSS
NC
149
24
VSS
NC
150
DQ54
25
NC
67
DQ23
109
NC
151
DQ55
26
68
111
VDD
NC
152
69
VSS
DQ24
110
27
VDD
WE0
153
VSS
DQ56
28
CAS0
70
DQ25
112
NC
154
DQ57
29
NC
71
DQ26
113
NC
155
DQ58
30
RAS0
72
DQ27
114
NC
156
DQ59
31
OE0
73
115
NC
157
32
74
116
158
75
DQ29
117
VSS
A1
VDD
DQ60
33
VSS
A0
VDD
DQ28
159
DQ61
34
A2
76
DQ30
118
A3
160
DQ62
35
A4
77
DQ31
119
A5
161
DQ63
36
A6
78
120
A7
162
37
A8
79
VSS
PD1
121
A9
163
VSS
PD2
38
A10
80
PD3
122
A11
164
PD4
39
A12
81
PD5
123
NC
165
PD6
40
82
PD7
124
PD8
83
ID0
125
VDD
NC
166
41
VDD
NC
167
ID1
42
NC
84
VDD
126
B0
168
VDD
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
PRODUCT PREVIEW
PIN
NO.
3
SMMS694 − AUGUST 1997
buffered dual-in-line memory module and components
The buffered dual-in-line memory module and components include:
D PC substrate: 1,27 " 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
D Bypass capacitors: Multilayer ceramic
D Contact area: Nickel plate and gold plate over copper
functional block diagram for the TM16ER72xP
RAS0
RAS2
WE0
WE2
OE0
OE2
CAS0
CAS4
CAS
DQ[0:3]
PRODUCT PREVIEW
DQ[4:7]
OE
DQ[8:11]
OE
DQ[12:15]
OE
CB[0:3]
OE
DQ[16:19]
OE
DQ[20:23]
OE
DQ[24:27]
OE
DQ[28:31]
OE
DQ[0:3]
A0
B0
A[1:n]
W
DQ[48:51]
W
DQ[52:55]
W
DQ[56:59]
DQ[60:63]
VDD
U[0:8]
DQ[0:3]
RAS
W
RAS
W
RAS
UB3
OE
W
RAS
UB8
OE
W
RAS
UB4
OE
W
RAS
UB5
OE
W
RAS
UB6
DQ[0:3]
CAS
RAS
U7
OE
DQ[0:3]
CAS
RAS
W
UB2
DQ[0:3]
CAS
RAS
OE
DQ[0:3]
CAS
RAS
U6
DQ[0:3]
CAS
W
CB[4:7]
RAS
UB1
DQ[0:3]
CAS
RAS
U5
DQ[0:3]
CAS
W
DQ[44:47]
OE
DQ[0:3]
CAS
RAS
U4
DQ[0:3]
CAS
W
DQ[40:43]
W
UB0
DQ[0:3]
CAS
RAS
U8
DQ[0:3]
CAS
W
DQ[36:39]
OE
DQ[0:3]
CAS
RAS
U3
DQ[0:3]
CAS
DQ[32:35]
U2
DQ[0:3]
CAS
W
CAS
RAS
U1
DQ[0:3]
CAS
W
U0
DQ[0:3]
CAS
4
OE
OE
W
RAS
UB7
U[0:8], UB[0:8]
Two 0.1 µF (Minimum)
per DRAM
UB[0:8]
A[1:n]: U[0:8], UB[0:8]
POST OFFICE BOX 1443
VSS
• HOUSTON, TEXAS 77251−1443
U[0:8], UB[0:8]
SMMS694 − AUGUST 1997
absolute maximum ratings over ambient temperature range (unless otherwise noted)†
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation: TM16ER72xP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 W
Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 125°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
recommended operating conditions
MIN
NOM
MAX
3
3.3
3.6
Supply voltage
VIH
VIL
High-level input voltage
2
Low-level input voltage
TA
Ambient temperature
Supply voltage
0
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
UNIT
V
V
V
−0.3
VDD + 0.3
0.8
0
70
°C
V
5
PRODUCT PREVIEW
VDD
VSS
SMMS694 − AUGUST 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted)
TM16ER72HP
PRODUCT PREVIEW
PARAMETER
’16ER72HP-40
TEST CONDITIONS†
IOH = − 2 mA
IOH = − 100 µA
IOL = 2 mA
MIN
LVTTL
High-level output
voltage
VOL
Low-level output
voltage
II
Input current
(leakage)
IOL = 100 µA
LVCMOS
VDD = 3.6 V,
VI = 0 V to 3.9 V,
All others = 0 V to VCC
IO
Output current
(leakage)
VDD = 3.6 V,
CASx high
ICC1‡§
Average read- or
write-cycle
current
VDD = 3.6 V,
ICC2
MAX
MIN
2.4
VOH
Average standby
current
’16ER72HP-50
LVCMOS
LVTTL
’16ER72HP-60
MAX
2.4
VDD −0.2
MIN
MAX
UNIT
2.4
VDD −0.2
V
VDD −0.2
0.4
0.4
0.4
0.2
0.2
0.2
± 20
± 20
± 20
µA
VO = 0 V to VDD,
± 20
± 20
± 20
µA
Minimum cycle
2 880
2 340
1 980
mA
18
18
18
mA
9
9
9
mA
VIH = 2 V (LVTTL),
After one memory cycle,
RASx and CASx high
VIH = VDD − 0.2 V (LVCMOS),
After one memory cycle,
RASx and CASx high
V
ICC3‡§
Average refresh
current
(RAS-only
refresh or CBR)
VDD = 3.6 V,
Minimum cycle,
RASx cycling,
CASx high (RASx-only refresh),
RASx low after CASx low (CBR)
2 880
2 340
1 980
mA
ICC4‡¶
Average EDO
current
VDD = 3.6 V,
RASx low,
2 700
2 160
1 800
mA
ICC5
Average CBR
refresh current
VDD = 3.6 V,
Minimum cycle,
RASx low after CASx low
2 880
2 340
1 980
mA
tHPC = MIN,
CASx cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RASx = VIL
¶ Measured with a maximum of one address change during each EDO cycle, tHPC
6
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
SMMS694 − AUGUST 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted) (continued)
TM16ER72LP
IOH = − 2 mA
IOH = − 100 µA
IOL = 2 mA
High-level output
voltage
VOL
Low-level output
voltage
II
Input current
(leakage)
IOL = 100 µA
LVCMOS
VDD = 3.6 V,
VI = 0 V to 3.9 V,
All others = 0 V to VCC
IO
Output current
(leakage)
VDD = 3.6 V,
CASx high
ICC1‡§
Average read- or
write-cycle
current
VDD = 3.6 V,
ICC2
MIN
LVTTL
VOH
Average standby
current
’16ER72LP-40
TEST CONDITIONS†
’16ER72LP-50
MAX
MIN
2.4
LVCMOS
MAX
2.4
VDD −0.2
LVTTL
’16ER72LP-60
MIN
MAX
UNIT
2.4
VDD −0.2
V
VDD −0.2
0.4
0.4
0.4
0.2
0.2
0.2
± 20
± 20
± 20
µA
VO = 0 V to VDD,
± 20
± 20
± 20
µA
Minimum cycle
2 250
1 800
1 620
mA
18
18
18
mA
9
9
9
mA
VIH = 2 V (LVTTL),
After one memory cycle,
RASx and CASx high
VIH = VDD − 0.2 V (LVCMOS),
After one memory cycle,
RASx and CASx high
V
ICC3‡§
Average refresh
current
(RAS-only
refresh or CBR)
VDD = 3.6 V,
Minimum cycle,
RASx cycling,
CASx high (RASx-only refresh),
RASx low after CASx low (CBR)
2 250
1 800
2 250
mA
ICC4‡¶
Average EDO
current
VDD = 3.6 V,
RASx low,
2 520
1 980
1 620
mA
ICC5
Average CBR
refresh current
VDD = 3.6 V,
Minimum cycle,
RASx low after CASx low
2 880
2 340
1 980
mA
tHPC = MIN,
CASx cycling
PRODUCT PREVIEW
PARAMETER
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RASx = VIL
¶ Measured with a maximum of one address change during each EDO cycle, tHPC
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
7
SMMS694 − AUGUST 1997
capacitance over recommended ranges of supply voltage and ambient temperature,
f = 1 MHz (see Note 2)
’16ER72xP
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, A0 −A10
6
pF
Ci(OE)
Input capacitance, OEx
6
pF
Ci(CAS)
Input capacitance, CASx
6
pF
Ci(RAS)
Input capacitance, RASx
65
pF
Ci(W)
Input capacitance, WEx
6
pF
9
pF
Co
Output capacitance
NOTE 2: VDD = NOM supply voltage ± 10%, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and ambient temperature
(see Note 3)
’16ER72xP-40
PRODUCT PREVIEW
PARAMETER
MIN
MAX
’16ER72xP-50
MIN
MAX
’16ER72xP-60
MIN
MAX
UNIT
tAA
tCAC
Access time from column address (see Note 4)
25
30
35
ns
Access time from CASx (see Note 4)
16
18
20
ns
tCPA
tRAC
Access time from CASx precharge (see Note 4)
27
33
40
ns
Access time from RASx (see Note 4)
45
50
60
ns
tOEA
tCLZ
Access time from OEx (see Note 4)
16
18
20
ns
Delay time, CASx to output in low impedance
2
tREZ
tCEZ
Output buffer turn off delay from RASx (see Note 5)
3
11
3
13
3
15
ns
Output buffer turn off delay from CASx (see Note 5)
5
16
5
18
5
20
ns
tOEZ
tWEZ
Output buffer turn off delay from OEx (see Note 5)
5
16
5
18
5
20
ns
Output buffer turn off delay from WEx (see Note 5)
3
11
3
13
3
15
ns
2
2
ns
NOTES: 3. With ac parameters, it is assumed that tT = 2 ns.
4. Access times are measured with output reference levels of VOH = 2 V and VOL = 0.8 V.
5. The maximum values of tREZ, tCEZ, tOEZ, and tWEZ are specified when the outputs are no longer driven. Data-in must not be driven
until one of the applicable maximum values is satisfied.
EDO timing requirements
’16ER72xP-40
MIN
MAX
’16ER72xP-50
MIN
MAX
’16ER72xP-60
MIN
MAX
UNIT
tHPC
tPRWC
Cycle time, EDO page mode, read-write
16
20
25
ns
Cycle time, EDO read-write
45
55
64
ns
tCSH
tCHO
Delay time, RASx active to CASx precharge
34
38
46
ns
Hold time, OEx from CASx
5
7
10
ns
tDOH
tCAS
Hold time, output from CASx
5
5
5
ns
Pulse duration, CASx active
6
tWPE
tOCH
Pulse duration, WEx active (output disable only)
5
5
Setup time, OEx before CASx
5
tCP
tOEP
Pulse duration, CASx precharge
6
Precharge time, OEx
5
8
POST OFFICE BOX 1443
10 000
• HOUSTON, TEXAS 77251−1443
8
10 000
10
10 000
ns
5
ns
5
5
ns
8
10
ns
5
5
ns
SMMS694 − AUGUST 1997
ac timing requirements (see Note 3)
MIN
MAX
’16ER72xP-50
MIN
MAX
’16ER72xP-60
MIN
MAX
UNIT
tRC
tRWC
Cycle time, random read or write
69
84
104
ns
Cycle time, read-write
97
116
140
ns
tRASP
tRAS
Pulse duration, RASx active, fast page mode (see Note 6)
40 100 000
50 100 000
60 100 000
ns
Pulse duration, RASx active, non-page mode (see Note 6)
40
50
60
ns
tRP
tWP
Pulse duration, RASx precharge
25
30
40
ns
Pulse duration, write command
7
9
11
ns
tRASS
tRPS
Pulse duration, RASx active, self-refresh (see Note 9)
7
9
11
ns
Pulse duration, RASx precharge after self-refresh
7
9
11
ns
tASC
tASR
Setup time, column address
0
0
0
ns
Setup time, row address
5
5
5
ns
tDS
tRCS
Setup time, data in (see Note 7)
5
5
5
ns
Setup time, read command
0
0
0
ns
tCWL
tRWL
Setup time, write command before CASx precharge
7
9
11
ns
Setup time, write command before RASx precharge
8
10
12
ns
Setup time, write command before CASx active
(early-write only)
0
0
0
ns
tWRP
tWTS
Setup time, WEx high before RAS low (CBR refresh only)
7
7
7
ns
Setup time, WEx low before RAS low (test mode only)
7
7
7
ns
tCSR
tCAH
Setup time, CASx referenced to RASx ( CBR refresh only )
3
3
3
ns
Hold time, column address
12
8
10
ns
tDH
tRAH
Hold time, data in (see Note 7)
11
13
15
ns
4
6
8
ns
tRCH
tRRH
Hold time, read command referenced to CASx (see Note 8)
0
0
0
ns
Hold time, read command referenced to RASx (see Note 8)
−2
−2
−2
ns
tWCH
tROH
Hold time, write command during CASx active ( early-write only )
7
9
11
ns
Hold time, RASx referenced to OEx
6
8
10
ns
tWRH
tWTH
Hold time, WEx high after RAS low (CBR refresh)
8
10
12
ns
Hold time, WEx low after RAS low (test mode only)
8
10
12
ns
tCHR
tOEH
Hold time, CASx referenced to RASx ( CBR refresh only )
4
6
8
ns
Hold time, OEx command
12
14
16
ns
tCHS
tRHCP
Hold time, CASx active after RASx precharge (self-refresh)
12
14
16
ns
Hold time, RASx active from CASx precharge
27
33
40
ns
tAWD
tCPW
Delay time, column address to write command ( read-write only )
34
41
48
ns
Delay time, WEx low after CASx precharge (read-write only)
37
45
54
ns
tCRP
tCWD
Delay time, CASx precharge to RASx
3
3
3
ns
Delay time, CASx to write command ( read-write only )
31
35
39
ns
tOED
tRAD
Delay time, OEx to data in
13
15
17
ns
Delay time, RASx to column address (see Note 9)
12
tWCS
Hold time, row address
NOTES: 3.
6.
7.
8.
9.
10 000
30
8
10 000
20
10
10 000
25
PRODUCT PREVIEW
’16ER72xP-40
ns
With ac parameters, it is assumed that tT = 2 ns.
In a read-write cycle, tRWD and tRWL must be observed.
Referenced to the later of CASx or WEx in write operations
Either tRCH or tRRH must be satisfied for a read cycle.
The maximum value is specified only to ensure access time.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
9
SMMS694 − AUGUST 1997
ac timing requirements (see Note 3) (continued)
’16ER72xP-40
MIN
MAX
’16ER72xP-50
MIN
MAX
’16ER72xP-60
MIN
MAX
UNIT
tRAL
tCAL
Delay time, column address to RASx precharge
25
30
35
Delay time, column address to CASx precharge
14
17
23
20
ns
tRCD
tRPC
Delay time, RASx to CASx ( see Note 9)
12
12
47
ns
tRSH
tRWD
Delay time, RASx precharge to CASx
31
10
39
ns
3
3
3
ns
Delay time, CASx active to RASx precharge
16
18
20
ns
Delay time, RASx to write command (read-write only)
92
67
79
ns
tTAA
tTCPA
Access time from address (test mode)
30
35
40
ns
Access time from column precharge (test mode)
35
40
45
ns
tTRAC
tREF
Access time from RASx (test mode)
17
55
65
ns
Refresh time interval
32
2
PRODUCT PREVIEW
tT
Transition time
NOTES: 3. With ac parameters, it is assumed that tT = 2 ns.
9. The maximum value is specified only to ensure access time.
10
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
30
32
2
30
2
32
ms
30
ns
SMMS694 − AUGUST 1997
device symbolization (TM16ER72HP illustrated)
TM16ER72HP
-SS
Buffered Key Position
YYMMT
3.3-V Voltage Key Position
YY
MM
T
-SS
=
=
=
=
Year Code
Month Code
Assembly Site Code
Speed Code
PRODUCT PREVIEW
NOTE A: Location of symbolization may vary.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
11
SMMS694 − AUGUST 1997
MECHANICAL DATA
BU (R-PDIM-N168)
DUAL IN-LINE MEMORY MODULE
5.255 (133,48)
5.245 (133,22)
(Note D)
Notch 0.157 (4,00) x 0.122 (3,10) Deep
2 Places
0.050 (1,27)
PRODUCT PREVIEW
0.039 (1,00) TYP
0.125 (3,18)
0.054 (1,37)
0.046 (1,17)
Notch 0.079 (2,00) x 0.122 (3,10) Deep
2 Places
0.014 (0,35) MAX
0.118 (3,00) TYP
0.125 (3,18)
0.700 (17,78) TYP
0.118 (3,00) DIA
2 Places
1.255 (31,88)
1.245 (31,62)
0.106 (2,70) MAX
0.157 (4,00) MAX
(For Double Sided DIMM Only)
4088183/A 07/97
NOTES: A.
B.
C.
D.
E.
12
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Falls within JEDEC MO-161
Dimension includes de-panelization variations; applies between notch and tab edge.
Outline may vary above notches to allow router/panelization irregularities.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
PRODUCT PREVIEW
SMMS694 − AUGUST 1997
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
13
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