TI TMS46100P

TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
D
D
D
D
D
D
D
D
D
Organization . . . 4 194 304 × 1
Single 5 V Power Supply, for TMS44100 / P
(± 10% Tolerance)
Single 3.3 V Power Supply, for TMS46100 / P
(± 10% Tolerance)
Low Power Dissipation ( TMS46100P only)
– 200-µA CMOS Standby
– 200-µA Self Refresh
– 300-µA Extended-Refresh Battery
Backup
Performance Ranges:
’4x100/P-60
’4x100/P-70
’4x100/P-80
DGA PACKAGE
( TOP VIEW )
D
W
RAS
NC
A10
A0
A1
A2
A3
ACCESS ACCESS ACCESS
READ
TIME
TIME
TIME OR WRITE
(tRAC) (tCAC)
(tAA)
CYCLE
(MAX)
(MAX)
(MAX)
(MIN)
60 ns
15 ns
30 ns
110 ns
70 ns
18 ns
35 ns
130 ns
80 ns
20 ns
40 ns
150 ns
VCC
DJ PACKAGE
( TOP VIEW )
1
2
3
4
5
26
25
24
23
22
VSS
Q
CAS
NC
A9
9
10
18
17
11
12
13
16
15
14
A8
A7
A6
A5
A4
D
W
RAS
NC
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
26
25
24
23
22
VSS
Q
CAS
NC
A9
9
10
18
17
11
12
13
16
15
14
A8
A7
A6
A5
A4
PIN NOMENCLATURE
A0 – A10
CAS
D
NC
Q
RAS
W
VCC
VSS
Enhanced Page-Mode Operation for Faster
Memory Access
CAS-Before-RAS ( CBR) Refresh
Long Refresh Period
– 1024-Cycle Refresh in 16 ms
– 128 ms (Max) for Low-Power,
Self-Refresh Version ( TMS4x100P)
3-State Unlatched Output
Texas Instruments EPIC CMOS Process
Operating Free-Air Temperature Range
0°C to 70°C
ADVANCE INFORMATION
D
D
Address Inputs
Column-Address Strobe
Data In
No Connection
Data Out
Row-Address Strobe
Write Enable
5-V or 3.3-V Supply
Ground
description
The TMS4x100 series are high-speed,
4 194 304-bit dynamic random-access memories,
organized as 4 194 304 words of one bit each. The
TMS4x100P series are high-speed, low-power,
self-refresh with extended-refresh, 4 194 304-bit
dynamic random-access memories, organized as
4 194 304 words of one bit each. Both series
employ state-of-the-art EPIC (Enhanced
Performance Implanted CMOS) technology for
high performance, reliability, and low voltage.
DEVICE
POWER
SUPPLY
SELF-REFRESH
BATTERY
BACKUP
REFRESH
CYCLES
TMS44100
5V
—
1024 in 16 ms
TMS44100P
5V
YES
1024 in 128 ms
TMS46100
3.3 V
—
1024 in 16 ms
TMS46100P
3.3 V
YES
1024 in 128 ms
These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. All addresses and data-in lines
are latched on chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TMS4x100 and TMS4x100P are offered in a 20- / 26-lead plastic surface-mount small-outline ( TSOP)
package (DGA suffix) and a 300-mil 20- / 26-lead plastic surface-mount SOJ package (DJ suffix). Both packages
are characterized for operation from 0°C to 70°C.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  1995, Texas Instruments Incorporated
ADVANCE INFORMATION concerns new products in the sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
POST OFFICE BOX 1443
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1
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
logic symbol†
RAM 4096K × 1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
RAS
ADVANCE INFORMATION
CAS
W
D
9
10
11
12
14
15
16
17
18
22
30D11/21D0
A
5
0
4 194 303
31D21/21D10
C30 [ROW]
G33 [REFRESH ROW]
34 [PWR DWN]
C31 [COL]
G34
&
33C32
3
24
2
1
34 EN
33,31D
A, 32D
25
A∇
Q
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
functional block diagram
RAS
CAS
W
Timing and Control
A0
A1
8
ColumnAddress
Buffers
Column Decode
Sense Amplifiers
3
128K Array
128K Array
A10
RowAddress
Buffers
R
o
w
128K Array
16
D
e
c
o
d
e
16
10
128K Array
16
128K Array
16
3
128K Array
10
2
POST OFFICE BOX 1443
I/O
Buffers
1 of 16
Selection
• HOUSTON, TEXAS 77251–1443
DataIn
Reg.
D
DataOut
Reg.
Q
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
operation
enhanced page mode
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the column addresses. This feature allows the TMS4x100 to operate at a higher data bandwidth than
conventional page-mode parts because data retrieval begins as soon as the column address is valid rather than
when CAS transitions low. This performance improvement is referred to as enhanced page mode. A valid
column address can be presented immediately after row-address hold time has been satisfied, usually well in
advance of the falling edge of CAS. In this case, data is obtained after tCAC max (access time from CAS low),
if tAA max (access time from column address) has been satisfied. If column addresses for the next cycle are
valid at the time CAS goes high, access time for the next cycle is determined by the later occurrence of tCAC
or tCPA (access time from rising edge of CAS).
address (A0 – A10)
Twenty-two address bits are required to decode 1 of 4 194 304 storage cell locations. Eleven row-address bits
are set up on inputs A0 through A10 and latched onto the chip by the row-address strobe (RAS). The eleven
column-address bits are set up on A0 through A10 and latched onto the chip by the column-address strobe
(CAS). All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar to a chip
enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select, activating
the output buffer, as well as latching the address bits into the column-address buffer.
write enable (W)
The read or write mode is selected through the write-enable (W) input. A logic high on W selects the read mode
and a logic low selects the write mode. W can be driven from standard TTL circuits (TMS44100 / P) or
low-voltage TTL circuits (TMS46100 / P) without a pullup resistor. The data input is disabled when the read mode
is selected. When W goes low prior to CAS (early write), data out remains in the high-impedance state for the
entire cycle, permitting common I/O operation.
data in (D)
Data is written during a write or read-write cycle. Depending on the mode of operation, the falling edge of CAS
or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to CAS and the data
is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or read-write cycle,
CAS is already low and the data is strobed in by W with setup and hold times referenced to this signal.
data out (Q)
Data out is the same polarity as data in. The output is in the high-impedance (floating) state until CAS is brought
low. In a read cycle, the output becomes valid after the access time interval tCAC (which begins with the negative
transition of CAS) as long as tRAC and tAA are satisfied. The output becomes valid after the access time has
elapsed and remains valid while CAS is low; CAS going high returns it to the high-impedance state. In a
delayed-write or read-write cycle, the output follows the sequence for the read cycle.
POST OFFICE BOX 1443
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3
ADVANCE INFORMATION
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The
maximum number of columns that can be accessed is determined by the maximum RAS low time and the CAS
page cycle time used.
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
refresh
A refresh operation must be performed at least once every 16 ms (128 ms for TMS4x100P) to retain data. This
can be achieved by strobing each of the 1024 rows (A0 – A9). A normal read or write cycle refreshes all bits in
each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level,
conserving power as the output buffer remains in the high-impedance state. Externally generated addresses
must be used for a RAS-only refresh. Hidden refresh can be performed while maintaining valid data at the
output. This is accomplished by holding CAS at VIL after a read operation and cycling RAS after a specified
precharge period, similar to a RAS-only refresh cycle. The external address is ignored during the hidden-refresh
cycle.
CAS-before-RAS (CBR) refresh
CBR refresh is utilized by bringing CAS low earlier than RAS (see parameter tCSR) and holding it low after RAS
falls (see parameter tCHR). For successive CBR refresh cycles, CAS can remain low while cycling RAS. The
external address is ignored and the refresh address is generated internally.
ADVANCE INFORMATION
A low-power battery-backup refresh mode that requires less than 300-µA (TMS46100P) or 500-µA
(TMS44100P) refresh current is available on the low-power devices. Data integrity is maintained using CBR
refresh with a period of 125 µs while holding RAS low for less than 1 µs. To minimize current consumption, all
input levels need to be at CMOS levels ( VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V ).
self refresh
The self-refresh mode is entered by dropping CAS low prior to RAS going low. CAS and RAS are both held low
for a minimum of 100 µs. The chip is then refreshed by an on-board oscillator. No external address is required
because the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS and CAS
are brought high to satisfy tCHS. Upon exiting the self-refresh mode, a burst refresh (refresh a full set of row
addresses) must be executed before continuing with normal operation. This ensures the DRAM is fully
refreshed.
power up
To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles
is required after full VCC level is achieved. These eight initialization cycles must include at least one refresh
(RAS-only or CBR) cycle.
test mode
An industry-standard design-for-test (DFT) mode is incorporated in the TMS4x100 and TMS4x100P. A CBR
cycle with W low (WCBR) cycle is used to enter the test mode. In the test mode, data is written into and read
from eight sections of the array in parallel. Data is compared upon reading and if all bits are equal, the data-out
terminal goes high. If any one bit is different, the data-out terminal goes low. Any combination of read, write,
read-write, or page-mode cycles can be used in the test mode. The test-mode function reduces test times by
enabling the 4-Mbit DRAM to be tested as if it were a 512K DRAM, where row address 10, column address 10,
and column address 0 are not used. A RAS-only or CBR refresh cycle is used to exit the DFT mode.
4
POST OFFICE BOX 1443
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TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
test mode (continued)
Exit Cycle
Entry Cycle
Normal
Mode
Test-Mode Cycle
RAS
CAS
W
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC:
TMS44100, TMS44100P . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
TMS46100, TMS46100P . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Voltage range on any pin (see Note 1): TMS44100, TMS44100P . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
TMS46100, TMS46100P . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
TMS44100 / P
TMS46100 / P
MIN
NOM
MAX
MIN
NOM
5
3.3
VCC
VIH
Supply voltage
4.5
5.5
3
High-level input voltage
2.4
6.5
2
VIL
Low-level input voltage (see Note 2)
–1
0.8
– 0.3
MAX
3.6
VCC + 0.3
0.8
UNIT
V
V
V
TA
Operating free-air temperature
0
70
0
70
°C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
5
ADVANCE INFORMATION
† The states of W, data in, and address are defined by the type of cycle used during test mode.
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
VOH
VOL
High-level output voltage
Low-level output voltage
’44100 - 60
’44100P - 60
TEST
CONDITIONS
MIN
IOH = – 5 mA
IOL = 4.2 mA
’44100 - 70
’44100P - 70
MAX
2.4
MIN
MAX
2.4
’44100 - 80
’44100P - 80
MIN
UNIT
MAX
2.4
V
0.4
0.4
0.4
V
± 10
± 10
± 10
µA
ADVANCE INFORMATION
II
Input current (leakage)
VCC = 5.5 V,
VI = 0 V to 6.5 V,
All others = 0 V to VCC
IO
Output current (leakage)
VCC = 5.5 V,
CAS high
VO = 0 V to VCC,
± 10
± 10
± 10
µA
ICC1
Read- or write-cycle current
(see Note 3)
VCC = 5.5 V,
Minimum cycle
105
90
80
mA
2
2
2
mA
1
1
1
mA
500
500
500
µA
105
90
80
mA
90
80
70
mA
500
500
500
µA
5
5
5
mA
500
500
500
µA
After 1 memory cycle,
RAS and CAS high,
VIH = 2.4 V ( TTL)
ICC2
Standby current
After 1 memory cycle,
RAS and CAS high,
g ,
VIH = VCC – 0.2 V
(CMOS)
’44100
’44100P
ICC3
Average refresh current
(RAS only or CBR)
(see Note 4)
VCC = 5.5 V,
Minimum cycle,
RAS cycling,
CAS high (RAS only);
RAS low after CAS low (CBR)
ICC4
Average page current
(see Notes 3 and 5)
VCC = 5.5 V,
RAS low,
ICC6†
Self-refresh current
(see Note 3)
CAS ≤ 0.2 V,
RAS < 0.2 V,
tRAS and tCAS > 1000 ms
ICC7
Standby current, outputs
enabled (see Note 3)
RAS = VIH,
CAS = VIL,
Data out = enabled
Battery-backup current
(with CBR)
tRC = 125 µs, tRAS ≤ 1 ms,
VCC – 0.2 V ≤ VIH ≤ 6.5 V,
0 V ≤ VIL ≤ 0.2 V,
W and OE = VIH,
Address and data stable
ICC10†
tPC = minimum,
CAS cycling
† For TMS44100P only
NOTES: 3. ICC max is specified with no load connected.
4. Measured with a maximum of one address change while RAS = VIL
5. Measured with a maximum of one address change while CAS = VIH
6
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TEST
CONDITIONS
VOH
High-level
g
output voltage
IOH = – 2 mA (LVTTL)
IOH = – 100 µA (LVCMOS)
VOL
Low-level
output voltage
IOL = 2 mA (LVTTL)
IOL = 100 µA (LVCMOS)
II
Input current
(leakage)
IO
ICC1
ICC2
’46100 - 60
’46100P - 60
’46100 - 70
’46100P - 70
’46100 - 80
’46100P - 80
MIN
MIN
MIN
MAX
2.4
MAX
2.4
VCC – 0.2
UNIT
MAX
2.4
VCC – 0.2
V
VCC – 0.2
0.4
0.4
0.4
0.2
0.2
0.2
VI = 0 V to 3.9 V, VCC = 3.6 V,
All others = 0 V to VCC
± 10
± 10
± 10
µA
Output current
(leakage)
VO = 0 V to VCC, VCC = 3.6 V,
CAS high
± 10
± 10
± 10
µA
Read- or
write-cycle
current
(see Note 3)
Minimum cycle,
70
60
50
mA
2
2
2
mA
’46100
300
300
300
µA
’46100P
200
200
200
µA
Standby
current
VCC = 3.6 V
After 1 memory cycle,
RAS and CAS high,
VIH = 2.0 V (LVTTL)
After 1 memory cycle,
RAS and CAS high,
g ,
VIH = VCC – 0.2 V
(LVCMOS)
V
ICC3
Average
refresh current
(RAS only or
CBR)
(see Note 4)
Minimum cycle, VCC = 3.6 V,
RAS cycling,
CAS high (RAS only);
RAS low after CAS low (CBR)
70
60
50
mA
ICC4
Average page
current
(see Notes 3
and 5)
tPC = minimum,
RAS low,
VCC = 3.6 V,
CAS cycling
60
50
40
mA
ICC6†
Self-refresh
current
(see Note 3)
CAS ≤ 0.2 V,
RAS < 0.2 V,
tRAS and tCAS > 1000 ms
200
200
200
µA
ICC7
Standby
current,
outputs
enabled
(see Note 3)
RAS = VIH,
CAS = VIL,
Data out = enabled
5
5
5
mA
ICC10†
tRC = 125 µs,
tRAS ≤ 1 ms,
Battery-backup VCC – 0.2 V ≤ VIH ≤ 3.9 V,
current
0 V ≤ VIL ≤ 0.2 V,
(with CBR)
W and OE = VIH,
Address and data stable
300
300
300
µA
ADVANCE INFORMATION
PARAMETER
† For TMS46100P only
NOTES: 3. ICC max is specified with no load connected.
4. Measured with a maximum of one address change while RAS = VIL
5. Measured with a maximum of one address change while CAS = VIH
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
7
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 6)
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, A0 – A10
5
pF
Ci(RC)
Input capacitance, CAS and RAS
7
pF
Ci(W)
Input capacitance, W
7
pF
Co
Output capacitance
7
pF
NOTE 6: VCC = 5 V ± .5 V for the TMS44100 devices, VCC = 3.3 V ± 0.3 V for the TMS46100 devices, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
’4x100 - 60
’4x100P - 60
’4x100 - 70
’4x100P - 70
’4x100 - 80
’4x100P - 80
MIN
MIN
MIN
MAX
MAX
UNIT
MAX
ADVANCE INFORMATION
tAA
tCAC
Access time from column address
30
35
40
ns
Access time from CAS low
15
18
20
ns
tCPA
tRAC
Access time from column precharge
35
40
45
ns
Access time from RAS low
60
70
80
ns
tCLZ
tOFF
CAS to output in low impedance
0
Output disable time after CAS high (see Note 7)
0
NOTE 7: tOFF is specified when the output is no longer driven.
8
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
0
15
0
0
18
0
ns
20
ns
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’4x100 - 60
’4x100P - 60
’4x100 - 70
’4x100P - 70
’4x100 - 80
’4x100P - 80
MIN
MIN
MIN
MAX
UNIT
MAX
tRC
tRWC
Cycle time, random read or write (see Note 8)
110
130
150
ns
Cycle time, read-write (see Note 8)
130
153
175
ns
tPC
tPRWC
Cycle time, page-mode read or write (see Notes 8 and 9)
40
45
50
ns
Cycle time, page-mode read-write (see Note 8)
60
68
75
ns
tRASP
tRAS
Pulse duration, RAS low, page mode (see Note 10)
60 100 000
70 100 000
80 100 000
ns
Pulse duration, RAS low, nonpage mode (see Note 10)
60
70
80
ns
tRASS
tCAS
Pulse duration, RAS low, self refresh
Pulse duration, CAS low, (see Note 11)
15
tCP
tRP
Pulse duration, CAS high
10
10
10
ns
Pulse duration, RAS high (precharge)
40
50
60
ns
tRPS
tWP
Precharge time after self refresh using RAS
140
130
150
ns
10
10
10
ns
tASC
tASR
Setup time, column address before CAS low
0
0
0
ns
Setup time, row address before RAS low
0
0
0
ns
tDS
tRCS
Setup time, data (see Note 12)
0
0
0
ns
Setup time, W high before CAS low
0
0
0
ns
tCWL
tRWL
Setup time, W low before CAS high
15
18
20
ns
Setup time, W low before RAS high
15
18
20
ns
tWCS
tWSR
Setup time, W low before CAS low (early-write operation only)
0
0
0
ns
Setup time, W high (CBR refresh only)
10
10
10
ns
tWTS
tCAH
Setup time, W low (test mode only)
10
10
10
ns
Hold time, column address after CAS low
10
15
15
ns
tDHR
tDH
Hold time, data after RAS low (see Note 13)
50
55
60
ns
Hold time, data (see Note 12)
10
15
15
ns
tAR
tRAH
Hold time, column address after RAS low (see Note 13)
50
55
60
ns
Hold time, row address after RAS low
10
10
10
ns
tRCH
tRRH
Hold time, W high after CAS high (see Note 14)
0
0
0
ns
Hold time, W high after RAS high (see Note 14)
0
0
0
ns
tWCH
tWCR
Hold time, W low after CAS low (early-write operation only)
10
15
15
ns
Hold time, W low after RAS low (see Note 13)
50
55
60
ns
tWHR
tWTH
Hold time, W high (CBR refresh only)
10
10
10
ns
Hold time, W low (test mode only)
10
10
10
ns
Delay time, column address to W low
(read-write operation only)
30
35
40
ns
Delay time, RAS low to CAS high (CBR refresh only)
10
10
10
ns
0
0
ns
70
80
ns
tAWD
tCHR
tCRP
100
Pulse duration, write
Delay time, CAS high to RAS low
10 000
100
10 000
0
tCSH
Delay time, RAS low to CAS high
60
NOTES: 8. All cycle times assume tT = 5 ns.
9. To assure tPC min, tASC should be ≥ 5 ns.
10. In a read-write cycle, tRWD and tRWL must be observed.
11. In a read-write cycle, tCWD and tCWL must be observed.
12. Referenced to the later of CAS or W in write operations
13. The minimum value is measured when tRCD is set to tRCD min as a reference.
14. Either tRRH or tRCH must be satisfied for a read cycle.
POST OFFICE BOX 1443
10 000
• HOUSTON, TEXAS 77251–1443
18
10 000
µs
100
10 000
20
10 000
ns
ADVANCE INFORMATION
MAX
9
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
’4x100 - 60
’4x100P - 60
MIN
’4x100 - 70
’4x100P - 70
MAX
MIN
MAX
’4x100 - 80
’4x100P - 80
MIN
UNIT
MAX
ADVANCE INFORMATION
tCSR
tCHS
Delay time, CAS low to RAS low (CBR refresh only)
tCWD
tRAD
Delay time, CAS low to W low (read-write operation only)
Delay time, RAS low to column address (see Note 15)
15
tRAL
tCAL
Delay time, column address to RAS high
30
35
40
Delay time, column address to CAS high
30
35
40
tRCD
tRPC
Delay time, RAS low to CAS low (see Note 15)
20
Delay time, RAS high to CAS low
0
0
0
ns
tRSH
tRWD
Delay time, CAS low to RAS high
15
18
20
ns
Delay time, RAS low to W low (read-write operation only)
60
70
80
ns
tTAA
tTCPA
Access time from address (test mode)
35
40
45
ns
Access time from column precharge (test mode)
40
45
50
ns
tTRAC
Access time from RAS (test mode)
tREF
Hold time, CAS low after RAS high, self refresh
5
5
5
ns
– 50
– 50
– 50
ns
15
18
20
30
45
65
’4x100
Refresh time interval
’4x100P
tT
Transition time
NOTE 15: The maximum value is specified only to assure access time.
2
15
20
35
52
75
15
20
ns
40
ns
ns
60
85
ns
16
16
ms
128
128
128
ms
50
ns
50
1.31 V
2
50
2
VCC = 5 V
RL = 218 Ω
R1 = 828 Ω
Output Under Test
CL = 100 pF
CL = 100 pF
(a) LOAD CIRCUIT
POST OFFICE BOX 1443
R2 = 295 Ω
(b) ALTERNATE LOAD CIRCUIT
Figure 1. Load Circuits for Timing Parameters
10
• HOUSTON, TEXAS 77251–1443
ns
16
PARAMETER MEASUREMENT INFORMATION
Output Under Test
ns
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
1.4 V
VCC = 3.3 V
RL = 500 Ω
R1 = 1178 Ω
Output Under Test
Output Under Test
CL = 100 pF
CL = 100 pF
(a) LOAD CIRCUIT
R2 = 868 Ω
(b) ALTERNATE LOAD CIRCUIT
ADVANCE INFORMATION
Figure 2. Low-Voltage Load Circuits for Timing Parameters
tRC
tRAS
RAS
tRP
tCSH
tRCD
tCRP
tRSH
tCAS
tT
CAS
tRAD
tCP
tASC
tASR
tRAL
tRAH
A0 – A10
tCAL
Row
Column
Don’t Care
tRCS
tRRH
tAR
tRCH
tCAH
W
Don’t Care
Don’t Care
tCAC
tOFF
tAA
Q
Hi-Z
See Note A
Valid Data Out
tCLZ
tRAC
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 3. Read-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
11
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tT
tRSH
tRCD
tRP
tCAS
tCRP
tCSH
CAS
tASC
tCAH
tRAH
tASR
tRAL
tAR
ADVANCE INFORMATION
A0 – A10
tCP
tCAL
Row
Column
Don’t Care
tCWL
tRWL
tRAD
tWCH
tWCR
tWCS
W
Don’t Care
Don’t Care
tDH
tWP
tDS
D
Don’t Care
Valid Data
tDHR
Hi-Z
Q
Figure 4. Early-Write-Cycle Timing
12
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tT
tRSH
tRCD
tRP
tCRP
tCAS
tCSH
CAS
tASC
tCAL
tRAH
tCAH
tAR
Row
Don’t Care
Column
tCWL
tRAD
tRWL
tDS
W
ADVANCE INFORMATION
tRAL
tASR
A0 – A10
tCP
Don’t Care
Don’t Care
tWP
tWCR
tDH
tDHR
D
Valid Data
Don’t Care
tCLZ
Don’t Care
tOFF
Invalid
Q
Figure 5. Write-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
13
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tRWC
tRAS
RAS
tT
tRP
tCAS
tRCD
tCRP
CAS
tASR
tRAH
tCP
tASC
tRAD
tCAH
tAR
A0 – A10
Row
Column
Don’t Care
ADVANCE INFORMATION
tCWL
tCAH
tRWL
tRCS
tWP
tAWD
W
Don’t Care
Don’t Care
tCWD
tRWD
tDS
D
Don’t Care
Valid In
tDH
tCLZ
(see Note A)
Q
Don’t Care
tOFF
Valid Out
Hi-Z
tCAC
tAA
tRAC
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 6. Read-Write-Cycle Timing
14
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tPC
tRCD
tCSH
tCRP
tCP
tT
tRSH
tCAS
CAS
A0 – A10
tCAH
tRAL
tCAL
tASC
Row
Column
Column
tAA
(see Note A)
tAR
tRCS
W
Don’t Care
ADVANCE INFORMATION
tRAH
tASR
tRRH
tRCH
tRAD
tCPA
(see Note A)
tCAC
tAA
tOFF
tRAC
tCLZ
Q
See Note B
Valid
Out
Valid Out
NOTES: A. Access time is tCPA or tAA dependent.
B. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 7. Enhanced-Page-Mode Read-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
15
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tCSH
tCRP
tPC
tRCD
tRSH
tCAS
CAS
tASR
tASC
tCP
tAR
tRAH
A0 – A10
tRAL
tCAL
tCAH
Row
Column
Don’t Care
Column
ADVANCE INFORMATION
tRAD
tCWL
tCWL
tWCR
tWP
tRWL
tDHR
W
Don’t Care
Don’t Care
See Note A
tDS
tDS
D
Don’t Care
See Note A
tDH
tDH
(see Note A)
See Note A
Valid
Data In
Valid Data In
Don’t Care
Hi-Z
Q
NOTES: A. Referenced to CAS or W, whichever occurs last
B. A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not
violated.
Figure 8. Enhanced-Page-Mode Write-Cycle Timing
16
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tPRWC
tCRP
tCP
tCSH
tRCD
tRSH
tCAS
CAS
tRAD
tASR
tASC
tCAH
tRAH
A0 – A10
Row
Column
Column
Don’t Care
tCWD
tRCS
tAWD
tCWL
tRWL
tWP
tRWD
ADVANCE INFORMATION
tAR
W
tDS
tDH
D
Valid
Don’t Care
Don’t Care
Valid
tCAC
tOFF
tCLZ
tAA
Don’t Care
tCPA
tRAC
tCLZ
See Note A
Valid
Out
Q
See Note A
Valid Out
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.
Figure 9. Enhanced-Page-Mode Read-Write-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
17
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tRP
tCRP
tCRP
tT
CAS
tRPC
Don’t Care
tRAH
tASR
Don’t Care
A0 – A10
Row
Don’t Care
See Note A
ADVANCE INFORMATION
W
Don’t Care
D
Don’t Care
Q
NOTE A: A10 is a don’t care.
Figure 10. RAS-Only Refresh-Cycle Timing
18
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
Row
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tRC
tRP
tRAS
RAS
tCSR
tRPC
tCHR
tT
CAS
tWSR
tWHR
A0 – A10
Don’t Care
D
Don’t Care
Q
Hi-Z
ADVANCE INFORMATION
W
Figure 11. Automatic CBR-Refresh-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
19
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tRP
tRPS
tRASS
RAS
tCSR
tRPC
tCHS
tT
CAS
tWSR
tWHR
W
Don’t Care
D
Don’t Care
Q
Hi-Z
ADVANCE INFORMATION
A0 – A10
Figure 12. Self-Refresh-Cycle Timing
20
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Refresh Cycle
Memory Cycle
tRP
tRAS
tRP
tRAS
RAS
tCHR
tCAS
CAS
tAR
tCAH
tASC
tRAH
A0 – A10
Row
ADVANCE INFORMATION
tASR
Don’t Care
Col
tRRH
tWHR
tWHR
tWSR
tRCS
tWSR
tWHR
tWSR
W
D
Don’t Care
tRAC
tAA
tCAC
tOFF
tCLZ
Q
Valid Data
Figure 13. Hidden-Refresh-Cycle (Read) Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
21
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Memory Cycle
Refresh Cycle
tRP
tRAS
tRP
tRAS
RAS
tCHR
tCAS
CAS
tCAH
tASC
tRAH
tAR
tASR
ADVANCE INFORMATION
Row
A0 – A10
Col
Don’t Care
tRRH
tWCS
tWHR
tWSR
tWCR
tWP
W
tWCH
tDH
tDHR
tDS
D
Don’t Care
Q
Hi-Z
Figure 14. Hidden-Refresh-Cycle (Write) Timing
22
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tRC
tRP
tRAS
RAS
tCSR
tRPC
tCHR
tT
CAS
tWTH
tWTS
A0 – A10
Don’t Care
D
Don’t Care
Q
Hi-Z
ADVANCE INFORMATION
Don’t Care
W
Figure 15. Test-Mode Entry Cycle
device symbolization (TMS44100 illustrated)
-SS
Speed ( - 60, - 70, - 80)
TMS44100
Low-Power / Self-Refresh Designator (blank or P)
DJ
Package Code
W
B
Y
M LLL
P
Asembly Site Code
Lot Traceability Code
Month Code
Year Code
Die Revision Code
Wafer Fab Code
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
23
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
24
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
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