SN74ALS233B 16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SCAS253B – MARCH 1990 – REVISED APRIL 1998 D D D D D D Independent Asychronous Inputs and Outputs 16 Words by 5 Bits Data Rates From up to 40 MHz Fall-Through Time 14 ns Typ 3-State Outputs Package Options Include Plastic Small-Outline Package (DW), Plastic Chip Carriers (FN), and Standard Plastic 300-mil DIPs (N) description DW OR N PACKAGE (TOP VIEW) OE FULL–1 FULL LDCK D0 D1 D2 D3 D4 GND This 80-bit memory uses advanced low-power Schottky technology and features high speed and a fast fall-through time. It is organized as 16 words by 5 bits. Data is written into memory on a low-to-high transition at the load clock (LDCK) input and is read out on a low-to-high transition at the unload clock (UNCK) input. The memory is full when the number of words clocked in exceeds by 16 the number of words clocked out. When the memory is full, LDCK signals have no effect. When the memory is empty, UNCK signals have no effect. 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC EMPTY+1 UNCK EMPTY Q0 Q1 Q2 Q3 Q4 RST FULL FULL–1 OE VCC EMPTY+1 FN PACKAGE (TOP VIEW) LDCK D0 D1 D2 D3 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 UNCK EMPTY Q0 Q1 Q2 D4 GND RST Q4 Q3 A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. This FIFO is designed to process data at rates up to 40 MHz in a bit-parallel format, word by word. 1 Status of the FIFO memory is monitored by the FULL, EMPTY, FULL–1, and EMPTY+1 output flags. The FULL output is low when the memory is full and high when it is not full. The FULL–1 output is low when the memory contains 15 data words. The EMPTY output is low when the memory is empty and high when it is not empty. The EMPTY+1 output is low when one word remains in memory. A low level on the reset (RST) input resets the internal stack control pointers and also sets EMPTY low and sets FULL, FULL–1, and EMPTY+1 high. The Q outputs are not reset to any specific logic level. The first low-to-high transition on LDCK, after either a RST pulse or from an empty condition, causes EMPTY to go high and the data to appear on the Q outputs. It is important to note that the first word does not have to be unloaded. Data outputs are noninverting with respect to the data inputs and are at high impedance when the output-enable (OE) input is low. OE does not affect the output flags. Cascading is easily accomplished in the word-width direction but is not possible in the word-depth direction. The SN74ALS233B is characterized for operation from 0°C to 70°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ALS233B 16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SCAS253B – MARCH 1990 – REVISED APRIL 1998 logic symbol† FIFO 16 × 5 (ALS233B) CTR RST LDCK UNCK OE D0 D1 D2 D3 D4 11 4 18 CT = 0 CT = 15 1(+/C2) 3– 1 5 6 (CT = 16) G1 CT = 1 (CT = 0) G3 3 2 19 17 FULL FULL–1 EMPTY+1 EMPTY EN4 2D 4 16 15 7 14 8 13 9 12 Q0 Q1 Q2 Q3 Q4 † This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. The symbol is functionally accurate but does not show the details of implementation; for these, see the logic diagram. The symbol represents the memory as if it were controlled by a single counter whose content is the number of words stored at the time. Output data is invalid when the counter content (CT) is 0. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALS233B 16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SCAS253B – MARCH 1990 – REVISED APRIL 1998 logic diagram (positive logic) 1 OE Ring Counter CTR DIV 16 1D 4 C1 LDCK S R Ring Counter CTR DIV 16 1 2 3 4 5 6 7 8 + 9 10 Read 11 12 Address 13 14 CT = 1 15 16 18 C1 UNCK 1 2 3 4 5 6 7 8 + 9 10 Write 11 Address 12 13 14 CT = 1 15 16 1D 11 RST 16 RAM 16 × 5 EN 16 16 1A 1 16 2A 1 16 C3 D0 D1 D2 D3 D4 5 1A, 3D 6 2A 16 15 7 14 8 13 9 12 16 16 COMP P=Q Q1 Q2 Q3 Q4 17 P Q Q0 EMPTY P=Q+2 P=Q–2 S 3 FULL R 2 FULL–1 19 EMPTY+1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74ALS233B 16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SCAS253B – MARCH 1990 – REVISED APRIL 1998 timing diagram RST LDCK ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ D0–D4 W1 W2 Don’t Care W3 W1 W2 W3 W14 W15 W16 UNCK Q0–Q4 Invalid Word 1 Word 2 Word 3 Invalid Word 1 Word 2 Word 3 Word 4 EMPTY EMPTY+1 FULL FULL–1 Initialize Pointers Unload W2 Empty Empty+1 Full–1 Full Load W1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Package thermal impedance, θJA (see Note 1): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALS233B 16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SCAS253B – MARCH 1990 – REVISED APRIL 1998 recommended operating conditions (see Note 2) VCC VIH Supply voltage VIL Low-level input voltage IOH High level output current High-level IOL Low level output current Low-level High-level input voltage MIN NOM MAX 4.5 5 5.5 2 UNIT V V 0.8 Q outputs –1.6 Status flags –0.4 Q outputs 24 Status flags 8 V mA mA TA Operating free-air temperature 0 70 °C NOTE 2: To ensure proper operation of this high-speed FIFO device, it is necessary to provide a clean signal to the LDCK and UNCK clock inputs. Any excessive noise or glitching on the clock inputs that violates the VIL, VIH, or minimum pulse duration limits can cause a false clock or improper operation of the internal read and write pointers. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS Q outputs VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = –2.6 mA Status flags VCC = 4.5 V to 5.5 V, Q outputs VCC = 4 4.5 5V IOH = –0.4 mA IOL = 12 mA Status flags VCC = 4 4.5 5V VOL IOZH IOZL VCC = 5.5 V, VCC = 5.5 V, II IIH VCC = 5.5 V, VCC = 5.5 V, IIL IO‡ VCC = 5.5 V, VCC = 5.5 V, MIN TYP† 2.4 3.2 MAX UNIT –1.2 V V VCC–2 0.25 0.4 IOL = 24 mA IOL = 4 mA 0.35 0.5 0.25 0.4 IOL = 8 mA VO = 2.7 V 0.35 0.5 20 VO = 0.4 V VI = 7 V VI = 2.7 V VI = 0.4 V VO = 2.25 V –30 V µA –20 µA 0.1 mA 20 µA –0.2 mA –112 mA ICC VCC = 5.5 V 88 133 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74ALS233B 16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SCAS253B – MARCH 1990 – REVISED APRIL 1998 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) MIN fclock l k tw tsu th Clock frequency Pulse duration Setup time Hold time NOM MAX LDCK 40 UNCK 40 RST low 18 LDCK low 15 LDCK high 10 UNCK low 15 UNCK high 10 Data before LDCK↑ 8 RST (inactive) before LDCK↑ 5 LDCK (inactive) before RST↑ 5 Data after LDCK↑ 5 UNIT MHz ns ns ns switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) fmax LDCK, UNCK 40 LDCK↑ 6 32 6 30 5 25 6 27 5 25 7 34 7 34 8 31 9 33 8 32 tpd d tPLH tPHL tpd d tPLH tpd d tPLH tPHL tPLH ten tdis 6 TO (OUTPUT) Any Q UNCK↑ LDCK↑ EMPTY UNCK↑ EMPTY RST↓ LDCK↑ UNCK↑ RST↓ EMPTY 1 EMPTY+1 EMPTY+1 LDCK↑ FULL 1 FULL–1 UNCK↑ MIN MAX UNIT MHz ns ns ns ns ns ns RST↓ FULL–1 11 32 ns LDCK↑ FULL 6 27 ns 5 25 9 30 UNCK↑ FULL RST↓ ns OE↑ Q 2 15 ns OE↓ Q 1 15 ns POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALS233B 16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SCAS253B – MARCH 1990 – REVISED APRIL 1998 PARAMETER MEASUREMENT INFORMATION 7V Open PARAMETER S1 ten R1 = 500 Ω From Output Under Test CL = 50 pF (see Note A) tPZH tPZL tPHZ tPLZ tPLH tPHL tdis Test Point R2 = 500 Ω tpd S1 Open Closed Open Closed Open Open LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V High-Level Pulse 1.3 V 0.3 V tw 3.5 V Timing Input 3.5 V 1.3 V 0.3 V th tsu Low-Level Pulse 1.3 V VOLTAGE WAVEFORMS PULSE DURATION 1.3 V 1.3 V 1.3 V 0.3 V 3.5 V Data Input 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3.5 V Output Control 3.5 V Input (see Note C) 1.3 V 1.3 V 0.3 V tPZL 1.3 V tPLZ 0.3 V tPHL tPLH In-Phase Output VOH 1.3 V VOL 1.3 V Out-of-Phase Output VOH 1.3 V 1.3 V 3.5 V Waveform 1 S1 Closed (see Note B) 1.3 V tPZH tPLH tPHL Waveform 2 S1 Open (see Note B) VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.3 V tPHZ VOL 0.3 V VOH 1.3 V 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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