iC-NQC
preliminary
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev B1, Page 1/29
FEATURES
APPLICATIONS
♦ Resolution of up to 8,192 angle steps per sine period
♦ Binary and decimal resolution settings, e.g. 500, 512, 1000,
1024; programmable angle hysteresis
♦ Count-safe vector follower principle, real-time system with
70 MHz sampling rate
♦ Conversion time of just 250 ns including amplifier settling
♦ Direct sensor connection; selectable input gain
♦ Input frequency of up to 250 kHz
♦ Signal conditioning for offset, amplitude and phase
♦ A/B quadrature signals of up to 2 MHz with adjustable
minimum transition distance
♦ Zero signal processing, adjustable in index position and width
♦ Absolute angle output via fast serial interface (BiSS, SSI)
♦ Permanent bidirectional memory access to parameters and
OEM data by BiSS C
♦ Period counting with up to 24 bits
♦ Error monitoring of frequency, amplitude and configuration
♦ Device setup from serial EEPROM or using BiSS
♦ ESD protection and TTL-/CMOS-compatible outputs
♦ Interpolator IC for angle
resolution from sine/cosine
sensor signals
♦ Optical encoders
♦ MR sensor systems
PACKAGES
TSSOP20
BLOCK DIAGRAM
Copyright © 2010 iC-Haus
http://www.ichaus.com
iC-NQC
preliminary
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev B1, Page 2/29
DESCRIPTION
iC-NQC is a monolithic A/D converter which, by applying a count-safe vector follower principle, converts
sine/cosine sensor signals with a selectable resolution and hysteresis into angle position data.
This absolute value is output via a bidirectional,
synchronous-serial I/O interface in BiSS C protocol
and trails a master clock rate of up to 10 Mbit/s. Alternatively, this value can be output so that it is compatible with SSI in Gray or binary code, with or without
error bits. The device also supports double transmission in SSI ring mode.
Signal periods are logged quickly by a 24-bit period
counter that can supplement the output data with an
upstream multiturn position value.
At the same time any changes in angle are converted into incremental A QUAD B signals. Here, the
minimum transition distance can be stipulated and
adapted to suit the system on hand (cable length, external counter). A synchronized zero index Z is generated if enabled by PZERO and NZERO.
The front-end amplifiers are configured as instrumentation amplifiers, permitting sensor bridges to be di-
rectly connected without the need for external resistors. Various programmable D/A converters are available for the conditioning of sine/cosine sensor signals
with regard to offset, amplitude ratio and phase errors (offset compensation by 8-bit DAC, gain ratio by
5-bit DAC, phase compensation by 6-bit DAC).
The front-end gain can be set in stages graded to
suit all common complementary sensor signals from
approximately 20 mVpp to 1.5 Vpp and also noncomplementary sensor signals from 40 mVpp to 3
Vpp respectively.
The device can be configured using two bidirectional
interfaces, the EEPROM interface from a serial EEPROM with I2 C interface, or the I/O interface in BiSS
C protocol. Free storage space on the EEPROM can
be accessed via BiSS for the storage of additional
data.
After a low voltage reset, iC-NQC reads in the configuration data including the check sum (CRC) from the
EEPROM and repeats the process if a CRC error is
detected.
preliminary
iC-NQC
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev B1, Page 3/29
CONTENTS
CONTENTS . . . . . . . . . . . . . . . . . . .
3
TEST FUNCTIONS
18
PACKAGES
4
I/O INTERFACE: BiSS C PROTOCOL
19
ABSOLUTE MAXIMUM RATINGS
5
THERMAL DATA
5
ELECTRICAL CHARACTERISTICS
CHARACTERISTICS: Diagrams . . . . . . .
6
8
OPERATING REQUIREMENTS: I/O Interface
9
Interface Parameters With BiSS C Protocol .
19
Example Of BiSS Data Output . . . . . . . .
20
Register Communication . . . . . . . . . . . .
20
Internal Reset Function . . . . . . . . . . . .
20
Short BiSS Timeout . . . . . . . . . . . . . .
20
I/O INTERFACE: SSI Protocol
Examples Of SSI Data Output
PARAMETER and REGISTER
10
SIGNAL CONDITIONING
11
CONVERTER FUNCTIONS
12
MAXIMUM POSSIBLE CONVERTER
FREQUENCY
Serial data output . . . . . . . . . . . . . . .
Incremental output to A, B and Z . . . . . . .
13
13
14
INCREMENTAL SIGNALS
15
SIGNAL MONITORING and ERROR
MESSAGES
17
22
. . . . . . . .
EEPROM INTERFACE
Example of CRC Calculation Routine . . . . .
23
24
24
STARTUP BEHAVIOR
25
APPLICATION NOTES
26
Principle input circuits . . . . . . . . . . . . .
26
Basic circuit . . . . . . . . . . . . . . . . . . .
27
EVALUATION BOARD
27
DESIGN REVIEW: Function Notes
27
preliminary
iC-NQC
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev B1, Page 4/29
PACKAGES TSSOP20 (according to JEDEC Standard)
PIN CONFIGURATION
TSSOP20 4.4 mm, lead pitch 0.65 mm
PIN FUNCTIONS
No. Name Function
1
2
3
4
5
6
PCOS
NCOS
VDDA
GNDA
VREF
A
Input Cosine +
Input Cosine +5 V Supply Voltage (analog)
Ground (analog)
Reference Voltage Output
Incremental Output A
Analog signal COS+ (TMA mode)
PWM signal for Offset Sine (calib.)
7 B
Incremental Output B
Analog signal COS- (TMA mode)
PWM signal for Offset Cosine (calib.)
8 Z
Incremental Output Z
PWM signal for Phase/Ratio (calib.)
9 GND
Ground
10 VDD
+5 V Supply Voltage (digital)
11 SLI
I/O Interface, data input*
12 MA
I/O Interface, clock line
13 SLO
I/O Interface, data output
14 SDA
EEPROM interface, data line
Analog signal SIN+ (TMA mode)
15 SCL
EEPROM interface, clock line
Analog signal SIN- (TMA mode)
16 NERR Error Input/Output, active low
17 PZERO Input Zero Signal +
18 NZERO Input Zero Signal 19 PSIN
Input Sine +
20 NSIN
Input Sine External connections linking VDDA to VDD and GND to GNDA are required.
*) If only a single iC-NQC is used and no chain circuitry of multiple BiSS slaves, pin SLI can remain unwired or
can be linked to ground (GND).
preliminary
iC-NQC
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev B1, Page 5/29
ABSOLUTE MAXIMUM RATINGS
These ratings do not imply permissible operating conditions; functional operation is not guaranteed.
Exceeding these ratings may damage the device.
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Max.
G001 VDDA
Voltage at VDDA
-0.3
6
V
G002 VDD
G003 Vpin()
Voltage at VDD
-0.3
6
V
-0.3
6
V
Voltage at
PSIN, NSIN, PCOS, NCOS, PZERO,
NZERO, VREF, NERR, SCL,
SDA, MA, SLI, SLO, A, B, Z
G004 Imx(VDDA) Current in VDDA
V() < VDDA + 0.3 V
V() < VDD + 0.3 V
-50
50
mA
G005 Imx(GNDA) Current in GNDA
-50
50
mA
G006 Imx(VDD)
Current in VDD
-50
50
mA
G007 Imx(GND) Current in GND
-50
50
mA
G008 Imx()
Current in
PSIN, NSIN, PCOS, NCOS, PZERO,
NZERO, VREF, NERR, SCL, SDA,
MA, SLI, SLO, A, B, Z
-10
10
mA
G009 Ilu()
Pulse Current in all pins
(Latch-up Strength)
according to Jedec Standard No. 78;
Ta = 25 °C, pulse duration to 10 ms,
VDDA = VDDAmax , VDD = VDDmax ,
Vlu() = (-0.5...+1.5) x Vpin()max
-100
100
mA
G010 Vd()
ESD Susceptibility at all pins
HBM 100 pF discharged through 1.5 kΩ
2
kV
G011 Tj
Junction Temperature
-40
150
°C
G012 Ts
Storage Temperature Range
-40
150
°C
THERMAL DATA
Operating Conditions: VDDA = VDD = 5 V ±10 %
Item
No.
T01
Symbol
Parameter
Conditions
Unit
Min.
Ta
Operating Ambient Temperature Range
(extended temperature range of
-40 to 125 °C available on request)
All voltages are referenced to ground unless otherwise stated.
All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative.
-25
Typ.
Max.
85
°C
preliminary
iC-NQC
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev B1, Page 6/29
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDDA = VDD = 5 V ±10 %, Tj = -40 ... 125 °C, unless otherwise stated.
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Typ.
Max.
Total Device
Functionality and parameters beyond the operating conditions (with reference to independent voltage supplies, for instance)
are to be verified within the individual application using FMEA methods.
001
VDDA,
VDD
Permissible Supply Voltage
4.5
5.5
V
002
I(VDDA)
Supply Current in VDDA
003
I(VDD)
Supply Current in VDD
fin() = 200 kHz; A, B, Z open
15
mA
fin() = 200 kHz; A, B, Z open
20
004
Von
Turn-on Threshold VDDA, VDD
3.2
mA
005
006
Vhys
Turn-on Threshold Hysteresis
200
Vc()hi
Clamp Voltage hi at
PSIN, NSIN, PCOS, NCOS,
PZERO, NZERO, VREF
007
Vc()lo
008
Vc()hi
Vc()hi = V() - VDDA;
I() = 1 mA, other pins open
4.4
V
mV
0.3
1.6
V
Clamp Voltage lo at
I() = -1 mA, other pins open
PSIN, NSIN, PCOS, NCOS,
PZERO, NZERO, VREF, NERR,
SCL, SDA, MA, SLI, SLO, A, B, Z
-1.6
-0.3
V
Clamp Voltage hi at
NERR, SCL, SDA, MA,
SLI, SLO, A, B, Z
0.3
1.6
V
-10
-15
10
15
mV
mV
Vc()hi = V() - VDD;
I() = 1 mA, other pins open
Input Amplifiers and Signal Inputs PSIN, NSIN, PCOS, NCOS
101 Vos()
Input Offset Voltage
Vin() and G() in accordance with table GAIN;
G ≥ 20
G < 20
102
TCos
Input Offset Voltage
Temperature Drift
see 101
±10
µV/K
103
Iin()
Input Current
V() = 0 V ... VDDA
-50
50
nA
104
GA
Gain Accuracy
G() in accordance with table GAIN
95
102
%
105
106
GArel
Gain SIN/COS Ratio Accuracy
G() in accordance with table GAIN
97
103
fhc
Cut-off Frequency
G = 80
G = 2.667
230
650
kHz
kHz
107
SR
Slew Rate
G = 80
G = 2.667
4
9
V/µs
V/µs
%
Sine-To-Digital Conversion
201
AAabs
Absolute Angle Accuracy without referred to 360° input signal, G = 2.667,
calibration
Vin = 1.5 Vpp, HYS = 0
-1.0
1.0
DEG
202
AAabs
Absolute Angle Accuracy after
calibration
referred to 360° input signal, HYS = 0, internal
signal amplitude of 2 ... 4 Vpp
-0.5
+0.5
DEG
203
AArel
Relative Angle Accuracy
referred to signal periods at A, resp. B
(see Fig. 1);
G = 2.667, Vin = 1.5 Vpp, SELRES = 1024,
FCTR = 0x0004 ... 0x00FF, fin < finmax
(see table 16)
-10
10
%
Reference Voltage
I(VREF) = -1 mA ... +1 mA
48
52
%
VDDA
Permissible Max. Oscillator
Frequency
presented at pin SCL with subdivision
of 2048;
90
MHz
Oscillator Frequency
presented at pin SCL with subdivision
of 2048;
VDDA = VDD = 5 V ±10 %, CFGOSC = 0x00
VDDA = VDD = 5 V, CFGOSC = 0x00
VDDA = VDD = 5 V, CFGOSC = 0x03
VDDA = VDD = 5 V, CFGOSC = 0x05
90
83
MHz
MHz
MHz
MHz
±0.35
Reference Voltage Output VREF
801
VREF
Oscillator
A01 fosc()max
A02
A03
fosc()
TCosc
Oscillator Frequency Temperature Drift
VDDA = VDD = 5 V
52
60
72
54
84
-0.1
%/K
preliminary
iC-NQC
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev B1, Page 7/29
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDDA = VDD = 5 V ±10 %, Tj = -40 ... 125 °C, unless otherwise stated.
Item
No.
A04
Symbol
Parameter
Conditions
Unit
Min.
VCosc
Oscillator Frequency Power Sup- CFGOSC = 0x00
ply Dependance
Typ.
Max.
+9
%/V
Zero Signal Enable Inputs PZERO, NZERO
B01
Vos()
Input Offset Voltage
V() = Vcm()
-20
20
mV
B02
Iin()
Input Current
V() = 0 V ... VDDA
-50
50
nA
B03
Vcm()
Common-Mode Input Voltage
Range
1.4
VDDA1.5
V
B04
Vdm()
Differential Input Voltage Range
0
VDDA
V
V
Incremental Outputs A, B, Z and I/O Interface Output SLO
D01 Vs()hi
Saturation Voltage hi
Vs()hi = VDD - V(); I() = -4 mA
0.4
D02 Vs()lo
Saturation Voltage lo
I() = 4 mA
0.4
V
D03 tr()
Rise Time
CL() = 50 pF
60
ns
D04 tf()
Fall Time
CL() = 50 pF
D05 RL()
Permissible Load at A, B
TMA = 1 (calibration mode)
60
1
ns
MΩ
I/O Interface Inputs MA, SLI
E01
Vt()hi
Threshold Voltage hi
E02
Vt()lo
Threshold Voltage lo
2
E03
Vt()hys
Hysteresis
E04
Ipu(MA)
E05
E06
Ipd(SLI)
fclk(MA)
Permissible MA Clock Frequency SSI protocol
BiSS protocol
E07
tp(MASLO)
Propagation Delay:
MA edge vs. SLO output
E08
tbusy_s
Processing Time Single-Cycle
Data (delay of start bit)
E09
tbusy_r
Processing Time Register Access (delay of start bit)
with read access to EEPROM
E10
tidle
Interface Blocking Time
powering up with no EEPROM
1
E11
t_tos
Timeout
CFGOSC = 0x00, TIMO = 0, TOA =0
20
V
0.8
V
Vt()hys = Vt()hi - Vt()lo
300
mV
Pull-up Current in MA
V() = 0 ... VDD - 1 V
-240
-120
-25
µA
Pull-down Current in SLI
V() = 1 ... VDD
20
120
300
µA
4
10
MHz
MHz
50
ns
RL(SLO) ≥ 1 kΩ
10
0
µs
2
ms
1.5
ms
µs
EEPROM Interface Inputs SDA and Error Input NERR
F01
Vt()hi
Threshold Voltage hi
F02
Vt()lo
Threshold Voltage lo
2
F03
Vt()hys
Hysteresis
F04
tbusy()cfg
Duration of Startup Configuration error free EEPROM access
F05
Vt()hi
Threshold Voltage hi
Vt()hys = Vt()hi - Vt()lo
V
0.8
V
300
mV
5
7
ms
2
V
100
kHz
EEPROM Interface Outputs SDA, SCL and Error Output NERR
G01 f()
Write/Read Clock at SCL
G02 Vs()lo
Saturation Voltage lo
I() = 4 mA
G03 Ipu()
Pull-up Current
V() = 0 ... VDD - 1 V
G04 ft()
Fall Time
CL() = 50 pF
G05 tmin()lo
Min. Duration Of Error Indication MA = hi, no BiSS access, amplitude or frequeny
at NERR (lo signal)
error
G06 Tpwm()
Cycle Duration Of Error Indication at NERR
G07 t()lo
Duty Cycle Of Error Indication at signal duration low to high;
AERR = 0 (amplitude error)
NERR
FERR = 0 (frequency error)
G08 RL()
Permissible Load at SDA, SCL
20
-600
V
-75
µA
60
10
fosc() subdivided 222
TMA = 1 (calibration mode)
-300
0.45
1
ns
ms
60.7
ms
75
50
%
%
MΩ
preliminary
iC-NQC
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev B1, Page 8/29
CHARACTERISTICS: Diagrams
tAB
tMTD
B
A
twhi
AArel
AArel
T
Figure 1: Definition of relative angle error and minimum transition distance
0.15°
0.1°
0.05°
0
-0.05°
-0.1°
-0.15°
0°
90°
180°
270°
Figure 2: Typical residual absolute angle error after calibration.
360°
preliminary
iC-NQC
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev B1, Page 9/29
OPERATING REQUIREMENTS: I/O Interface
Operating Conditions: VDD = 5 V ±10 %, Ta = -25 ... 85 °C; input levels lo = 0 ... 0.45 V, hi = 2.4 V ... VDD
Item
No.
Symbol
Parameter
Conditions
Fig.
Unit
Min.
Max.
SSI Protocol
I001 TMAS
Permissible Clock Period
4
250
2x ttos
ns
I002 tMASh
Clock Signal Hi Level Duration
ttos according to Table 45
4
25
ttos
ns
I003 tMASl
Clock Signal Lo Level Duration
4
25
ttos
ns
BiSS C Protocol
I004 TMAS
Permissible Clock Period
5
100
2x ttos
ns
I005 tMASh
Clock Signal Hi Level Duration
ttos according to Table 35
5
25
ttos
ns
I006 tMASl
Clock Signal Lo Level Duration
5
25
ttos
ns
Figure 3: Timing diagram in SSI protocol.
Figure 4: Timing diagram in BiSS C protocol.
preliminary
iC-NQC
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev B1, Page 10/29
PARAMETER and REGISTER
Signal Monitoring
and Error Messages . . . . . . . . . . . . . . . . . . . . . . . Page 17
SELAMPL: Amplitude Monitoring, function
AMPL:
Amplitude Monitoring, thresholds
AERR:
Amplitude Error
FERR:
Frequency Error
Register Description, Overview . . . . . . . . . . . Page 10
Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . Page 11
GAIN:
Gain Select
SINOFFS:
Offset Calibration Sine
COSOFFS: Offset Calibration Cosine
REFOFFS: Offset Calibration Reference
RATIO:
Amplitude Calibration
PHASE:
Phase Calibration
Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 18
TMODE:
Test Mode
TMA:
Analog Test Mode
Converter Function . . . . . . . . . . . . . . . . . . . . . . . . Page 12
SELRES:
Resolution
HYS:
Hysteresis
CFGOSC:
Oscillator Calibration
FCTR:
Max. Permissible Converter Frequency
BiSS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 19
SELSSI:
Protocol Version
TIMO, TOA: Timeout
TOS:
Timeout Short
M2S:
Data Output and Options
CRC6:
CRC Polynomial
NZB:
Zero Bit
ENCDS:
Protocol Options
RPL:
Register Protection Settings
GRAY:
SSI Data Format
Incremental Signals . . . . . . . . . . . . . . . . . . . . . . . Page 15
CFGABZ:
Output A, B, Z
ROT:
Direction of Rotation
CBZ:
24-bit Period Counter Configuration
ENRESDEL: Output Delay A, B, Z
ZPOS:
Zero Signal Position
CFGZ:
Zero Signal Length
CFGAB:
Zero Signal Logic
OVERVIEW
Adr
Bit 7
0x00
ENCDS
0x01
Bit 6
Bit 5
Bit 4
M2S(1:0)
ENRESDEL
SELSSI
0x03
CRC6
NZB
Bit 1
Bit 0
ZPOS(4:0)
ROT
CBZ
CFGABZ(1:0)
CFGAB(1:0)
0x04
RPL
CFGZ(1:0)
0
AERR
FERR
FCTR(7:0)
GRAY
FCTR(14:8)
0x06
TIMO
TMODE(2:0)
0x07
TOA
0x08
TMA
CFGOSC(2:0)
GAIN(3:0)
RATIO(3:0)
0x09
SINOFFS(7:0)
0x0A
COSOFFS(7:0)
0x0B
0x0C
Bit 2
SELRES(4:0)
HYS(2:0)
0x02
0x05
Bit 3
PHASE(5:0)
reserved
reserved
reserved
reserved
REFOFFS
reserved
SELAMPL
RATIO(4)
AMPL(1:0)
0x0D
0x0E
0x0F
CRC_E2P(7:0) - check value read from the EEPROM for addresses 0x00 to 0x0E
EEPROM
0x10 0x1F
0x00 - 0x0F
Reserved EEPROM memory section: iC-NQC device configuration data.
0x41 0x7F
0x31 - 0x6F
Reserved EEPROM memory section: BiSS C Slave Registers (device identifier 4E 51 43 33 00 00 69 43)
When no register protection is active, all registers permit read and write access (see RPL).
Register contents are random when powering up without an EERPOM.
Table 5: Register layout
preliminary
iC-NQC
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev B1, Page 11/29
SIGNAL CONDITIONING
Input stages SIN and COS are configured as instrumentation amplifiers. The amplifier gain must be selected in accordance with the input signal amplitude
and programmed to register GAIN according to the folGAIN
lowing table. Half of the supply voltage is available at
VREF as a center voltage to enable the DC level to be
adapted.
Adr 0x08, Bit 7:4
Code
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Amplification
80.000
66.667
53.333
40.000
33.333
28.571
26.667
20.000
14.287
10.000
8.000
6.667
5.333
4.000
3.333
2.667
Differential
up to 50 mVpp
up to 60 mVpp
up to 75 mVpp
up to 0.1 Vpp
up to 0.12 Vpp
up to 0.14 Vpp
up to 0.15 Vpp
up to 0.2 Vpp
up to 0.28 Vpp
up to 0.4 Vpp
up to 0.5 Vpp
up to 0.6 Vpp
up to 0.75 Vpp
up to 1 Vpp
up to 1.2 Vpp
up to 1.5 Vpp
Sine/Cosine Input Signal Levels Vin()
Amplitude
Average value (DC)
Single-ended
Differential
Single-ended
up to 100 mVpp
0.7 V ... VDDA - 1.2 V
0.8 V ... VDDA - 1.2 V
up to 120 mVpp
0.7 V ... VDDA - 1.2 V
0.8 V ... VDDA - 1.2 V
up to 0.15 Vpp
0.7 V ... VDDA - 1.2 V
0.8 V ... VDDA - 1.2 V
up to 0.2 Vpp
1.2 V ... VDDA - 1.2 V
1.3 V ... VDDA - 1.3 V
up to 0.24 Vpp
1.2 V ... VDDA - 1.2 V
1.3 V ... VDDA - 1.3 V
up to 0.28 Vpp
0.7 V ... VDDA - 1.2 V
0.8 V ... VDDA - 1.3 V
up to 0.3 Vpp
1.2 V ... VDDA - 1.2 V
1.3 V ... VDDA - 1.3 V
up to 0.4 Vpp
0.7 V ... VDDA - 1.2 V
0.8 V ... VDDA - 1.3 V
up to 0.56 Vpp
1.2 V ... VDDA - 1.3 V
1.4 V ... VDDA - 1.4 V
up to 0.8 Vpp
1.2 V ... VDDA - 1.3 V
1.4 V ... VDDA - 1.5 V
up to 1 Vpp
0.8 V ... VDDA - 1.4 V
1.0 V ... VDDA - 1.6 V
up to 1.2 Vpp
0.8 V ... VDDA - 1.4 V
1.1 V ... VDDA - 1.7 V
up to 1.5 Vpp
0.9 V ... VDDA - 1.5 V
1.3 V ... VDDA - 1.9 V
up to 2 Vpp
1.2 V ... VDDA - 1.6 V
1.7 V ... VDDA - 2.1 V
up to 2.4 Vpp
1.2 V ... VDDA - 1.7 V
1.8 V ... VDDA - 2.3 V
up to 3 Vpp
1.3 V ... VDDA - 1.8 V
2.0 V ... VDDA - 2.6 V
Table 6: Input gain
SINOFFS
COSOFFS
Code
Adr 0x09, Bit 7:0
Adr 0x0A, Bit 7:0
Output Offset
RATIO
Code
Adr 0x0B, Bit 0, Adr 0x08, Bit 3:0
COS / SIN
Code
COS / SIN
0x00
0x01
...
0x7F
0x80
0x81
0V
-7.8125 mV
...
-0.9922 V
0V
+7,8125 mV
Input Offset
0x00
1.0000
0x10
1.0000
0V
-7.8125* mV / GAIN
...
-0.9922 V / GAIN
0V
+7.8125 mV / GAIN
0x01
...
0x0F
1.0067
...
1.1
0x11
...
0x1F
0.9933
...
0.9000
...
0xFF
...
+0.9922 V
...
+0.9922 V / GAIN
PHASE
Code
Adr 0x0B, Bit 7:2
Phase Shift
Notes
*) With REFOFFS = 0x00 and VDDA = 5 V.
Code
Phase Shift
90°
90.703125°
...
102.65625°
102.65625°
0x20
0x21
...
0x32
...
90°
89.296875°
...
77.34375°
77.34375°
102.65625°
0x3F
77.34375°
Table 9: Amplitude calibration
REFOFFS
Adr 0x0B, Bit 1
0x00
0x01
...
0x12
...
Code
Reference Voltage
0x1F
0x00
Dependent on VDDA
(example of application: MR sensors)
Not dependent on VDDA
(example of application: Sin/Cos encoders)
Table 7: Sine/cosine offset calibration
0x01
Table 8: Offset reference
Table 10: Phase calibration
preliminary
iC-NQC
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev B1, Page 12/29
CONVERTER FUNCTIONS
SELRES
Code
Adr 0x00, Bit 4:0
Binary
Examples of Permissible
Resolutions
Input Frequencies finmax
(FCTR 0x0004, 0x4302)
SELRES
Code
Adr 0x00, Bit 4:0
Decimal
Examples of Permissible
Resolutions
Input Frequencies finmax
(FCTR 0x0004, 0x4302)
0x00
0x01
0x02
0x03
0x04
0x05
8192
4096
2048
158 Hz, 1.06 kHz
317 Hz, 2.12 kHz
634 Hz, 4.24 kHz
0x10
0x11
0x12
0x13
0x14
0x15
2000
1600
1000
800
500
400
650 Hz, 4.3 kHz
812 Hz, 5.5 kHz
1.3 kHz, 8.6 kHz
1.6 kHz, 10.8 kHz
2.6 kHz, 17 kHz
3.2 kHz, 22 kHz
0x06
0x07
0x08
0x09
0x0A
0x0B
1024
512
256
128
64
32
1.27 kHz, 8.5 kHz
2.54 kHz, 17 kHz
5.1 kHz, 34 kHz
10.2 kHz, 68 kHz
20.3 kHz, 136 kHz
40.6 kHz (max. 250 kHz)
0x16
0x17
0x18
0x19
0x1A
0x1B
250 *1
125 *1,2
320
160 *2
80 *4
40 *8
5.2 kHz, 35 kHz
5.2 kHz, 35 kHz
4.1 kHz, 27 kHz
4.1 kHz, 27 kHz
4.1 kHz, 27 kHz
4.1 kHz, 27 kHz
0x0C
0x0D
0x0E
0x0F
16
8
-
81.3 kHz (max. 250 kHz)
162 kHz (max. 250 kHz)
0x1C
0x1D
0x1E
0x1F
200
100 *2
50 *1,4
25 *1,8
6.5 kHz, 43.3 kHz
6.5 kHz, 43.3 kHz
6.5 kHz, 43.3 kHz
6.5 kHz, 43.3 kHz
Notes
*1
Table 11: Binary resolutions
Not suitable for incremental output on A, B.
The internal resolution is higher by
a factor of 2, 4 or 8.
*2,4,8
Table 12: Decimal resolutions
HYS
Code
Adr 0x01, Bit 7:5
Hysteresis in
Hysteresis in
degrees
LSB
0x00
0°
0x01
0.0879°
0x02
0.1758°
0x03
0.3516°
0x04
0.7031°
0x05
0x06
1.4063°
5.625°
0x07
45°
Notes
*) The resulting absolute error is equivalent to half
the angle hysteresis.
Absolute error*
1 LSB @
12 bit
1/2 LSB @
10 bit
1 LSB @
10 bit
0.044°
1/2 LSB @
8 bit
1 LSB @ 8 bit
0.352°
only
recommended
for calibration
22.5°
Table 13: Hysteresis
0.088°
0.176°
0.703°
2.813°
CFGOSC
Code
Adr 0x07, Bit 2:0
Trimming Frequency
0x00
0x01
0x02
0x03
No change
-10 %
-14.4 %
-22 %
0x04
0x05
0x06
0x07
Not permissible
+12.5 %
+6.25 %
-4.5 %
Table 14: Oscillator calibration
preliminary
iC-NQC
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev B1, Page 13/29
MAXIMUM POSSIBLE CONVERTER FREQUENCY
The converter frequency automatically adjusts to the
value required by the input frequency and resolution.
This value ranges from zero to a maximum dependent on the oscillator frequency that is set via register
FCTR.
Serial data output
For BiSS or SSI output the maximum possible converter frequency can be adjusted to suit the maximum input frequency; an automatic converter resolution step-down feature can be enabled via the FCTR
register. Should the input frequency exceed the frequency limit of the selected converter resolution, the
LSB is kept stable and not resolved any further; the
interpolation resolution halves.
If the next frequency limit is overshot, the LSB and LSB
+1 are kept stable and so on. If the input frequency
again sinks below this frequency threshold, fine resolution automatically returns.
With the programming of CRC6 = 1 a resolution stepdown will be signalled via the BiSS warning bit.
Max. Possible Converter Frequency For Serial Data Output
Resolution
Protocol
Max. Input Frequency
Restrictions
Requirements
at high input frequency
FCTR
Min. Res. bin dec BiSS SSI finmax
0x0004
X
X
X
X
f(OSC)min / 40 / Resolution –
0x4102
≥8
X
X
X
X
f(OSC)min / 24 / Resolution Rel. angle error 2x increased
0x4202
≥ 16
X
X
X
X
2 x f(OSC)min / 24 / Res.
Rel. angle error 4x increased
0x4302
≥ 32
X
X
X
X
4 x f(OSC)min / 24 / Res.
Rel. angle error 8x increased
0x4702
≥ 64
X
X
X
8 x f(OSC)min / 24 / Res.
Resolution lowered by factor of 2
0x4B02 ≥ 128
X
X
X
16 x f(OSC)min / 24 / Res.
Res. lowered by factor of 2-4
0x4F02 ≥ 256
X
X
X
32 x f(OSC)min / 24 / Res.
Res. lowered by factor of 2-8
0x5302
≥ 512
X
X
X
64 x f(OSC)min / 24 / Res.
Res. lowered by factor of 2-16
0x5702
≥ 1024
X
X
X
128 x f(OSC)min / 24 / Res. Res. lowered by factor of 2-32
0x5B02 ≥ 2048
X
X
X
256 x f(OSC)min / 24 / Res. Res. lowered by factor of 2-64
0x5F02 ≥ 4096
X
X
X
512 x f(OSC)min / 24 / Res. Res. lowered by factor of 2-128
0x6302
8192
X
X
X
1024 x f(OSC)min / 24 / Res. Res. lowered by factor of 2-256
Notes
*) Calculated with fosc()min taken from Electrical Characteristics, item A01.
Table 15: Maximum converter frequency for serial data output.
Examples*
finmax [kHz] at resol.
8192 1024 200
0.16
1.27
6.5
0.26
2.1
10.8
0.53
4.2
21.6
1.06
8.5
43.3
2.1
16.9
4.2
33.8
8.5
67.7
16.9
135
33.8
250
67.7
135
250
-
iC-NQC
preliminary
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev B1, Page 14/29
Incremental output to A, B and Z
Settings for the maximum possible converter frequency using register FCTR are governed by two criteria:
also make a suitable zero-delay digital glitch filter that
acts on ESD impact on the sensor and keeps the output signals spike free through temporal separation, for
example.
1. The maximum input frequency
2. System restrictions caused by slow counters or data
transmission via cable
Serial data output is possible at any time in BiSS or
SSI protocol. However, for the transfer of angle data to
the output register the incremental output is halted for
one period of the clock signal at pin MA.
In this case it is sensible to preselect a minimum transition distance for the output signals. These settings
1. Max. Possible Converter Frequency Defined By The Maximum Input Frequency
Output Frequency Resolution Maximum Input Frequency
Restrictions
fout @ finmax
Requirem.
at high input frequency
FCTR
A, B
bin dec finmax
0x0004
325 kHz
X
X
f(OCS)min / 40 / Resolution
None
0x4102
542 kHz
X
X
f(OSC)min / 24 / Resolution
Relative angle error 2x increased
0x4202
1.08 MHz
X
X
2 x f(OSC)min / 24 / Res.
Relative angle error 4x increased
0x4302
2.17 MHz
X
X
4 x f(OSC)min / 24 / Res.
Relative angle error 8x increased
Notes
*) Calculated with fosc()min taken from Electrical Characteristics, item A01.
Examples*
finmax [kHz] at resol.
8192 1024 200
0.16
1.27
6.5
0.26
2.1
10.8
0.53
4.2
21.6
1.06
8.5
43.3
Table 16: Maximum possible converter frequency for incremental A/B/Z output,
defined by the maximum input frequency
2. Max. Possible Converter Frequency Defined By The Minimum Transition Distance
Output Frequency Resolution Minimum Transition Distance Restrictions
Example*
fout @ tMTD
Requirem. at A, B
at high input frequency
tMTD [µsec]
FCTR
A, B
bin dec tMTD
0x00FF 11 kHz
X
X
2048 / f(OSC)max
None
22.8
0x00FE 11.03 kHz
X
X
2040 / f(OSC)max
None
22.7
0x00FD 11.07 kHz
X
X
2032 / f(OSC)max
None
22.6
...
...
...
...
...
...
...
0x0006
402 kHz
X
X
56 / f(OSC)max
None
0.62
0x0005
536 kHz
X
X
48 / f(OSC)max
None
0.53
0x0004
562 kHz
X
X
40 / f(OSC)max
None
0.44
0x4102
938 kHz
X
X
24 / f(OSC)max
Relative angle error 2x increased
0.27
0x4202
1.87 MHz
X
X
12 / f(OSC)max
Relative angle error 4x increased
0.13
0x4302
3.75 MHz
X
X
6 / f(OSC)max
Relative angle error 8x increased
0.07
Notes
*) Calculated with fosc()max taken from El.Char., item A01; transition distance output A vs. output B with same direction
of rotation.
Table 17: Maximum possible converter frequency for incremental A/B/Z output,
defined by the minimum transition distance
preliminary
iC-NQC
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev B1, Page 15/29
INCREMENTAL SIGNALS
CFGABZ
Code
Adr 0x02, Bit 3:2
Mode
A
B
Z
0x00
Normal
A
B
Z
0x01
Control signals for
external period counters
CA
CB
CZ
0x02
Calibration mode
Offset+Phase
The following settings
are required additionally:
SELRES = 0x0D
ZPOS = 0x00
HYS = 0x07
ROT = 0x00
CFGAB = 0x00
AERR = 0x00
0x03
Calibration mode
Offset+Amplitude
The following settings
are required additionally:
SELRES = 0x0D
ZPOS = 0x00
HYS = 0x07
ROT = 0x00
CFGAB = 0x00
AERR = 0x00
Notes
Figure 5: Offset SIN*
Figure 6: Offs. COS*
Figure 7: Phase*
Figure 8: Offset SIN*
Figure 9: Offs. COS*
Figure 10: Amplit.*
*) Trimmed accurately when duty cycle is 50 %;
Recommended trimming order (after selecting GAIN): offset, phase, amplitude ratio, offset;
Table 18: Outputs A, B, Z
ROT
Code
Adr 0x02, Bit 5
Code direction
0x00
0x01
Ascending order, B then A
Descending order, A then B
SIN
Table 19: Code direction
COS
cw: F->0
CBZ
Code
Adr 0x02, Bit 4
Reset via zero
0x00
0x01
Not activated
Activated
FFFFFF
ccw: 0->F
A
B
Z
Table 20: Reset enable for period counter
Code
Adr 0x02, Bit 7
Output*
Function
0x00
immediately
An external counter displays the
absolute angle following power-on.
0x01
after 5 ms
An external counter only displays
changes vs. the initial power-on
(conditional on standby at
power-on)
Notes
*) Output delay after device configuration and
internal reset.
ENRESDEL
P(23:0)
000000
Table 21: Output delay A, B, Z
-180°
-90°
0°
45°
90°
180°
Figure 11: Period counter reset by zero signal (enabled by CBZ = 1).
Example gives a resolution of 64
(SELRES = 0x0A), a zero signal at 45°
(ZPOS = 0x04, CFGAB = 0x00) and no
inversion of the direction of rotation
(ROT = 0x00, COS leads SIN).
preliminary
iC-NQC
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev B1, Page 16/29
ZPOS
Code
Adr 0x01, Bit 4:0
Position
CFGZ
Code
Adr 0x02, Bit 1:0
Length
0x00
0x08
0x10
0x18
0°
90°
180°
270°
0x00
0x01
0x02.. 03
90°
180°
Synchronization
0x01
...
0x1F
11.25° (1 x 11.25°)
...
348.75° (31 x 11.25°)
CFGAB
Adr 0x03, Bit 5:4
Notes
The zero signal is only output if released by the
input pins (for instance with PZERO = 5 V, NZERO =
VREF).
Code
Z = 1 for
0x00
0x01
B = 1, A = 1
B = 0, A = 1
Table 22: Zero signal position
0x02
0x03
B = 1, A = 0
B = 0, A = 0
Table 23: Zero signal length
Table 24: Zero signal logic
SIN
COS
A
B
Z (CFGZ= 0)
Z (CFGZ= 1)
Z (CFGZ= 2)
-180°
-90°
0°
45°
90°
180° Winkel
Figure 12: Incremental output signals for various zero signal lengths.
Example gives a resolution of 64 (SELRES = 0x0A), a zero signal position of 45° (ZPOS = 0x04,
CFGAB = 0x00) and no inversion of the direction of rotation (ROT = 0x00, COS leads SIN).
preliminary
iC-NQC
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev B1, Page 17/29
SIGNAL MONITORING and ERROR MESSAGES
Vss
SELAMPL
AMPL
Adr 0x0C, Bit 2
Adr 0x0C, Bit 1:0
Max ( |Sin| , |Cos| )
Code
Voltage threshold Vth
Output amplitude*
0x00
0x01
0.60 x VDDA
0.64 x VDDA
1.4 Vpp
2.0 Vpp
0x02
0x03
0.68 x VDDA
0.72 x VDDA
2.6 Vpp
3.1 Vpp
Vth
Figure 13: Signal monitoring at minimum amplitude.
Sin2 + Cos2
Code
Vthmin ↔ Vthmax
Output amplitude*
0x04
0x05
0.20 ↔ 0.9 x VDDA
0.30 ↔ 0.9 x VDDA
1.0 Vpp ↔ 4.5 Vpp
1.5 Vpp ↔ 4.5 Vpp
0x06
0x07
0.40 ↔ 0.9 x VDDA
0.50 ↔ 0.9 x VDDA
2.0 Vpp ↔ 4.5 Vpp
2.5 Vpp ↔ 4.5 Vpp
Notes
*) Entries are calculated with VDDA = 5 V.
Table 25: Signal amplitude monitoring
AERR
Code
Adr 0x03, Bit 1
Amplitude error message
0x00
disabled
0x01
enabled
Vthmax
Vthmin
Figure 14: Sin2 + Cos2 signal monitoring.
Error Messages
Failure Mode
Error bits E1, E0
for BiSS and SSI
CRC6 = 0
Error bits nE, nW
for BiSS and SSI
CRC6 = 1
No error
Amplitude error
Frequency error
System error*
1, 1
0, 1
1, 0
0, 0
1, nW
0, nW
0, nW
0, nW
Warning**
—
nE, 0
Notes
*System error
NERR pulled low by external signal
Table 26: Amplitude error
FERR
Code
Adr 0x03, Bit 0
Excessive frequency error message
0x00
0x01
disabled
enabled
Notes
Input frequency monitoring is operational for
resolutions ≥ 16
Table 27: Frequency error
Configuration error
Always enabled
Table 28: Configuration error
Error Indication at NERR
Failure Mode
Pin signal NERR
No error
Amplitude error
HI
LO/HI = 75 % (resp. HI for AERR = 0)
Frequency error
Configuration
Undervoltage
System error
LO/HI = 50 % (resp. HI for FERR = 0)
LO
LO
NERR = low caused by an external error
signal
Table 29: Error indication at NERR
**Warning
Line Signal SLO
Automatic step-back of resolution
Data output is deactivated and SLO
permanently high in case of: configuration
phase, invalid configuration, undervoltage.
Table 30: Error messages
To enable the diagnosis of faults, the various types
of error are signaled at NERR using a PWM code as
given in the key on the left.
Two error bits are provided to enable communication
via the I/O interface; these bits can decode four different types of error. If NERR is held at low by an external
source, such as an error message from the system, for
example, this can also be verified via the I/O interface.
Error are stored until the sensor data is output via the
I/O interface and then deleted. Errors at NERR are
displayed for a minimum of ca. 10 ms unless they are
deleted beforehand by a data output.
preliminary
iC-NQC
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev B1, Page 18/29
If an error in amplitude occurs, conversion is terminated and the incremental output signals halted. An
error in amplitude rules out the possibility of an error in
frequency.
TEST FUNCTIONS
TMODE
Code
Adr 0x06, Bit 3:1
Signal at Z
Description
0x00
0x01
0x02
Z
A xor B
ENCLK
no test mode
Output A EXOR B
iC-Haus device test
0x03
0x04
0x05
0x06
0x07
NLOCK
CLK
DIVC
PZERO - NZERO
TP
iC-Haus device test
iC-Haus device test
iC-Haus device test
iC-Haus device test
iC-Haus device test
Condition
CFGABZ = 0x00
TMA
Code
Adr 0x06, Bit 0
Pin A
Pin B
Pin SDA
Pin SCL
0x00
0x01
A
COS+
SDA
SIN+
SCL
SIN-
Notes
To permit the verification of GAIN and OFFSET
settings, signals are output after the input amplifier.
A converter signal of 4 Vpp is the ideal here and
should not be exceeded. Loads of 1 MΩ and above
are recommended for accurate measurement.
EEPROM access is not possible during mode TMA.
B
COS-
Table 32: Analog test mode
Table 31: Test mode
5V
A: COS+
SDA: Sin+
0V
Y/T 1 V/Div vert.
X/Y 1 V/Div vert. 1 V/Div hor.
Figure 15: Calibrated signals in TMA mode.
The signal is set to ca. 4 Vpp using GAIN and must not
be altered after calibration. Both display modes are
suitable for OFFS (positive values) and RATIO adjustments; X/Y mode is preferable for PHASE. Test signals
COS- (pin B) and SIN- (pin SCL) must be selected to
set negative values for OFFS.
preliminary
iC-NQC
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev B1, Page 19/29
I/O INTERFACE: BiSS C PROTOCOL
The serial I/O interface operates in BiSS C protocol
mode and enables sensor data to be output in uninterruptible cycles (data channel SCD). At the same time
parameters can be exchanged via bidirectional register
communication (data channel CD).
The sensor data produced by iC-NQC contains the angle value (S) with 3 to 13 bits, the period count (P) with
0, 8, 12 or 24 bits, two error bits (E1 and E0) and 5 or
6 CRC bits (CRC).
Interface Parameters With BiSS C Protocol
SELSSI
Code
Adr 0x02, Bit 6
Protocol
0
1
BiSS C
SSI
Information
www.biss-interface.com
Table 34: Protocol version
Figure 16: Example line signals (BiSS C)
Single Cycle Data Channel: SCD
Bits
Typ
Label
0...24
DATA
Period counter P(23:0):
0, 8, 12, 24 bit (multiturn position)
3...13
DATA
Angle data S(12:0):
3 bis 13 bit (singleturn position)
1
ERROR
Error bit E1 (amplitude error)
1
ERROR
Error bit E0 (frequency error)
5...6
CRC
Polynomial 0x25
x5 + x2 + x0 (inverted bit output)
- oder Polynomial 0x43
x6 + x1 + x0 (inverted bit output)
TIMO
Code
Adr 0x06, Bit 5
Clock
Timeout ttos
0
1
TOA
0
1
46-47
5-6
Addr 0x07, Bit 3
see TIMO
adaptive with
TCLK =
42/fosc
Notes
32
A ref. clock count is equal to fosc
(see El. Char.,
A02).
The permissible max. clock frequency is specified
by E06.
*) A low clock frequency can reduce the permissible
maximum input frequency since conversion is
paused for one MA cycle from Latch onwards.
fclk(MA) min*
ca. 20 µs
ca. 2.5 µs
50 kHz
400 kHz
see BiSS
specification
50 kHz
Table 35: Timeout configuration (protectable)
Table 33: BiSS data channels
M2S
Code
Adr 0x00, Bit 6:5
Data Length
CRC Polynomial
0x00
0x01
0x02
0x03
P(7:0)
P(11:0)
P(23:0)
0x25 (with CRC6 = 0)
0x25 (with CRC6 = 0)
0x43
0x43
Table 36: Period counter output
CRC6
Code
Adr 0x03, Bit 7
CRC Polynomial
Status Messages
0
determined by M2S
E1, E0
1
0x43
nE, nW
Table 37: CRC polynomial
preliminary
iC-NQC
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev B1, Page 20/29
NZB
Code
Adr 0x03, Bit 6
Function
SCD: Angle data with 8-bit period count
Bits
Type
Label
0
1
Zero bit
No zero bit
Notes
The optional zero bit is output as the final bit after
the CRC.
8
13
2
5
DATA
DATA
ERROR
CRC
Period counter P(7:0)
Angle data S(12:0)
Error bits E1, E0
Polynomial 0x25
1
Zero
Zero bit
Config.
SELRES = 0x03, M2S = 0x01, CRC6 = 0, NZB = 0
Table 38: Zero bit
Table 41: Example format 2
ENCDS
Code
Adr 0x00, Bit 7
Description
0x00
0x01
Data output BiSS B or SSI
Data output BiSS C
Table 39: Protocol options
SCD: Angle data with 24-bit period count
Bits
Type
Label
24
13
2
6
DATA
DATA
ERROR
CRC
Period counter P(23:0)
Angle data S(12:0)
Error bits E1, E0
Polynomial 0x43 (no zero bit)
Config.
SELRES = 0x03, M2S = 0x03, CRC6 = 0, NZB = 1
M2S can be used to set the number of period counter
bits sent as sensor data. The counter bits are transmitted before the angle value, with the MSB leading.
Table 42: Example format 3
The 5-bit CRC output is based on polynomial 0x25
(100101b), with the 6-bit CRC output based on polynomial 0x43 (1000011b) automatically coming active
with longer SCD data, or when preselected by CRC6.
As a rule, CRC bits are sent inverted.
Register Communication
After the BiSS C protocol slave registers are directly
addressed in a reserved address area (0x40 to 0x7F).
Other storage areas are addressed dynamically and in
blocks. BiSS addresses 0x00 to 0x3F aim for a register bank consisting of 64 bytes, the physical storage
address of which is determined by Bank Select n.
An additional zero bit can be output following the CRC
bits. However, disabling the zero bit by NZB = 1 is recommended when the output data length does not need
to comply with existing applications.
iC-NQC supports up to 16 storage banks, making it
possible to use an 8-bit EEPROM to its full capacity.
There is therefore also enough storage space for an
ID plate (EDS) and OEM data.
To obtain a position data output being compatible to the
BiSS B protocol parameter ENCDS = 0 does switch off
the CDS bit, without a replacement by a zero bit. Thus,
the output data length is shorten by one bit and register
communication is limited to the direction of the master
to the slave. The bidirectional BiSS C register communication must be enabled by setting ENCDS = 1.
Example Of BiSS Data Output
SCD: Angle data
Bits
Typ
Label
12
2
6
DATA
ERROR
CRC
Angle data S(11:0)
Error nE and warning nW
Polynomial 0x43
Config.
SELRES = 0x04, M2S = 0x00, CRC6 = 0, NZB = 1
Table 40: Example format 1 for BiSS profile BP1
Information regarding memory map and addressing
via BiSS is given on page 25).
Internal Reset Function
A write access at RAM address 0x00 (BiSS address
0x00 with Bank Select n = 0) triggers an internal reset.
Based on the current configuration in the RAM, iCNQC restarts without reading the EEPROM. The configured interface timeout and write protect settings become active, the period counter is set to zero and any
stored configuration errors are deleted. Providing no
amplitude error is present, the converter again counts
up from an angle value of zero to the current angle position.
Short BiSS Timeout
For programming via the I/O interface iC-NQC has a
short BiSS timeout function according to the description of the BiSS C protocol (see page 19, Table 2, El.
Char. no. 6).
iC-NQC
preliminary
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev B1, Page 21/29
Regardless of register protection settings a short timeout of typically 1.8 µs can be temporarily activated by
writing value 0x07 to address 0x7C (address 124d).
A controller can then transmit the device configuration
over a shorter period.
TOS
Code
Adr 0x7C, Bit 2:0
Function
000
001...111
Regular timeout (configured by TIMO)
Short timeout (equal to TIMO = 1)
Table 43: Short timeout (via BiSS device ID)
The value written to address 0x7C is also transferred
to the EEPROM, provided an EEPROM has been connected up and is available.
On reading address 0x7C the byte stored in the EEPROM is output as part of the BiSS device ID. Here,
high-order bits 7:3 are part of the manufacturer’s ID;
low-order bits 2:0 act as an indicator of the timeout options (regular or short timeout, see Table 43).
preliminary
iC-NQC
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev B1, Page 22/29
I/O INTERFACE: SSI Protocol
iC-NQC can transmit position data in SSI protocol
mode; the parameters described in the following give
the necessary settings and options.
M2S
Code
Adr 0x00, Bit 6:5
Period counter output length
0x00
0x01
0x02
0x03
P(7:0)
P(11:0)
P(23:0)
Table 46: Period counter for SSI data output
Figure 17: Example line signal (SSI)
SELSSI
Code
Adr 0x02, Bit 6
Protocol
0
1
BiSS C
SSI
CRC6
NZB
Code
Adr 0x03, Bit 7
Adr 0x03, Bit 6
Additional bits
Ring operation
00
01
10
E1, E0
none
E1, E0, zero bit
no
no
yes
11
none
yes
Table 47: Options for SSI data output
Table 44: Protocol version
GRAY
Adr 0x05, Bit 7
Code
SSI data format
fclk(MA)min*
0
1
binary coded
gray coded
50 kHz
Notes
Data output starts with MSB for binary or Gray
coded data.
TIMO
Code
Adr 0x06, Bit 5
Timeout ttos
0
1
TOA
0
Long: ca. 20 µs
not permitted
Adr 0x07, Bit 3
see TOS
1
not permitted
Notes
32
A ref. clock count is equal to fosc
(see El. Char.
A01). The permissible max. clock frequency is
specified by item E06.
*) A low clock frequency can reduce the permissible
maximum input frequency since conversion is
paused for one MA cycle from Latch onwards.
Table 45: Timeout configuration for SSI
Table 48: SSI data format
preliminary
iC-NQC
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev B1, Page 23/29
Examples Of SSI Data Output
SSI Output Formats
13-bit SSI
Res
Mode Error CRC
10 bit SSI
X
-
T1
T2
T3
T4... T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25
S9
S8
S7
S6 ... S0
E1
E0
Example
13 bit SSI
-
-
0
Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop
0
0
Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop
S12 S11 S10 S9 ... S3
S2
S1
S0
S12 S11 S10 S9 ... S3
S2
S1
S0
0
0
0
0
0
0
0
0
0
0
0
*1
Example
SSI-R -
-
0
0
0
0
0
Stop S12 S11 S10 S9
0
0
0
0
0
0
0
S8
S7
S6
S5
S4
S3
S2
*2
Example
0
25-bit SSI
13 bit SSI
X
-
S12 S11 S10 S9 ... S3
S2
S1
S0
E1
E0
Example
8 + 13 SSI
bit*3
X
-
P7
P6
P5
P4 ... P0, S10 S9
S12, S11
S8
S7
S6
0
Stop Stop Stop Stop Stop Stop Stop Stop Stop
0
0
0
0
0
0
0
0
0
0
S5
S4
S3
S2
S1
S0
E1
E0
0
Stop
0
0
Example
Configuration Input SLI = 0, SELSSI = 1, M2S = 0x00, CRC6 = 0, NZB = 0, unless otherwise noted.
*1) CRC6 = 0, NZB = 1; *2) CRC6 = 1, NZB = 1; *3) M2S = 0x01
Caption SSI = SSI protocol
SSI-R = SSI ring operation
Table 49: SSI transmission formats
preliminary
iC-NQC
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev B1, Page 24/29
EEPROM INTERFACE
The serial EEPROM interface consists of the two pins
SCL and SDA and enables read and write access to
a serial EEPROM with I2 C interface (such as a 24C02
with 128 bytes, 5 V type with a 3.3 V function).
The configuration data in the EEPROM, of addresses
0x00 to 0x0F, is secured by a CRC check value to address 0x0F. When the device is powered up, the address range from 0x00 to 0x0F is mapped onto iCNQC’s configuration RAM. The higher memory area
contains BiSS C slave registers and optional memory
banks available to the sensor system.
The register access to the configuration data and the
memory banks 1 to 7 (intended for EDS) can be restricted by parameter RPL.
Example of CRC Calculation Routine
unsigned char ucDataStream = 0 ;
i n t iCRCPoly = 0x127 ;
unsigned char ucCRC=0;
int i = 0;
ucCRC = 0 ; / / s t a r t v a l u e ! ! !
f o r ( iReg = 0 ; iReg <15; iReg ++)
{
ucDataStream = ucGetValue ( iReg ) ;
f o r ( i =0; i <=7; i ++) {
i f ( ( ucCRC & 0x80 ) ! = ( ucDataStream & 0x80 ) )
ucCRC = (ucCRC << 1 ) ^ iCRCPoly ;
else
ucCRC = (ucCRC << 1 ) ;
ucDataStream = ucDataStream << 1 ;
}
}
CRC_E2P
Code
Adr 0x0F, Bit 7:0
Description
0x00
...
0xFF
Check value formed by CRC polynomial 0x127
Register Configuration
BiSS Adr
BiSS Adr
hex
decimal
Contents
0x00...0F
0x10...1F
0x20...3F
Config. Data RAM (16 bytes)
Config. Data EEPROM (16 bytes)
Unused memory area (32 bytes)
0...15
16...31
32...63
BiSS C Slave-Registers (direct addresses):
0x40
64
Bank Select (1 byte)
0x41
65
EDS Bank (1 byte)
0x42...43
0x44...47
0x48...77
66...67
68...71
72...119
Profile ID (2 bytes)
Serial No. (4 bytes)
Slave Registers (48 bytes)
0x78
0x79
0x7A
0x7B
0x7C
120
121
122
123
124
Device ID (6 bytes):
4E (default)
51 (default)
43 (default)
31 (default)
Bit 7:3: Adr 0x00, Bit 2:0: TOS
0x7D
125
00 (default)
0x7E
126
Manufacturer’s ID (2 bytes):
69 (default)
0x7F
127
43 (default)
Table 51: Register overview
RPL
Code
Adr 0x03, Bit 3
Bank 0
0x40..7F
Config. Dat. BiSS ID
Bank 1..7
EDS
Bank 8..15
User Data
0x0
read /
write
read /
write
read /
write
read /
write
0x1
-
read*
read
read /
write
Notes
*) Exception: write to 0x40 and 0x7C is always
possible.
Table 52: Register protection settings
Table 50: Check value for EEPROM data
preliminary
iC-NQC
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Direct Access Registers
RAM
0x00 Configuration
0x0F Data
-16
0x3F
0x40
0x41
0x42
0x43
0x44
0x47
0x48
0x77
0x78
0x7D
0x7E
0x7F
Bank Selection ®n
0x00
0x3F
n=1
Bank 0
EEPROM
0x00 Configuration
0x0F Data
0x10 unused
0x2F
0x30 not available
0x31 EDS Bank
0x32
Profile ID
0x33
0x34
Serial Number
0x37
0x38
Slave Register
0x78
0x7D
0x7E
0x7F
ROM
n=2
n=3
n = ...14
n = 15
0x67
0x68
Device ID
0x6D
0x6E
Manufact. ID
0x6F
0x70
not available
0x7F
Bank 1
0x80
0xBF
Bank 2
0xC0
0xFF
Bank 3
0x100
0x13F
...0x3FF Bank ...14
Bank 15
0x400
0x43F
not available
Bank 0
8 kbit / 24C08
n=0
16k bit / 24C16
BiSS
0x00
0x0F
0x10
0x1F
0x20
2 kbit / 24C02
Registers (Bank n)
Rev B1, Page 25/29
R/W
---
0x41...0x7F
R/W
R
Bank 1...7
R/W
R
Bank 8...15
R/W
R/W
RPL0 RPL1
Register
Protection
Figure 18: Registers and addressing
STARTUP BEHAVIOR
After the supply has been turned on (power on reset),
iC-NQC reads the configuration data from the EEPROM and during this phase halts error pin NERR actively on a low signal (open drain output) as well as
data output SLO on a high signal.
After a successful CRC the data output is released
and the error indication at pin NERR reset; an external pull-up resistor can supply a high signal. iC-NQC
then switches to normal operation and determines the
current angle position, providing that a sensor is connected up to it and there is no amplitude error (or this
is deactivated).
Should the CRC prove unsuccessful due to a data error (disrupted transmission, no EEPROM or the EEPROM is not programmed), the configuration phase is
automatically repeated. After a third failed attempt, the
procedure is aborted and error pin NERR remains active, displaying a permanent low.
After startup, iC-NQC does not recognize a defined
configuration; the configuration RAM can contain any
values.
So that it is always possible to configure the setup using the I/O interface - even without an EEPROM - iCNQC first ignores parameters TIMO, TOA and RPL.
The I/O interface can then be addressed in BiSS C
protocol with the longest timeout (30 µs maximum),
without safety settings being observed (cf. RPL =
0x0).This allows the configuration to be written to RAM
addresses 0x01 to 0x0C and to address 0x00. Address 0x00 must be written to last of all and triggers an
internal reset (see description on page 20).
A short timeout of 3 µs maximum can be temporarily activated by writing value 0x07 to address 0x7C
(address 124d) to keep the device configuration time
shorter.
When operated without an EEPROM, iC-NQC does
not respond to higher addresses - with the exception
of the BiSS addresses reserved for manufacturers and
device IDs (0x78 to 0x7F). This address area supplies
the chip version from the ROM.
preliminary
iC-NQC
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev B1, Page 26/29
APPLICATION NOTES
Principle input circuits
PSIN
+
PSIN
11µApp
PSIN
+
RS1
25kS
-
1Vss to 120S
-
RS2
25kS
NSIN
NSIN
+
PSIN
INPUT SIN
VREF
RS
120S
NSIN
-
SENSOR
iC-NQC
case
NSIN
+
INPUT SIN
VREF
SENSOR
iC-NQC
case
Figure 20: Input circuit for current signals of 11 µA
with no ground reference. Offset calibration is not possible with this circuit.
Figure 19: Input circuit for voltage signals of 1 Vpp
with no ground reference. When ground
is not separated the connection NSIN to
VREF must be omitted.
+5V
R3
1kS
R001
1kS
R1
1kS
-
+
+
R2
1kS
V-GEN
1Vpp
PSIN
PSIN
R002
1kS
+
-
R4
1kS
-
V-GEN
2Vpp
-
NSIN
NSIN
+
+
INPUT SIN
INPUT SIN
VREF
VREF
iC-NQC
Figure 21: Input circuit for non-symmetrical voltage
or current source signals with ground reference (adaptation via resistors R3, R4).
iC-NQC
Figure 22: Simplified input wiring for nonsymmetrical voltage signals with ground
reference.
R1
10kS
+TTL
-TTL or open
-
5kS
RS3
1kS
PSIN
+
5kS
PSIN
-
+
+
+SIN
R2
10kS
120S
RS2
5kS
-SIN
Ip
10µApp
RS1
5kS
GAIN= 10
CS1
220pF
RS4
1kS
NSIN
+
-
In
10µApp
NSIN
+
INPUT SIN
ENCODER
VREF
case
CS2
47nF
iC-NQC
INPUT SIN
VREF
iC-NQC
Figure 23: Input circuit for complementary low-side
current source outputs, such as for optoencoder iC-WG.
Figure 24: Combined input circuit for 11 µA, 1 Vpp
(with 120 Ω termination) or TTL encoder
signals. RS3/4 and CS1 serve as protection against ESD and transients.
preliminary
iC-NQC
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev B1, Page 27/29
Basic circuit
Figure 25: Basic circuit for the evaluation of MR bridge sensors.
EVALUATION BOARD
iC-NQC comes with a demo board for test purposes.
Instructions are available separately.
DESIGN REVIEW: Function Notes
iC-NQC 1
No.
Function, Parameter/Code
Description and Application Notes
Please refer to datasheet release A1.
Table 53: Notes on chip functions regarding iC-NQC chip release 1.
iC-NQC 2
No.
Function, Parameter/Code
Description and Application Notes
Table 54: Notes on chip functions regarding iC-NQC chip release 2.
iC-NQC
preliminary
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev B1, Page 28/29
iC-Haus expressly reserves the right to change its products and/or specifications. An info letter gives details as to any amendments and additions made to the
relevant current specifications on our internet website www.ichaus.de/infoletter; this letter is generated automatically and shall be sent to registered users by
email.
Copying – even as an excerpt – is only permitted with iC-Haus’ approval in writing and precise reference to source.
iC-Haus does not warrant the accuracy, completeness or timeliness of the specification and does not assume liability for any errors or omissions in these
materials.
The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, fitness
for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which information refers and no
guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of
the product.
iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade
mark rights of a third party resulting from processing or handling of the product and/or any other use of the product.
As a general rule our developments, IPs, principle circuitry and range of Integrated Circuits are suitable and specifically designed for appropriate use in technical
applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. In principle the range of
use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued
annually by the Bureau of Statistics in Wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in
Hanover (Hannover-Messe).
We understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations
of patent law. Our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can
be put to.
preliminary
iC-NQC
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev B1, Page 29/29
ORDERING INFORMATION
Type
Package
Order Designation
iC-NQC
TSSOP20 4.4 mm
iC-NQC TSSOP20
Evaluation Board
iC-NQC EVAL NQ6D
For technical support, information about prices and terms of delivery please contact:
iC-Haus GmbH
Am Kuemmerling 18
D-55294 Bodenheim
GERMANY
Tel.: +49 (61 35) 92 92-0
Fax: +49 (61 35) 92 92-192
Web: http://www.ichaus.com
E-Mail: [email protected]
Appointed local distributors: http://www.ichaus.com/sales_partners