ICS843003 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS843003 is a 3 differential output LVPECL Synthesizer designed to generate Ethernet referHiPerClockS™ ence clock frequencies and is a member of the HiPerClocks™ family of high performance clock solutions from ICS. Using a 31.25MHz or 26.041666MHz, 18pF parallel resonant crystal, the following frequencies can be generated based on the settings of 4 frequency select pins (DIV_SEL[A1:A0], DIV_SEL[B1:B0]): 625MHz, 312.5MHz, 156.25MHz, and 125MHz. The 843003 has 2 output banks, Bank A with 1 differential LVPECL output pair and Bank B with 2 differential LVPECL output pairs. • Three 3.3V LVPECL outputs on two banks, A Bank with one LVPECL pair and B Bank with 2 LVPECL output pairs • Using a 31.25MHz or 26.041666 crystal, the two output banks can be independently set for 625MHz, 312.5MHz, 156.25MHz or 125MHz • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input • VCO range: 560MHz to 700MHz • RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz): 0.51ps (typical) • RMS phase noise at 156.25MHz Phase noise: Offset Noise Power 100Hz ............... -96.8 dBc/Hz 1KHz .............. -119.1 dBc/Hz 10KHz .............. -126.4 dBc/Hz 100KHz .............. -127.0 dBc/Hz • Full 3.3V supply mode • 0°C to 70°C ambient operating temperature • Industrial temperature available upon request ICS The two banks have their own dedicated frequency select pins and can be independently set for the frequencies mentioned above. The ICS843003 uses ICS’ 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter requirements. The ICS843003 is packaged in a small 24-pin TSSOP package. PIN ASSIGNMENT DIV_SELB0 VCO_SEL MR VCCO_A QA0 nQA0 OEB OEA FB_DIV VCCA VCC DIV_SELA0 BLOCK DIAGRAM DIV_SELA[1:0] Pullup TEST_CLK Pulldown XTAL_IN XTAL_OUT XTAL_SEL Pullup 00 01 ÷1 ÷2 (default) 10 11 ÷4 ÷5 FB_DIV 00 ÷1 0 = ÷20 (default) 1 = ÷24 01 10 ÷2 ÷4 (default) 11 ÷5 0 OSC 24 23 22 21 20 19 18 17 16 15 14 13 DIV_SELB1 VCCO_B QB0 nQB0 QB1 nQB1 XTAL_SEL TEST_CLK XTAL_IN XTAL_OUT VEE DIV_SELA1 ICS843003 OEA Pullup VCO_SEL 1 2 3 4 5 6 7 8 9 10 11 12 1 0 Phase Detector VCO 625MHz 24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body G Package QA0 Top View nQA0 1 QB0 FB_DIV Pulldown nQB0 QB1 nQB1 DIV_SELB[1:0] MR Pulldown OEB Pullup 843003AG www.icst.com/products/hiperclocks.html 1 REV. A JULY 27, 2004 ICS843003 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number Name Type Description Division select pin for Bank B. Default = Low. Pulldown LVCMOS/LVTTL interface levels. VCO select pin. When Low, the PLL is bypassed and the cr ystal reference or TEST_CLK (depending on XTAL_SEL setting) are passed directly to the Pullup output dividers. Has an internal pullup resistor so the PLL is not bypassed by default. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx Pulldown to go high. When logic LOW, the internal dividers and the outputs are enabled. Has an internal pulldown resistor so the power-up default state of outputs and dividers are enabled. LVCMOS/LVTTL interface levels. Output supply pin for Bank A outputs. 1 DIV_SELB0 Input 2 VCO_SEL Input 3 MR Input 4 VCCO_A Power 5, 6 QA0, nQA0 Ouput 7 OEB Input Pullup 8 OEA Input Pullup 9 FB_DIV Input Pulldown 10 VCCA Power 11 VCC Power 12 DIV_SELA0 Input 13 DIV_SELA1 Input 14 VEE Power 15, 16 XTAL_OUT, XTAL_IN Input 17 TEST_CLK Input 18 XTAL_SEL Input 19, 20 nQB1, QB1 Output 21, 22 nQB0, QB0 Output Differential output pair. LVPECL interface levels. Output enable Bank B. Active High output enable. When logic HIGH, the output pair on Bank B is enabled. When logic LOW, the output pair drives differential Low (QB0=Low, nQB0=High). Has an internal pullup resistor so the default power-up state of outputs are enabled. LVCMOS/LVTTL interface levels. Output enable Bank A. Active High output enable. When logic HIGH, the 2 output pairs on Bank A are enabled. When logic LOW, the output pair drives differential Low (QA0=Low, nQA0=High). Has an internal pullup resistor so the default power-up state of outputs are enabled. LVCMOS/LVTTL interface levels. Feedback divide select. When Low (default), the feedback divider is set for ÷20. When HIGH, the feedback divider is set for ÷24. LVCMOS/LVTTL interface levels. Analog supply pin. Core supply pin. Division select pin for Bank A. Default = HIGH. Pullup LVCMOS/LVTTL interface levels. Division select pin for Bank A. Default = Low. Pulldown LVCMOS/LVTTL interface levels. Negative supply pin. Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the input. XTAL_IN is also the overdrive pin if you want to overdrive the cr ystal circuit with a single-ended reference clock. Single-ended reference clock input. Has an internal pulldown resistor to Pulldown pull to low state by default. Can leave floating if using the cr ystal interface. LVCMOS/LVTTL interface levels. Cr ystal select pin. Selects between the single-ended TEST_CLK or cr ystal Pullup interface. Has an internal pullup resistor so the cr ystal interface is selected by default. LVCMOS/LVTTL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Output supply pin for Bank B outputs. Division select pin for Bank B. Default = High. 24 DIV_SELB1 Input Pullup LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 23 843003AG VCCO_B Power www.icst.com/products/hiperclocks.html 2 REV. A JULY 27, 2004 ICS843003 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions CIN Input Capacitance Minimum Typical Maximum 4 Units pF RPULLDOWN Input Pulldown Resistor 51 KΩ RPULLUP Input Pullup Resistor 51 KΩ TABLE 3A. BANK A FREQUENCY TABLE Inputs Bank A Output Divider M/N Multiplication Factor QA0/nQA0 Output Frequency Crystal Frequency DIV_SELA1 DIV_SELA0 FB_DIV Feedback Divider 31.25 0 0 0 20 1 20 625 31.25 0 1 0 20 2 10 312.5 31.25 1 0 0 20 4 5 156.25 31.25 1 1 0 20 5 4 125 26.041666 0 0 1 24 1 24 625 26.041666 0 1 1 24 2 12 312.5 26.041666 1 0 1 24 4 6 156.25 26.041666 1 1 1 24 5 4.8 125 Bank B Output Divider M/N Multiplication Factor QBx/nQBx Output Frequency TABLE 3B. BANK B FREQUENCY TABLE Inputs Crystal Frequency DIV_SELA1 DIV_SELA0 FB_DIV Feedback Divider 31.25 0 0 0 20 1 20 625 31.25 0 1 0 20 2 10 312.5 31.25 1 0 0 20 4 5 156.25 31.25 1 1 0 20 5 4 125 26.041666 0 0 1 24 1 24 625 26.041666 0 1 1 24 2 12 312.5 26.041666 1 0 1 24 4 6 156.25 26.041666 1 1 1 24 5 4.8 125 843003AG www.icst.com/products/hiperclocks.html 3 REV. A JULY 27, 2004 ICS843003 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 3C. OUTPUT BANK CONFIGURATION SELECT FUNCTION TABLE Inputs Outputs Inputs Outputs DIV_SELA1 DIV_SELA0 QA DIV_SELB1 DIV_SELB0 QB 0 0 ÷1 0 0 ÷1 0 1 ÷2 0 1 ÷2 1 0 ÷4 1 0 ÷4 1 1 ÷5 1 1 ÷5 TABLE 3D. FEEDBACK DIVIDER CONFIGURATION SELECT FUNCTION TABLE Inputs FB_DIV Feedback Divide 0 ÷20 1 ÷24 Enabled Disabled TEST_CLK OEA, OEB nQA0, nQBx QA0, QBx FIGURE 1. OE TIMING DIAGRAM 843003AG www.icst.com/products/hiperclocks.html 4 REV. A JULY 27, 2004 ICS843003 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 70°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VCC Core Supply Voltage Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V VCCO_A, B Output Supply Voltage 3.135 3.3 3.465 V I EE Power Supply Current ICCA Analog Supply Current Included in IEE 158 mA 15 mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage DIV_SELA0:A1, FB_DIV DIV_SELB0:B1, VCO_SEL, Input Low Voltage MR, OEA, OEB, XTAL_SEL TEST_CLK TEST_CLK, MR, FB_DIV DIV_SELA1, DIV_SELB0 Input High Current DIV_SELB1, DIV_SELA0, VCO_SEL, XTAL_SEL, OEA, OEB TEST_CLK, MR, FB_DIV DIV_SELA1, DIV_SELB0 Input Low Current DIV_SELB1, DIV_SELA0, VCO_SEL, XTAL_SEL, OEA, OEB VIL IIH IIL 843003AG Test Conditions Minimum Typical Maximum Units 2 VCC + 0.3 V -0.3 0.8 V -0.3 1.3 V VCC = VIN = 3.465V 150 µA VCC = VIN = 3.465V 5 µA VCC = 3.465V, VIN = 0V -5 µA VCC = 3.465V, VIN = 0V -150 µA www.icst.com/products/hiperclocks.html 5 REV. A JULY 27, 2004 ICS843003 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum VCCO - 1.4 Typical VCCO - 0.9 V VOL Output Low Voltage; NOTE 1 VCCO - 2.0 VCCO - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V Maximum Units NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Frequency Typical Fundamental FB_DIV = ÷20 28 31.25 35 MHz FB_DIV = ÷24 23.33 26.04166 29.167 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF NOTE: Characterized using an 18pF parallel resonant crystal. TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fOUT Output Frequency Range tsk(b) Bank Skew, NOTE 1 tsk(o) tjit(Ø) tR / tF Output Skew; NOTE 2, 4 RMS Phase Jitter (Random); NOTE 3 Output Rise/Fall Time Test Conditions Minimum Maximum Units DIV_SELx[1:0] = 00 560 Typical 700 MHz DIV_SELx[1:0] = 01 280 350 MHz DIV_SELx[1:0] = 10 140 175 MHz DIV_SELx[1:0] = 11 112 140 MHz 20 ps 35 ps Outputs @ Same Frequency Outputs @ Different Frequencies 100 0.42 ps 312.5MHz (1.875MHz - 20MHz) 0.50 ps 156.25MHz (1.875MHz - 20MHz) 0.51 ps 125MHz (1.875MHz - 20MHz) 0.52 ps 20% to 80% 250 DIV_SELx[1:0] = 00 40 odc Output Duty Cycle DIV_SELx[1:0] ≠ 00 47 NOTE 1: Defined as skew winthin a bank of outputs at the same voltages and with equal load conditions. NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential cross points. NOTE 3: Please refer to the Phase Noise Plots. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 843003AG ps 625MHz (1.875MHz - 20MHz) www.icst.com/products/hiperclocks.html 6 600 ps 60 53 % % REV. A JULY 27, 2004 ICS843003 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE AT 125MHZ ➤ 0 -10 -20 10Gb Ethernet Filter -30 -40 125MHz -50 RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.52ps (typical) -70 -80 -90 -100 Raw Phase Noise Data -110 ➤ NOISE POWER dBc Hz -60 -120 -130 -140 -150 ➤ -160 -170 Phase Noise Result by adding 10Gb Ethernet Filter to raw data -180 -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 156.25MHZ ➤ 0 -10 -20 10Gb Ethernet Filter -30 -40 156.25MHz -50 RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.51ps (typical) -70 -80 -90 Raw Phase Noise Data -100 -110 ➤ NOISE POWER dBc Hz -60 -120 -130 -140 -150 ➤ -160 -170 Phase Noise Result by adding 10Gb Ethernet Filter to raw data -180 -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 843003AG www.icst.com/products/hiperclocks.html 7 REV. A JULY 27, 2004 ICS843003 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE AT 312.5MHZ ➤ 0 -10 -20 10Gb Ethernet Filter -30 -40 312.5MHz -50 RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.50ps (typical) -70 -80 -90 Raw Phase Noise Data -100 ➤ NOISE POWER dBc Hz -60 -110 -120 -130 -140 ➤ -150 -160 -170 Phase Noise Result by adding 10Gb Ethernet Filter to raw data -180 -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 625MHZ ➤ 0 -10 -20 10Gb Ethernet Filter -30 -40 625MHz -50 RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.42ps (typical) -70 -80 Raw Phase Noise Data -90 -100 ➤ NOISE POWER dBc Hz -60 -110 -120 -130 -140 ➤ -150 -160 -170 Phase Noise Result by adding 10Gb Ethernet Filterto raw data -180 -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 843003AG www.icst.com/products/hiperclocks.html 8 REV. A JULY 27, 2004 ICS843003 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 2V Qx V CC, nQx SCOPE Qx VCCA, VCCO_A. _B nQy LVPECL Qy nQx VEE tsk(o) -1.3V±0.165V 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW Phase Noise Plot Noise Power nQB0 QB0 nQB1 Phase Noise Mask QB1 tsk(b) f1 Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot RMS PHASE JITTER BANK SKEW nQA0, nQB0, nQB1 QA0, QB0, QB1 80% 80% VSW I N G Pulse Width t odc = Clock Outputs PERIOD 20% 20% t PW tR tF t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 843003AG OUTPUT RISE/FALL TIME www.icst.com/products/hiperclocks.html 9 REV. A JULY 27, 2004 ICS843003 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843003 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCOx should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10Ω resistor along with a 10µF and a .01µF bypass capacitor should be connected to each VCCA pin. 3.3V VCC .01µF 10 Ω VCCA .01µF 10µF FIGURE 2. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE The ICS843003 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 3 below were determined using a 31.25MHz or 26.041666MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error. XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 27p ICS843003 Figure 3. CRYSTAL INPUt INTERFACE 843003AG www.icst.com/products/hiperclocks.html 10 REV. A JULY 27, 2004 ICS843003 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 4A. LVPECL OUTPUT TERMINATION 843003AG 125Ω 84Ω FIGURE 4B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 11 REV. A JULY 27, 2004 ICS843003 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER LAYOUT GUIDELINE Figure 5A shows a schematic example of the ICS843003. An example of LVEPCL termination is shown in this schematic. Additional LVPECL termination approaches are shown in the LVPECL Termination Application Note. In this example, an 18 pF parallel resonant 31.25MHz crystal is used. The C1=27pF and C2=33pF are recommended for frequency accuracy. The C1 and C2 may be slightly adjusted for optimizing frequency accuracy. 3.3V VCCA VCC R2 10 R5 133 R3 133 Zo = 50 Ohm C3 10uF C4 0.01u + VCC VCCO C6 0.1u To Logic Input pins RD1 Not Install To Logic Input pins RD2 1K U1 ICS843003 DIV_SELA1 VEE XTAL_OUT XTAL_IN TEST_CLK XTAL_SEL nQB1 QB1 nQB0 QB0 VCCO_B DIV_SELB1 RU2 Not Install RU1 1K - R6 82.5 R4 82.5 DIV_SELA0 VCC VCCA FB_DIV OEA OEB nQA0 QA0 VCCO_A MR VCO_SEL DIV_SELB0 Set Logic Input to '0' VDD VCC=3.3V 3.3V VCCO=3.3V R7 133 13 14 15 16 17 18 19 20 21 22 23 24 Set Logic Input to '1' VDD Zo = 50 Ohm C7 0.1u 12 11 10 9 8 7 6 5 4 3 2 1 Logic Control Input Examples R9 133 VCCO Zo = 50 Ohm + Zo = 50 Ohm C2 33pF X1 31.25MHz 18pF C8 0.1u R8 82.5 - R10 82.5 C1 27pF FIGURE 5A. ICS843003 SCHEMATIC EXAMPLE PC BOARD LAYOUT EXAMPLE Figure 5B shows an example of ICS843003 P.C. board layout. The crystal X1 footprint shown in this example allows installation of either surface mount HC49S or through-hole HC49 package. The footprints of other components in this example are listed in the Table 7. There should be at least one decoupling capacitor per power pin. The decoupling capacitors should be located as close as possible to the power pins. The layout assumes that the board has clean analog power ground plane. TABLE 7. FOOTPRINT TABLE Reference Size C1, C2 0402 C3 0805 C4, C5, C6, C7, C8 0603 R2 0603 NOTE: Table 7, lists component sizes shown in this layout example. FIGURE 5B. ICS843003 PC BOARD LAYOUT EXAMPLE 843003AG www.icst.com/products/hiperclocks.html 12 REV. A JULY 27, 2004 ICS843003 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS843003. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843003 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 158mA = 547.5mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 3 * 30mW = 90mW Total Power_MAX (3.465V, with all outputs switching) = 547.5mW + 90mW = 637.5mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 8 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.638W * 65°C/W = 111.5°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 8. THERMAL RESISTANCE θJA FOR 24-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 843003AG 0 1 2.5 70°C/W 65°C/W 62°C/W www.icst.com/products/hiperclocks.html 13 REV. A JULY 27, 2004 ICS843003 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V (V CCO_MAX • -V ) = 0.9V OH_MAX For logic low, VOUT = V OL_MAX (V CCO_MAX -V OL_MAX =V CC_MAX – 1.7V ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. ))/R ] * (V – (V - 2V))/R ] * (V -V ) = [(2V - (V -V -V )= Pd_H = [(V OH_MAX CC_MAX CC_MAX OH_MAX OH_MAX CC_MAX OH_MAX L CC_MAX L [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(V OL_MAX – (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V )= OL_MAX [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 843003AG www.icst.com/products/hiperclocks.html 14 REV. A JULY 27, 2004 ICS843003 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 9. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 70°C/W 65°C/W 62°C/W TRANSISTOR COUNT The transistor count for ICS843003 is: 3767 843003AG www.icst.com/products/hiperclocks.html 15 REV. A JULY 27, 2004 ICS843003 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 24 LEAD TSSOP TABLE 10. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N A Maximum 24 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.90 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 843003AG www.icst.com/products/hiperclocks.html 16 REV. A JULY 27, 2004 ICS843003 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 11. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS843003AG ICS843003AG 24 Lead TSSOP 60 per tube 0°C to 70°C ICS843003AGT ICS843003AG 24 Lead TSSOP on Tape and Reel 2500 0°C to 70°C The aforementioned trademarks, HiPerClockS™ and FemtoClocks™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843003AG www.icst.com/products/hiperclocks.html 17 REV. A JULY 27, 2004