ICS873033 Integrated Circuit Systems, Inc. HIGH SPEED, ÷4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS873033 is a high speed, high performance Differential-to-3.3V, 5V LVPECL/ECL HiPerClockS™ Clock Generator a n d a m e m b e r o f t h e HiPerClockS ™ family of High Perfor mance Clock Solutions from ICS. The ICS873033 is characterized to operate from either a 3.3V or a 5V power supply. • One differential 3.3V, 5V LVPECL / ECL output ICS • One differential PCLK, nPCLK input pair • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Input frequency: 3.2GHz (maximum) • Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nPCLK input • Additive phase jitter, RMS: 0.20ps (typical) • LVPECL mode operating voltage supply range: VCC = 3.0V to 5.5V, VEE = 0V • ECL mode operating voltage supply range: VCC = 0V, VEE = -5.5V to -3.0V • -40°C to 85°C ambient operating temperature • Available in both standard and lead-free RoHS-compliant packages BLOCK DIAGRAM PIN ASSIGNMENT RESET PCLK nPCLK ÷4 RESET PCLK nPCLK VBB Q nQ 1 2 3 4 8 7 6 5 Vcc Q nQ VEE ICS873033 V BB 8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View ICS873033 8-Lead TSSOP, 118 mil 3mm x 3mm x 0.95mm package body G Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 873033AM www.icst.com/products/hiperclocks.html REV. A OCTOBER 19, 2005 1 ICS873033 Integrated Circuit Systems, Inc. HIGH SPEED, ÷4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name 1 RESET Input Type Pulldown Reset pin. Single-ended 100h LVPECL interface levels. Description 2 PCLK Input Pulldown Clock input. Default LOW when left floating. LVPECL interface levels. 3 nPCLK Input Pulldown Clock input. LVPECL interface levels. 4 VBB Output Bias voltage. 5 VEE Power Negative supply pin. 6, 7 nQ, Q Output Differential output pair. LVPECL interface levels. 8 VCC Power Positive supply pin. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions RPULLDOWN Input Pulldown Resistor Minimum Typical 75 Maximum Units kΩ TABLE 3. TRUTH TABLE Inputs Outputs PCLK nPCLK RESET Q nQ X X LH L H ÷4 ÷4 LH HL L LH = LOW to HIGH transistion HL = HIGH to LOW transistion PCLK tRR RESET tPW Q FIGURE 1. TIMING DIAGRAM 873033AM www.icst.com/products/hiperclocks.html 2 REV. A OCTOBER 19, 2005 ICS873033 Integrated Circuit Systems, Inc. HIGH SPEED, ÷4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 6V (LVPECL mode, VEE = 0) Negative Supply Voltage, VEE -6V (ECL mode, VCC = 0) Inputs, VI (LVPECL mode) -0.5V to VCC + 0.5V Inputs, VI (ECL mode) 0.5V to VEE - 0.5V Outputs, IO Continuous Current Surge Current VBB Sink/Source, IBB NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those 50mA 100mA listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maxi- ± 0.5mA mum rating conditions for extended periods may affect product reliability. Operating Temperature Range, TA -40°C to +85°C Storage Temperature, TSTG -65°C to 150°C Package Thermal Impedance, θJA 112.7°C/W (0 lfpm) (Junction-to-Ambient) for 8 Lead SOIC Package Thermal Impedance, θJA 101.7°C/W (0 m/s) (Junction-to-Ambient) for 8 Lead TSSOP TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.0V TO 5.5V; VEE = 0V Symbol Parameter VCC Positive Supply Voltage IEE Power Supply Current Test Conditions Minimum Typical Maximum Units 3.0 3.3 5.5 V 30 mA TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V Min -40°C Typ Max Min 25°C Typ Max Min 85°C Typ Max Output High Voltage; NOTE 1 2.175 2.275 2.38 2.225 2.295 2.37 2.295 2.33 2.365 V Output Low Voltage; NOTE 1 1.405 1.545 1.68 1.425 1.52 1.615 1.44 1.535 1.63 V VIH Input High Voltage(Single-Ended) 2.075 2.36 2.075 2.36 2.075 2.36 V VIL Input Low Voltage(Single-Ended) 1.43 1.765 1.43 1.765 1.43 1.765 V VBB Output Voltage Reference 1.86 1.98 1.86 1.98 1.86 1.98 V 1200 mV 3. 3 V 150 µA Symbol Parameter VOH VOL VPP 150 800 1200 150 800 1200 150 Peak-to-Peak Input Voltage Input High Voltage 1.2 3.3 1.2 3.3 1.2 VCMR Common Mode Range; NOTE 2, 3 Input 150 15 0 IIH PCLK, nPCLK High Current Input -10 -1 0 IIL -10 PCLK, nPCLK Low Current Input and output parameters vary 1:1 with VCC. VEE can vary +0.3V to -2.2V. NOTE 1: Outputs terminated with 50Ω to VCC - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V. 873033AM www.icst.com/products/hiperclocks.html 3 800 Units µA REV. A OCTOBER 19, 2005 ICS873033 Integrated Circuit Systems, Inc. HIGH SPEED, ÷4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 5V; VEE = 0V Min -40°C Typ Max Min 25°C Typ Max Min 85°C Typ Max Output High Voltage; NOTE 1 3.875 3.975 4.08 3.925 3.995 4.07 3.995 4.03 4.065 V Output Low Voltage; NOTE 1 3.105 3.245 3.38 3.125 3.22 3.315 3.14 3.235 3.33 V VIH Input High Voltage(Single-Ended) 3.775 4.06 3.775 4.06 3.775 4.06 V VIL Input Low Voltage(Single-Ended) 3.13 3.465 3.13 3.465 3.13 3.465 V VBB Output Voltage Reference 3.56 3.68 3.56 3.68 3.56 Symbol Parameter VOH VOL VPP 150 800 1200 150 800 1200 150 Peak-to-Peak Input Voltage Input High Voltage 1.2 5 1.2 5 1.2 VCMR Common Mode Range; NOTE 2, 3 Input 150 15 0 IIH PCLK, nPCLK High Current Input -10 -1 0 IIL -10 PCLK, nPCLK Low Current Input and output parameters vary 1:1 with VCC. VEE can vary +2V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCC - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V. 800 Units 3.68 V 1200 mV 5 V 150 µA µA TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -5.5V TO -3.0V Symbol -40°C Parameter 25°C Min Typ Max Min Typ 85°C Max Min Typ Max Units VOH Output High Voltage; NOTE 1 -1.125 -1.025 -0.92 -1.075 -1.005 -0.93 -1.005 -0.97 -0.935 V VOL Output Low Voltage; NOTE 1 -1.895 -1.755 -1.62 -1.875 -1.78 -1.685 -1.86 -1.765 -1.67 V VIH Input High Voltage(Single-Ended) -1.225 -0.94 -1.225 -0.94 -1.225 -0.94 V VIL Input Low Voltage(Single-Ended) -1.87 -1.535 -1.87 -1.535 -1.87 -1.535 V VBB Output Voltage Reference -1.44 -1.32 -1.44 -1.32 -1.44 -1.32 V 1200 mV 0 V 150 µA VPP 150 800 1200 150 800 1200 150 Peak-to-Peak Input Voltage Input High Voltage VEE+1.2V 0 VEE+1.2V 0 VEE+1.2V VCMR Common Mode Range; NOTE 2, 3 Input 150 150 PCLK, nPCLK IIH High Current Input -10 -10 -10 PCLK, nPCLK IIL Low Current Input and output parameters vary 1:1 with VCC. NOTE 1: Outputs terminated with 50Ω to VCC - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V. 873033AM www.icst.com/products/hiperclocks.html 4 800 µA REV. A OCTOBER 19, 2005 ICS873033 Integrated Circuit Systems, Inc. HIGH SPEED, ÷4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -5.5V TO -3.0V VCC = 3.0V TO 5.5V; VEE = 0V -40°C Symbol Parameter fMAX Input Frequency t PD Propagation Delay; NOTE 1 Buffer Additive Phase Jitter, RMS; 155.52MHz, Integration Range 12kHz - 20MHz; Refer to Additive Phase Jitter Section 300 tRR Set/Reset Recovery; NOTE 2 150 tR/tF Output Rise/Fall Time 100 tjit(Ø) OR Min Typ 25°C Max Min Typ 3.2 20% to 80% 475 85°C Max Min 300 430 530 350 0.20 200 250 100 100 200 250 www.icst.com/products/hiperclocks.html 5 450 Units 3.2 GHz 550 ps 0.20 ps 100 ps 100 tPW Pulse Width; NOTE 3 RESET 550 480 550 480 550 All parameters are measured at f ≤ 1.7GHz, unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: See Figure 1, Timing Diagram. 873033AM Max 3.2 0.20 100 Typ 250 480 ps ps REV. A OCTOBER 19, 2005 ICS873033 Integrated Circuit Systems, Inc. HIGH SPEED, ÷4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR ADDITIVE PHASE JITTER ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a 0 -10 Additive Phase Jitter -20 @ 155.52MHz (12kHz to 20MHz) = 0.20ps typical -30 -40 -50 SSB PHASE NOISE dBc/HZ -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated 873033AM above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. www.icst.com/products/hiperclocks.html 6 REV. A OCTOBER 19, 2005 ICS873033 Integrated Circuit Systems, Inc. HIGH SPEED, ÷4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 2V VCC Qx VCC SCOPE nPCLK LVPECL V V Cross Points PP CMR PCLK nQx VEE V EE -3.5V to -1.0V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL Phase Noise Plot Noise Power nPCLK PCLK nQ Phase Noise Mask Q tPD f1 Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot PROPAGATION DELAY RMS PHASE JITTER 80% 80% VSW I N G Clock Outputs 20% 20% tR tF OUTPUT RISE/FALL TIME 873033AM www.icst.com/products/hiperclocks.html 7 REV. A OCTOBER 19, 2005 ICS873033 Integrated Circuit Systems, Inc. HIGH SPEED, ÷4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K Single Ended Clock Input PCLK V_REF nPCLK C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 3 shows an example of the differential input that can be wired to accept single ended levels. The reference voltage level VBB generated from the device is connected to the negative input. The C1 capacitor should be located as close as possible to the input pin. VCC C1 0.1u CLK_IN PCLK VBB nPCLK FIGURE 3. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT 873033AM www.icst.com/products/hiperclocks.html 8 REV. A OCTOBER 19, 2005 ICS873033 Integrated Circuit Systems, Inc. HIGH SPEED, ÷4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR LVPECL CLOCK INPUT INTERFACE gested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces sug- 3.3V 3.3V R1 50 CML 3.3V 3.3V 3.3V Zo = 50 Ohm R2 50 Zo = 50 Ohm PCLK nPCLK PCLK R1 100 Zo = 50 Ohm nPCLK Zo = 50 Ohm HiPerClockS PCLK/nPCLK HiPerClockS PCLK/nPCLK CML Built-In Pullup FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER FIGURE 4B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 3.3V R4 125 Zo = 50 Ohm 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 84 R4 84 PCLK PCLK Zo = 50 Ohm nPCLK LVPECL R1 84 nPCLK HiPerClockS Input R5 100 - 200 R2 84 FIGURE 4C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER R6 100 - 200 R1 125 FIGURE 4D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE 3.3V 2.5V 3.3V 3.3V 3.3V 2.5V R3 120 SSTL Zo = 50 Ohm R4 120 C1 LVDS Zo = 60 Ohm R3 1K R4 1K PCLK PCLK R5 100 Zo = 60 Ohm nPCLK R1 120 C2 nPCLK Zo = 50 Ohm HiPerClockS PCLK/nPCLK R1 1K R2 120 FIGURE 4E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER 873033AM HiPerClockS PCLK/nPCLK R2 125 FIGURE 4F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER www.icst.com/products/hiperclocks.html 9 HiPerClockS PCL K/n PC LK R2 1K REV. A OCTOBER 19, 2005 ICS873033 Integrated Circuit Systems, Inc. HIGH SPEED, ÷4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR TERMINATION FOR 3.3V LVPECL OUTPUTS 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 3.3V Zo = 50Ω 125Ω FOUT FIN 125Ω Zo = 50Ω Zo = 50Ω FOUT 50Ω FIN 50Ω Zo = 50Ω VCC - 2V 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o RTT 84Ω FIGURE 5A. LVPECL OUTPUT TERMINATION 84Ω FIGURE 5B. LVPECL OUTPUT TERMINATION TERMINATION FOR 5V LVPECL OUTPUT This section shows examples of 5V LVPECL output termination. Figure 6A shows standard termination for 5V LVPECL. The termination requires matched load of 50Ω resistors pull down to VCC - 2V = 3V at the receiver. Figure 6B shows Thevenin equivalence of Figure 6A. In actual application where the 3V DC power supply is not available, this approached is normally used. 5V 5V 5V 5V R3 84 PECL PECL Zo = 50 Ohm R4 84 Zo = 50 Ohm + + Zo = 50 Ohm Zo = 50 Ohm - R1 50 - PECL R1 125 R2 50 PECL R2 125 3V FIGURE 6A. STANDARD 5V PECL OUTPUT TERMINATION 873033AM FIGURE 6B. 5V PECL OUTPUT TERMINATION EXAMPLE www.icst.com/products/hiperclocks.html 10 REV. A OCTOBER 19, 2005 ICS873033 Integrated Circuit Systems, Inc. HIGH SPEED, ÷4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS873033. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS873033 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 5.5V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 5.5V * 30mA = 165mW Power (outputs)MAX = 30.94mW/Loaded Output pair Total Power_MAX (5.5V, with all outputs switching) = 165mW + 30.94mW = 195.94mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 6A below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.196W * 103.3°C/W = 105.2°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6A. THERMAL RESISTANCE θJA FOR 8-PIN SOIC, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3°C/W 112.7°C/W 128.5°C/W 103.3°C/W 115.5°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 6B. THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 873033AM 0 1 2 101.7°C/W 90.5°C/W 89.8°C/W www.icst.com/products/hiperclocks.html 11 REV. A OCTOBER 19, 2005 ICS873033 Integrated Circuit Systems, Inc. HIGH SPEED, ÷4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC • For logic high, VOUT = V OH_MAX (V CC_MAX • -V OH_MAX OL_MAX CC_MAX -V OL_MAX CC_MAX –0.935V ) = 0.935V For logic low, VOUT = V (V =V =V CC_MAX – 1.67V ) = 1.67V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. ))/R ] * (V Pd_H = [(V – (V - 2V))/R ] * (V -V ) = [(2V - (V -V -V )= OH_MAX CC_MAX CC_MAX OH_MAX CC_MAX OH_MAX CC_MAX OH_MAX L L [(2V - 0.935V)/50Ω] * 0.935V = 19.92mW Pd_L = [(V OL_MAX – (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V OL_MAX )= [(2V - 1.67V)/50Ω] * 1.67V = 11.02mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW 873033AM www.icst.com/products/hiperclocks.html 12 REV. A OCTOBER 19, 2005 ICS873033 Integrated Circuit Systems, Inc. HIGH SPEED, ÷4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR RELIABILITY INFORMATION TABLE 7A. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3°C/W 112.7°C/W 128.5°C/W 103.3°C/W 115.5°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 7B. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2 101.7°C/W 90.5°C/W 89.8°C/W TRANSISTOR COUNT The transistor count for ICS873033 is: 165 Pin compatible with MC100EP33 873033AM www.icst.com/products/hiperclocks.html 13 REV. A OCTOBER 19, 2005 ICS873033 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - M SUFFIX HIGH SPEED, ÷4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR FOR 8 LEAD SOIC TABLE 8A. PACKAGE DIMENSIONS SYMBOL Millimeters MINIMUN N A MAXIMUM 8 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e H 1.27 BASIC 5.80 6.20 h 0.25 0.50 L 0.40 1.27 α 0° 8° Reference Document: JEDEC Publication 95, MS-012 873033AM www.icst.com/products/hiperclocks.html 14 REV. A OCTOBER 19, 2005 ICS873033 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX HIGH SPEED, ÷4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR FOR 8 LEAD TSSOP TABLE 8B. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N A Maximum 8 -- 1.10 A1 0 0.15 A2 0.79 0.97 b 0.22 0.38 c 0.08 0.23 D 3.00 BASIC E 4.90 BASIC E1 3.00 BASIC e 0.65 BASIC e1 1.95 BASIC L 0.40 0.80 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-187 873033AM www.icst.com/products/hiperclocks.html 15 REV. A OCTOBER 19, 2005 ICS873033 Integrated Circuit Systems, Inc. HIGH SPEED, ÷4 DIFFERENTIAL-TO3.3V, 5V LVPECL/ECL CLOCK GENERATOR TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS873033AM 873033AM 8 lead SOIC tube -40°C to 85°C ICS873033AMT 873033AM 8 lead SOIC 2500 tape & reel -40°C to 85°C ICS873033AMLF 873033AL 8 lead "Lead-Free" SOIC tube -40°C to 85°C ICS873033AMLFT 873033AL 8 lead "Lead-Free" SOIC 2500 tape & reel -40°C to 85°C ICS873033AG TBD 8 lead TSSOP tube -40°C to 85°C ICS873033AGT TBD 8 lead TSSOP 2500 tape & reel -40°C to 85°C ICS873033AGLF TBD 8 lead "Lead-Free" TSSOP tube -40°C to 85°C ICS873033AGLFT TBD 8 lead "Lead-Free" TSSOP 2500 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 873033AM www.icst.com/products/hiperclocks.html 16 REV. A OCTOBER 19, 2005