ICS853013 Integrated Circuit Systems, Inc. LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS853013 is a low skew, high performance dual 1-to-3 Differential-to-2.5V/3.3V/5V HiPerClockS™ LVPECL/ECL Fanout Buffer and a member of the HiperclocksTM family of High Performance Clock Solutions from ICS. The ICS853013 operates with a positive or negative power supply at 2.5V, 3.3V, or 5V. Guaranteed output and part-to-par t skew characteristics make the ICS853013 ideal for those clock distribution applications demanding well defined performance and repeatability. • Two differential LVPECL / ECL bank outputs ICS • Two differential LVPECL clock input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Output frequency: >2GHz (typical) • Translates any single ended input signal to LVPECL levels with resistor bias on nPCLKx input • Output skew: 40ps (maximum) • Part-to-part skew: 250ps (maximum) • Propagation delay: 570ps (maximum) • Additive phase jitter, RMS: 0.03ps (typical) • LVPECL mode operating voltage supply range: VCC = 2.375V to 5.25V • ECL mode operating voltage supply range: VCC = 0V, VEE = -5.25V to -2.375V • -40°C to 85°C ambient operating temperature • Available in both standard and lead-free RoHS-compliant packages BLOCK DIAGRAM PCLKA nPCLKA PIN ASSIGNMENT QA0 nQA0 nQA0 QA0 VCC PCLKA nPCLKA PCLKB nPCLKB VCC nQB0 QB0 QA1 nQA1 QA2 nQA2 PCLKB nPCLKB QB0 nQB0 20 19 18 17 16 15 14 13 12 11 QA1 nQA1 QA2 nQA2 VCC QB2 nQB2 QB1 nQB1 VEE ICS853013 QB1 nQB1 20-Lead, 300-MIL SOIC 7.5mm x 12.8mm x 2.3mm body package M Package Top View QB2 nQB2 853013AM 1 2 3 4 5 6 7 8 9 10 www.icst.com/products/hiperclocks.html 1 REV. A OCTOBER 19, 2005 ICS853013 Integrated Circuit Systems, Inc. LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 2 nQA0, QA0 Output 3, 8, 16 VCC Power 4 PCLKA Input 5 nPCLKA Input 6 PCLKB Input 7 nPCLKB Input 9, 10 nQB0, QB0 Output Differential output pair. LVPECL interface levels. 11 VEE Power Negative supply pin. 12, 13 nQB1, QB1 Output Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Power supply pins. Pulldown Pullup/ Pulldown Pulldown Pullup/ Pulldown Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. VCC/2 default when left floating. Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. VCC/2 default when left floating. 14, 15 nQB2, QB2 Output Differential output pair. LVPECL interface levels. 17, 18 nQA2, QA2 Output Differential output pair. LVPECL interface levels. 19, 20 nQA1, QA1 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter RPULLDOWN Input Pulldown Resistor Test Conditions Minimum Typical 75 Maximum Units kΩ RVCC/2 Pullup/Pulldown Resistors 50 kΩ TABLE 3. CLOCK INPUT FUNCTION TABLE Inputs PCLKA or PCLKB 0 nPCLKA or nPCLKB 1 1 0 Outputs QA0:QA2, nQA0:nQA2, QB0:QB2 nQB0:nQB2 HIGH LOW Input to Output Mode Polarity Differential to Differential Non Inver ting HIGH LOW Differential to Differential Non Inver ting 0 Biased; NOTE 1 LOW HIGH Single Ended to Differential Non Inver ting 1 Biased; NOTE 1 HIGH LOW Single Ended to Differential Non Inver ting Biased; NOTE 1 0 HIGH LOW Single Ended to Differential Inver ting Biased; NOTE 1 1 LOW HIGH Single Ended to Differential Inver ting NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels". 853013AM www.icst.com/products/hiperclocks.html 2 REV. A OCTOBER 19, 2005 ICS853013 Integrated Circuit Systems, Inc. LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Negative Supply Voltage, VEE 5.5V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage -5.5V (ECL mode, VCC = 0) Inputs, VI (LVPECL mode) -0.5V to VCC + 0.5V Inputs, VI (ECL mode) 0.5V to VEE - 0.5V Supply Voltage, VCC Outputs, IO Continuous Current Surge Current to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Character- 50mA 100mA istics is not implied. Exposure to absolute maximum rating conditions for extended periods may Operating Temperature Range, TA -40°C to +85°C Storage Temperature, TSTG -65°C to 150°C Package Thermal Impedance, θJA 46.2°C/W (0 lfpm) affect product reliability. (Junction-to-Ambient) TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375 TO 5.25V; VEE = 0V Symbol Parameter VCC Power Supply Voltage IEE Power Supply Current Test Conditions Minimum Typical Maximum Units 2.375 3.3 5.25 V 60 mA TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V Symbol Parameter VOH Output High Voltage; NOTE 1 Min -40°C Typ Max 2.175 2.275 2.38 1.545 VOL Output Low Voltage; NOTE 1 1.405 VIH Input High Voltage(Single-Ended) 2.075 VIL Input Low Voltage(Single-Ended) 1.43 VPP Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 Input PCLKA, PCLKB High Current nPCLKA, nPCLKB PCLKA, PCLKB Input Low Current nPCLKA, nPCLKB 150 VCMR IIH IIL 800 1.2 Min 25°C Typ Max 2.225 2.295 2.37 1.52 1.68 1.425 2.36 2.075 1.765 1.43 1200 150 3.3 1.2 800 150 -10 Min 85°C Typ Max 2.295 2.33 2.365 V 1.615 1.44 1.535 2.36 2.075 1.765 1.43 1200 150 3.3 1.2 15 0 -1 0 800 1.63 V 2.36 V 1.765 V 1200 mV 3. 3 V 150 µA -10 µA -150 -150 -150 Input and output parameters var y 1:1 with VCC. VEE can var y +0.925V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCC - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLKA, nPCLKB and PCLKA, nPCLKB is VCC + 0.3V. 853013AM www.icst.com/products/hiperclocks.html 3 Units µA REV. A OCTOBER 19, 2005 ICS853013 Integrated Circuit Systems, Inc. LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V Symbol Parameter VOH VOL -40°C 25°C 85°C Units Min Typ Max Min Typ Max Min Typ Max Output High Voltage; NOTE 1 1.375 1.475 1.58 1.425 1.495 1.57 1.495 1.53 1.565 V Output Low Voltage; NOTE 1 0.605 0.745 0.88 0.625 0.72 0.815 0.64 0.735 0.83 V VIH Input High Voltage(Single-Ended) 1.275 1.56 1.275 1.56 1.275 -0.83 V VIL Input Low Voltage(Single-Ended) 0.63 0.965 0.63 0.965 0.63 0.965 V VPP 150 1200 15 0 1200 150 1200 mV 2.5 1.2 2.5 1.2 2.5 V IIH Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 Input PCLKA, PCLKB High Current nPCLKA, nPCLKB 150 µA IIL Input Low Current VCMR PCLKA, PCLKB 800 1.2 800 150 -10 800 150 -10 -10 µA -150 -150 -150 nPCLKA, nPCLKB Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCC - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLKA, nPCLKB and PCLKA, nPCLKB is VCC + 0.3V. µA TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 5V; VEE = 0V Symbol -40°C Parameter 25°C Min Typ Max Min Typ 85°C Max Min Typ Max Units VOH Output High Voltage; NOTE 1 -1.125 -1.025 -0.92 -1.075 -1.005 -0.93 -1.005 -0.97 -0.935 V VOL Output Low Voltage; NOTE 1 -1.895 -1.755 -1.62 -1.875 -1.78 -1.685 -1.86 -1.765 -1.67 V VIH Input High Voltage(Single-Ended) -1.225 -0.94 -1.225 -0.94 -1.225 -0.94 V VIL Input Low Voltage(Single-Ended) -1.87 -1.535 -1.87 -1.535 -1.87 -1.535 V VPP 150 1200 150 1200 150 1200 mV 0 VEE+1.2V 0 VEE+1.2V 0 V IIH Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 Input PCLKA, PCLKB High Current nPCLKA, nPCLKB 150 µA IIL Input Low Current VCMR PCLKA, PCLKB 800 VEE+1.2V 800 150 -10 800 150 -10 -10 µA -150 -150 -150 nPCLKA, nPCLKB Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCC - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLKA, nPCLKB and PCLKA, nPCLKB is VCC + 0.3V. 853013AM www.icst.com/products/hiperclocks.html 4 µA REV. A OCTOBER 19, 2005 ICS853013 Integrated Circuit Systems, Inc. LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER TABLE 4E. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V Symbol Parameter VOH VOL -40°C 25°C 85°C Units Min Typ Max Min Typ Max Min Typ Max Output High Voltage; NOTE 1 -1.125 -1.025 -0.92 -1.075 -1.005 -0.93 -1.005 -0.97 -0.935 V Output Low Voltage; NOTE 1 -1.895 -1.755 -1.62 -1.875 -1.78 -1.685 -1.86 -1.765 -1.67 V VIH Input High Voltage(Single-Ended) -1.225 -0.94 -1.225 -0.94 -1.225 -0.94 V VIL Input Low Voltage(Single-Ended) -1.87 -1.535 -1.87 -1.535 -1.87 -1.535 V VPP 150 1200 150 1200 150 1200 mV 0 VEE+1.2V 0 VEE+1.2V 0 V IIH Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 Input PCLKA, PCLKB High Current nPCLKA, nPCLKB 150 µA IIL Input Low Current VCMR 800 VEE+1.2V PCLKA, PCLKB 800 150 800 150 -10 -10 -10 µA -150 -150 -150 nPCLKA, nPCLKB Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCC - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLKA, nPCLKA and PCLKB, nPCLKB is VCC + 0.3V. TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V Parameter fMAX Output Frequency Propagation Delay, Low-to-High; NOTE 1 Propagation Delay, High-to-Low; NOTE 1 Output Skew; NOTE 2, 4 tP HL tsk(o) VCC = 2.375V TO 5.25V; VEE = 0V -40°C Symbol tP LH OR Min Typ µA 25°C Max Min Typ >2 85°C Max Min Typ >2 Max >2 Units GH z 300 410 510 330 42 5 520 360 465 57 0 ps 300 410 51 0 330 42 5 520 360 465 57 0 ps 40 ps 40 40 tsk(odc) Output Duty Cycle Skew 40 40 40 ps tsk(pp) Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 250 250 250 ps tjit tR/tF Output Rise/Fall Time 20% to 80% 0.03 120 18 0 0.03 250 140 180 0.03 150 190 ps 230 ps All parameters tested ≤ 1GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 853013AM www.icst.com/products/hiperclocks.html 5 REV. A OCTOBER 19, 2005 ICS853013 Integrated Circuit Systems, Inc. LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER ADDITIVE PHASE JITTER the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in 0 -10 -20 Input/Output Additive Phase Jitter at 156.25MHz -30 = 0.03ps (typical) -40 SSB PHASE NOISE dBc/HZ -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de- 853013AM vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. www.icst.com/products/hiperclocks.html 6 REV. A OCTOBER 19, 2005 ICS853013 Integrated Circuit Systems, Inc. LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 2V VCC Qx SCOPE VCC LVPECL nPCLKA, nPCLKB nQx V VEE Cross Points PP V CMR PCLKA, PCLKB -0.375V to -3.25V V EE OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQx PART 1 Qx nQx nQy nQy Qx PART 2 Qy Qy tsk(pp) tsk(o) PART-TO-PART SKEW OUTPUT SKEW nPCLKA, nPCLKB nPCLKA, nPCLKB PCLKA, PCLKB PCLKA, PCLKB nQA0:nQA2, nQB0:nQB2, nQA0:nQA2, nQB0:nQB2, QA0:QA2, QB0:QB2, QA0:QA2, QB0:QB2, tpLH tpLH tpHL tpHL tsk(odc) = ⎥ tpLH - tpHL⎥ OUTPUT DUTY CYCLE SKEW 80% PROPAGATION DELAY 80% VSW I N G Clock Outputs 20% 20% tR tF OUTPUT RISE/FALL TIME 853013AM www.icst.com/products/hiperclocks.html 7 REV. A OCTOBER 19, 2005 ICS853013 Integrated Circuit Systems, Inc. LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K Single Ended Clock Input PCLK V_REF nPCLK C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: PCLK/nPCLK INPUT: For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from PCLK to ground. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. 853013AM www.icst.com/products/hiperclocks.html 8 REV. A OCTOBER 19, 2005 ICS853013 Integrated Circuit Systems, Inc. LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER LVPECL CLOCK INPUT INTERFACE suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLKx /nPCLKx accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS PCLKx/nPCLKx input driven by the most common driver types. The input interfaces 2.5V 3.3V 3.3V 3.3V 2.5V 3.3V R1 50 CML R3 120 R2 50 SSTL Zo = 50 Ohm R4 120 Zo = 60 Ohm PCLK PCLK Zo = 60 Ohm Zo = 50 Ohm nPCLK nPCLK HiPerClockS PCLK/nPCLK R1 120 FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A CML DRIVER HiPerClockS PCLK/nPCLK R2 120 FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 R4 125 3.3V Zo = 50 Ohm Zo = 50 Ohm C1 LVDS R3 1K R4 1K PCLK PCLK R5 100 Zo = 50 Ohm nPCLK LVPECL R1 84 C2 nPCLK Zo = 50 Ohm HiPerClockS Input R1 1K R2 84 FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER HiPerClockS PC L K /n PC LK R2 1K FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 3.3V 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 84 R4 84 PCLK nPCLK R5 100 - 200 R6 100 - 200 R1 125 HiPerClockS PCLK/nPCLK R2 125 FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE 853013AM www.icst.com/products/hiperclocks.html 9 REV. A OCTOBER 19, 2005 ICS853013 Integrated Circuit Systems, Inc. LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER TERMINATION FOR 3.3V LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. ance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched imped- 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 3A. LVPECL OUTPUT TERMINATION 853013AM 125Ω 84Ω FIGURE 3B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 10 REV. A OCTOBER 19, 2005 ICS853013 Integrated Circuit Systems, Inc. LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER TERMINATION FOR 2.5V LVPECL OUTPUT Figure 4A and Figure 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C. 2.5V VCC=2.5V 2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm R3 250 + Zo = 50 Ohm + Zo = 50 Ohm - Zo = 50 Ohm 2,5V LVPECL Driv er - R1 50 2,5V LVPECL Driv er R2 62.5 R2 50 R4 62.5 R3 18 FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE 853013AM www.icst.com/products/hiperclocks.html 11 REV. A OCTOBER 19, 2005 ICS853013 Integrated Circuit Systems, Inc. LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS853013. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS853013 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 5.25V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 5.25V * 60mA = 315mW Power (outputs)MAX = 30.94mW/Loaded Output pair If all outputs are loaded, the total power is 6 * 30.94mW = 185.64mW Total Power_MAX (5.25V, with all outputs switching) = 315mW + 185.64mW = 500.64mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.500W * 39.7°C/W = 104.85°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 20-PIN SOIC, FORCED CONVECTION θ by Velocity (Linear Feet per Minute) JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 83.2°C/W 46.2°C/W 65.7°C/W 39.7°C/W 57.5°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 853013AM www.icst.com/products/hiperclocks.html 12 REV. A OCTOBER 19, 2005 ICS853013 Integrated Circuit Systems, Inc. LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER 3. Calculations and Equations. LVPECL output driver circuit and termination are shown in Figure 5. VCCO Q1 VOUT RL 50 VCCO - 2V Figure 5. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CCO • For logic high, VOUT = V OH_MAX (V CC_MAX • CCO_MAX – 0.935V ) = 0.935V -V OH_MAX For logic low, VOUT = V OL_MAX (V -V Pd_H = [(V – (V CCO_MAX OH_MAX =V OL_MAX =V CCO_MAX – 1.67V ) = 1.67V CCO_MAX - 2V))/R ] * (V CCO_MAX L -V OH_MAX ) = [(2V - (V CCO_MAX -V OH_MAX ))/R ] * (V -V CCO _MAX L )= OH_MAX [(2V - 0.935V)/50Ω] * 0.935V = 19.92mW Pd_L = [(V OL_MAX – (V CCO_MAX - 2V))/R ] * (V L CCO_MAX -V OL_MAX ) = [(2V - (V CCO_MAX -V OL_MAX ))/R ] * (V L CCO_MAX -V )= OL_MAX [(2V - 1.67V)/50Ω] * 1.67V = 11.02mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW 853013AM www.icst.com/products/hiperclocks.html 13 REV. A OCTOBER 19, 2005 ICS853013 Integrated Circuit Systems, Inc. LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 20 LEAD SOIC θ by Velocity (Linear Feet per Minute) JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 83.2°C/W 46.2°C/W 65.7°C/W 39.7°C/W 57.5°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS853013 is: 226 Pin compatible with MC100LVEL13, MC100EL13 853013AM www.icst.com/products/hiperclocks.html 14 REV. A OCTOBER 19, 2005 ICS853013 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - Y SUFFIX FOR LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER 20 LEAD SOIC TABLE 7. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N Maximum 20 A -- 2.65 A1 0.10 -- A2 2.05 2.55 B 0.33 0.51 C 0.18 0.32 D 12.60 13.00 E 7.40 7.60 e H 1.27 BASIC 10.00 10.65 h 0.25 0.75 L 0.40 1.27 α 0° 8° Reference Document: JEDEC Publication 95, MS-013, MO-119 853013AM www.icst.com/products/hiperclocks.html 15 REV. A OCTOBER 19, 2005 ICS853013 Integrated Circuit Systems, Inc. LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS853013AM ICS853013AM 20 Lead SOIC tube -40°C to 85°C ICS853013AMT ICS853013AM 20 Lead SOIC 1000 tape & reel -40°C to 85°C ICS853013AMLF ICS853013AMLF 20 Lead "Lead-Free" SOIC tube -40°C to 85°C ICS853013AMLFT ICS853013AMLF 20 Lead "Lead-Free" SOIC 1000 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 853013AM www.icst.com/products/hiperclocks.html 16 REV. A OCTOBER 19, 2005 Integrated Circuit Systems, Inc. ICS853013 LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER REVISION HISTORY SHEET Rev A 853013AM Table T8 Page 8 16 Description of Change Added Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free marking. www.icst.com/products/hiperclocks.html 17 Date 10/19/05 REV. A OCTOBER 19, 2005