Integrated Circuit Systems, Inc. ICS853111-02 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS853111-02 is a low skew, high performance 1 - t o - 10 Differential-to-2.5V/3.3V HiPerClockS™ LVPECL/ECL Fanout Buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS853111-02 is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and par t-to-par t skew characteristics make the ICS85311102 ideal for those clock distribution applications demanding well defined perfor mance and repeatability. • Ten differential 2.5V/3.3V LVPECL / ECL outputs ICS • Two selectable differential input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum output frequency: 3.2GHz • Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nPCLK input • Output skew: 25ps (typical) • Part-to-part skew: 85ps (typical) • Propagation delay: 680ps (typical) • Jitter, RMS: < 0.03ps (typical) • LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V • ECL mode operating voltage supply range: VCC = 0V, VEE = -3.8V to -2.375V • -40°C to 85°C ambient operating temperature • Available in both standard and lead-free RoHS-compliant packages Q1 nQ1 Q7 nQ7 Q8 nQ8 nQ6 Q6 nQ5 Q5 nQ4 Q7 Q2 27 14 nQ7 nQ1 28 13 Q8 Q1 29 12 nQ8 nQ0 30 11 Q9 Q0 31 10 nQ9 VCCO 32 9 VCCO ICS853111-02 1 2 3 4 5 6 7 8 VEE Q6 nQ6 VCCO 15 nPCLK1 Q5 nQ5 16 26 PCLK1 Q4 nQ4 25 nQ2 VBB V BB Q3 nQ3 VCCO nPCLK0 Q2 nQ2 CLK_SEL Q4 24 23 22 21 20 19 18 17 PCLK0 1 Q3 PCLK1 nPCLK1 Q0 nQ0 VCC 0 CLK_SEL PCLK0 nPCLK0 PIN ASSIGNMENT nQ3 BLOCK DIAGRAM 32-Lead TQFP 7mm x 7mm x 1.0mm package body Y Package Top View Q9 nQ9 The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 853111AY-02 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006 1 ICS853111-02 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1 VCC Power Type Description 2 CLK_SEL Input Pulldown 3 PCLK0 Input Pulldown 4 nPCLK0 Input Pullup/Pulldown 5 VBB Output 6 PCLK1 Input Pulldown 7 nPCLK1 Input Pullup/Pulldown 8 VEE Power Core supply pin. Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs. When LOW, selects PCLK0, nPCLK0 inputs. LVCMOS / LVTTL interface levels. Non-inver ting differential clock input. Inver ting differential LVPECL clock input. VCC/2 default when left floating. Bias voltage. Non-inver ting differential clock input. Inver ting differential LVPECL clock input. VCC/2 default when left floating. Negative supply pin. 9, 16, 25, 32 VCCO Power Output supply pins. 10, 11 nQ9, Q9 Output Differential output pair. LVPECL interface levels. 12, 13 nQ8, Q8 Output Differential output pair. LVPECL interface levels. 14, 15 nQ7, Q7 Output Differential output pair. LVPECL interface levels. 17, 18 nQ6, Q6 Output Differential output pair. LVPECL interface levels. 19, 20 nQ5, Q5 Output Differential output pair. LVPECL interface levels. 21, 22 nQ4, Q4 Output Differential output pair. LVPECL interface levels. 23 , 2 4 nQ3, Q3 Output Differential output pair. LVPECL interface levels. 26, 27 nQ2, Q2 Output Differential output pair. LVPECL interface levels. 28, 29 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 30, 31 nQ0, Q0 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum RPULLDOWN Input Pulldown Resistor 75 kΩ RVCC/2 Pullup/Pulldown Resistors 50 kΩ PCLKx Outputs nPCLKx Q0:Q9 nQ0:Q9 Maximum Units TABLE 3B. CONTROL INPUT FUNCTION TABLE TABLE 3A. CLOCK INPUT FUNCTION TABLE Inputs Typical Input to Output Mode Polarity Inputs 0 1 LOW HIGH Differential to Differential Non Inver ting CLK_SEL 1 0 Biased; NOTE 1 Biased; NOTE 1 HIGH LOW Differential to Differential Non Inver ting 0 PCLK0, nPCLK0 LOW HIGH Single Ended to Differential Non Inver ting 1 PCLK1, nPCLK1 HIGH LOW Single Ended to Differential Non Inver ting 0 1 Selected Source Biased; 0 HIGH LOW Single Ended to Differential Inver ting NOTE 1 Biased; 1 LOW HIGH Single Ended to Differential Inver ting NOTE 1 NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels". 853111AY-02 www.icst.com/products/hiperclocks.html 2 REV. A JANUARY 10, 2006 Integrated Circuit Systems, Inc. ICS853111-02 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Negative Supply Voltage, VEE 4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage -4.6V (ECL mode, VCC = 0) Inputs, VI (LVPECL mode) -0.5V to VCC + 0.5 V Inputs, VI (ECL mode) 0.5V to VEE - 0.5V Supply Voltage, VCC Outputs, IO Continuous Current Surge Current VBB Sink/Source, IBB to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Character- 50mA 100mA istics is not implied. Exposure to absolute maximum rating conditions for extended periods may ± 0.5mA Operating Temperature Range, TA -40°C to +85°C affect product reliability. Storage Temperature, TSTG -65°C to 150°C Package Thermal Impedance, θJA 49.5°C/W (0 lfpm) (Junction-to-Ambient) TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375 TO 3.8V; VEE = 0V Symbol Parameter VCC Positive Supply Voltage IEE Power Supply Current Test Conditions Minimum Typical Maximum Units 2.375 3.3 3.8 V 85 mA TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V Symbol Parameter VOH -40°C 25°C 85°C Units Min Typ Max Min Typ Max Min Typ Max Output High Voltage; NOTE 1 2.175 2.275 2.38 2.225 2.295 2.37 2.295 2.33 2.365 V VOL Output Low Voltage; NOTE 1 1.405 1.545 1.68 1.425 1.52 1.615 1.44 1.535 1.63 V VIH Input High Voltage(Single-Ended) 2.075 2.36 2.075 2.36 2.075 2.36 V VIL Input Low Voltage(Single-Ended) 1.43 1.765 1.43 1.765 1.43 1.765 V VBB Output Voltage Reference; NOTE 2 1.86 1.98 1.86 1.98 1.86 1.98 V VPP Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 PCLK0, PCLK1 Input High Current nPCLK0, nPCLK1 150 1200 150 1200 150 1200 V 3.3 1. 2 3.3 1.2 3.3 V 150 µA VCMR IIH 800 1.2 800 150 800 150 PCLK0, PCLK1 -150 -150 -150 nPCLK0, nPCLK1 Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. NOTE 2: Single-ended input operation is limited VCC ≥ 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V. IIL 853111AY-02 Input Low Current www.icst.com/products/hiperclocks.html 3 µA REV. A JANUARY 10, 2006 Integrated Circuit Systems, Inc. ICS853111-02 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V Symbol Parameter -40°C Min 25°C Typ Max Min Typ 85°C Max Min Typ Max Units VOH Output High Voltage; NOTE 1 1.375 1.475 1.58 1.425 1.495 1.57 1.495 1.53 1.565 V VOL Output Low Voltage; NOTE 1 0.605 0.745 0.88 0.625 0.72 0.815 0.64 0.735 0.83 V VIH Input High Voltage(Single-Ended) 1.275 1.56 1.275 1.56 1.275 -0.8 V VIL Input Low Voltage(Single-Ended) 0.63 0.965 0.63 0.965 0.63 0.965 V VPP Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 PCLK0, PCLK1 Input High Current nPCLK0, nPCLK1 150 1200 150 1200 150 1200 V 2.5 1.2 2.5 1.2 2.5 V 150 µA VCMR IIH 800 1.2 800 150 800 150 PCLK0, PCLK1 -150 -150 -150 nPCLK0, nPCLK1 Input and output parameters var y 1:1 with VCC. VEE can var y +0.125V to -1.3V. NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V. IIL Input Low Current µA TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V Symbol Parameter VOH -40°C 25°C 85°C Units Min Typ Max Min Typ Max Min Typ Max Output High Voltage; NOTE 1 -1.125 -1.025 -0.92 -1.075 -1.005 -0.93 -1.005 -0.97 -0.935 V VOL Output Low Voltage; NOTE 1 -1.895 -1.755 -1.62 -1.875 -1.78 -1.685 -1.86 -1.765 -1.67 V VIH Input High Voltage(Single-Ended) -1.225 -0.94 -1.225 -0.94 -1.225 -0.94 V VIL Input Low Voltage(Single-Ended) Output Voltage Reference; NOTE 2 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input PCLK0, PCLK1 High Current nPCLK0, nPCLK1 -1.87 -1.535 -1.87 -1.535 -1.87 -1.535 V -1.486 -1.386 -1.486 -1.386 -1.486 -1.386 V 1200 150 1200 150 1200 V 0 VEE+1.2V 0 VEE+1.2V 0 V 150 µA VBB VPP VCMR IIH 150 800 VEE+1.2V 800 150 800 150 Input PCLK0, PCLK1 -150 -150 -150 Low Current nPCLK0, nPCLK1 Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. NOTE 2: Single-ended input operation is limited VCC ≥ 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V. IIL 853111AY-02 www.icst.com/products/hiperclocks.html 4 µA REV. A JANUARY 10, 2006 Integrated Circuit Systems, Inc. ICS853111-02 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V OR VCC = 2.375 TO 3.8V; VEE = 0V Symbol -40°C Parameter 25°C Min Typ Max 600 680 750 85°C Min Typ Max 650 725 790 Units Min Typ Max 3.2 GHz 690 790 890 ps fMAX Output Frequency t PD Propagation Delay; NOTE 1 t sk(o) Output Skew; NOTE 2, 4 25 37 25 37 25 37 ps t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section 85 225 85 225 85 225 ps t jit tR/tF Output Rise/Fall Time 3.2 20% to 80% 3.2 0.03 60 200 0.03 325 100 200 0.03 280 130 200 ps 270 ps All parameters are measured ≤ 1GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 853111AY-02 www.icst.com/products/hiperclocks.html 5 REV. A JANUARY 10, 2006 ICS853111-02 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER ADDITIVE PHASE JITTER the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in 0 -10 Additive Phase Jitter at 155.52MHz = 0.03ps (typical) -20 -30 -40 SSB PHASE NOISE dBc/HZ -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de- 853111AY-02 vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. www.icst.com/products/hiperclocks.html 6 REV. A JANUARY 10, 2006 Integrated Circuit Systems, Inc. ICS853111-02 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 2V VCC, VCCO Qx VCC SCOPE nCLK0, nCLK1 LVPECL V Cross Points PP VEE V CMR CLK0, CLK1 nQx V EE -0.375V to -1.8V 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQx PART 1 Qx nQx nQy nQy Qx PART 2 Qy Qy tsk(pp) tsk(o) PART-TO-PART SKEW OUTPUT SKEW nCLK0, nCLK1 80% 80% CLK0, CLK1 VSW I N G Clock Outputs nQ0:nQ9 20% 20% tR tF Q0:Q9 tPD OUTPUT RISE/FALL TIME 853111AY-02 PROPAGATION DELAY www.icst.com/products/hiperclocks.html 7 REV. A JANUARY 10, 2006 Integrated Circuit Systems, Inc. ICS853111-02 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS LEVELS Figure 2A shows an example of the differential input that can be wired to accept single ended LVCMOS levels. The reference voltage level VBB generated from the device is connected to the negative input. The C1 capacitor should be located as close as possible to the input pin. VCC R1 1K Single Ended Clock Input PCLK V_REF nPCLK C1 0.1u R2 1K FIGURE 2A. SINGLE ENDED LVCMOS SIGNAL DRIVING DIFFERENTIAL INPUT WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS Figure 2B shows an example of the differential input that can be wired to accept single ended LVPECL levels. The reference voltage level VBB generated from the device is connected to the negative input. The C1 capacitor should be located as close as possible to the input pin. VDD(or VCC) CLK_IN + VBB - C1 0.1uF FIGURE 2B. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT 853111AY-02 www.icst.com/products/hiperclocks.html 8 REV. A JANUARY 10, 2006 ICS853111-02 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER LVPECL CLOCK INPUT INTERFACE gested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces sug- 2.5V 3.3V 3.3V 3.3V 2.5V 3.3V R1 50 CML R3 120 R2 50 SSTL Zo = 50 Ohm R4 120 Zo = 60 Ohm PCLK PCLK Zo = 60 Ohm Zo = 50 Ohm nPCLK nPCLK HiPerClockS PCLK/nPCLK R1 120 FIGURE 3A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A CML DRIVER HiPerClockS PCLK/nPCLK R2 120 FIGURE 3B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY AN SSTL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 3.3V R4 125 Zo = 50 Ohm Zo = 50 Ohm C1 LVDS R3 1K R4 1K CLK PCLK R5 100 Zo = 50 Ohm nCLK LVPECL R1 84 C2 nPCLK Zo = 50 Ohm HiPerClockS Input R1 1K R2 84 FIGURE 3C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER HiPerClockS PCL K/n PC LK R2 1K FIGURE 3D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 3.3V 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 84 R4 84 PCLK nPCLK R5 100 - 200 R6 100 - 200 R1 125 HiPerClockS PCLK/nPCLK R2 125 FIGURE 3E. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE 853111AY-02 www.icst.com/products/hiperclocks.html 9 REV. A JANUARY 10, 2006 ICS853111-02 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS OUTPUTS: INPUTS: LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. PCLK/nPCLK INPUT: For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from PCLK to ground. TERMINATION FOR 3.3V LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. ance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched imped- 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 4A. LVPECL OUTPUT TERMINATION 853111AY-02 125Ω 84Ω FIGURE 4B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 10 REV. A JANUARY 10, 2006 Integrated Circuit Systems, Inc. TERMINATION FOR ICS853111-02 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER 2.5V LVPECL OUTPUT Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 5B can be eliminated and the termination is shown in Figure 5C. 2.5V 2.5V 2.5V VCCO=2.5V VCCO=2.5V R1 250 R3 250 Zo = 50 Ohm Zo = 50 Ohm + + Zo = 50 Ohm Zo = 50 Ohm - - 2,5V LVPECL Driv er 2,5V LVPECL Driv er R2 62.5 R1 50 R4 62.5 R2 50 R3 18 FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE 853111AY-02 www.icst.com/products/hiperclocks.html 11 REV. A JANUARY 10, 2006 ICS853111-02 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER SCHEMATIC EXAMPLE This application note provides general design guide using ICS853111-02 LVPECL buffer. Figure 6 shows a schematic example of the ICS853111-02 LVPECL clock buffer. In this ex- ample, the input is driven by an LVPECL driver. CLK_SEL is set at logic high to select PCLK0/nPCLK0 input. Zo = 50 + Zo = 50 - R2 50 VCC 32 31 30 29 28 27 26 25 C6 (Option) 0.1u Zo = 50 Ohm 1 2 3 4 5 6 7 8 Zo = 50 Ohm R4 1K R10 50 C8 (Option) 0.1u R11 50 Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6 9 10 11 12 13 14 15 16 R9 50 VCC CLK_SEL PCLK0 nPCLK0 VBB PCLK1 nPCLK1 VEE R3 50 24 23 22 21 20 19 18 17 VCCO nQ9 Q9 nQ8 Q8 nQ7 Q7 VCCO 3.3V LVPECL VCCO Q0 nQ0 Q1 nQ1 Q2 nQ2 VCCO VCC R1 50 U1 ICS853111 VCC Zo = 50 + VCC=3.3V Zo = 50 (U1-9) VCC (U1-16) (U1-25) (U1-32) - (U1-1) R8 50 C1 0.1uF C2 0.1uF C3 0.1uF C4 0.1uF R7 50 C5 0.1uF C7 (Option) 0.1u R13 50 FIGURE 6. EXAMPLE ICS853111-02 LVPECL CLOCK OUTPUT BUFFER SCHEMATIC THERMAL RELEASE PATH solder as shown in Figure 7. For further information, please refer to the Application Note on Surface Mount Assembly of Amkor’s Thermally /Electrically Enhance Leadframe Base Package, Amkor Technology. The expose metal pad provides heat transfer from the device to the P.C. board. The expose metal pad is ground pad connected to ground plane through thermal via. The exposed pad on the device to the exposed metal pad on the PCB is contacted through EXPOSED PAD SOLDER M ASK SOLDER SIGNAL TRACE SIGNAL TRACE GROUND PLANE Expose Metal Pad THERM AL VIA FIGURE 7. P.C. BOARD 853111AY-02 FOR (GROUND PAD) EXPOSED PAD THERMAL RELEASE PATH EXAMPLE www.icst.com/products/hiperclocks.html 12 REV. A JANUARY 10, 2006 Integrated Circuit Systems, Inc. ICS853111-02 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS853111-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS853111-02 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.8V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 85mA = 323mW Power (outputs)MAX = 30.94mW/Loaded Output pair If all outputs are loaded, the total power is 10 * 30.94mW = 309.4mW Total Power_MAX (3.8V, with all outputs switching) = 323mW + 309.4mW = 632.4mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43.8°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.632W * 43.8°C/W = 112.7°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 32-PIN TQFP, E-PAD, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 69.3°C/W 49.5°C/W 57.8°C/W 43.8°C/W 52.1°C/W 41.3°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 853111AY-02 www.icst.com/products/hiperclocks.html 13 REV. A JANUARY 10, 2006 ICS853111-02 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER 3. Calculations and Equations. LVPECL output driver circuit and termination are shown in Figure 8. VCCO Q1 VOUT RL 50 VCCO - 2V Figure 8. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CCO • For logic high, VOUT = V OH_MAX (V CC_MAX • -V OH_MAX OL_MAX -V Pd_H = [(V – (V CCO_MAX OH_MAX CCO_MAX – 0.935V ) = 0.935V For logic low, VOUT = V (V =V OL_MAX =V CCO_MAX – 1.67V ) = 1.67V CCO_MAX - 2V))/R ] * (V CCO_MAX L -V OH_MAX ) = [(2V - (V CCO_MAX -V OH_MAX ))/R ] * (V -V CCO _MAX L OH_MAX )= [(2V - 0.935V)/50Ω] * 0.935V = 19.92mW Pd_L = [(V OL_MAX – (V CCO_MAX - 2V))/R ] * (V L CCO_MAX -V OL_MAX ) = [(2V - (V CCO_MAX -V OL_MAX ))/R ] * (V L CCO_MAX -V OL_MAX )= [(2V - 1.67V)/50Ω] * 1.67V = 11.02mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW 853111AY-02 www.icst.com/products/hiperclocks.html 14 REV. A JANUARY 10, 2006 Integrated Circuit Systems, Inc. ICS853111-02 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 32 LEAD TQFP, E-PAD θ by Velocity (Linear Feet per Minute) JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 69.3°C/W 49.5°C/W 57.8°C/W 43.8°C/W 52.1°C/W 41.3°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS853111-02 is: 1340 Pin compatible with MC100EP111 and MC100LVEP111 853111AY-02 www.icst.com/products/hiperclocks.html 15 REV. A JANUARY 10, 2006 ICS853111-02 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TQFP PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD TQFP, E-PAD -HD VERSION HEAT SLUG DOWN TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS ABA-HD SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.20 A1 0.05 0.10 0.15 A2 0.95 1.0 1.05 b 0.30 0.35 0.40 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. D3 4.00 BASIC E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. E3 4.00 BASIC 0.80 BASIC e L 0.45 0.60 0.75 θ 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 853111AY-02 www.icst.com/products/hiperclocks.html 16 REV. A JANUARY 10, 2006 ICS853111-02 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS853111AY-02 ICS853111A02 32 lead, E-Pad TQFP tray -40°C to 85°C ICS853111AY-02T ICS853111A02 32 lead, E-Pad TQFP 1000 tape & reel -40°C to 85°C ICS853111AY-02LF ICS853111A02L 32 lead "Lead-Free," E-Pad TQFP tray -40°C to 85°C ICS853111AY-02LFT ICS853111A02L 32 lead "Lead-Free," E-Pad TQFP 1000 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 853111AY-02 www.icst.com/products/hiperclocks.html 17 REV. A JANUARY 10, 2006 Integrated Circuit Systems, Inc. ICS853111-02 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER REVISION HISTORY SHEET Rev A 853111AY-02 Table T9 Page 10 17 Description of Change Added Recommendations for Unused Input and Output Pins. Ordering Information Table - added Lead-Free marking. www.icst.com/products/hiperclocks.html 18 Date 1/10/06 REV. A JANUARY 10, 2006