SN65LBC173A, SN75LBC173A QUADRUPLE RS-485 DIFFERENTIAL LINE RECEIVERS SLLS456A – NOVEMBER 2000 – REVISED FEBRUARY 2001 Designed for TIA/EIA-485, TIA/EIA-422, and SN65LBC173A (Marked as 65LBC173A) SN75LBC173A (Marked as 75LBC173A) D or N PACKAGE (TOP VIEW) ISO 8482 Applications Signaling Rate† Exceeding 50 Mbps Fail-Safe in Bus Short-Circuit, Open-Circuit, and Idle-Bus Conditions ESD Protection on Bus Inputs Exceeds 6 kV Common-Mode Bus Input Range –7 V to 12 V Propagation Delay Times <16 ns Low Standby Power Consumption <20 µA Pin-Compatible Upgrade for AM26LS32, DS96F173, LTC488, and SN75173 1B 1A 1Y G 2Y 2A 2B GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 4B 4A 4Y G 3Y 3A 3B logic diagram G description G The SN65LBC173A and SN75LBC173A are quadruple differential line receivers with 3-state outputs, designed for TIA/EIA-485 (RS-485), TIA/EIA-422 (RS-422), and ISO 8482 (Euro RS-485) applications. These devices are optimized for balanced multipoint bus communication at data rates up to and exceeding 50 million bits per second. The transmission media may be twisted-pair cables, printed-circuit board traces, or backplanes. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. 1A 1B 1Y 2A 2B 2Y 3A 3B 3Y 4A 4B 4Y Each receiver operates over a wide range of positive and negative common-mode input voltages, and features ESD protection to 6 kV, making it suitable for high-speed multipoint data transmission applications in harsh environments. These devices are designed using LinBiCMOS, facilitating low power consumption and robustness. The G and G inputs provide enable control logic for either positive- or negative-logic enabling all four drivers. When disabled or powered off, the receiver inputs present a high-impedance to the bus for reduced system loading. The SN75LBC173A is characterized for operation over the temperature range of 0°C to 70°C. The SN65LBC173A is characterized over the temperature range from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinBiCMOS is a trademark of Texas Instruments. †The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second). Copyright 2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN65LBC173A, SN75LBC173A QUADRUPLE RS-485 DIFFERENTIAL LINE RECEIVERS SLLS456A – NOVEMBER 2000 – REVISED FEBRUARY 2001 FUNCTION TABLE (each receiver) ENABLES DIFFERENTIAL INPUTS A – B (VID) G G H X X L H X X L H X X L L H OPEN OPEN H X X L H X VID ≤ –0.2 02V –0.2 0 2 V < VID < –0.01 0 01 V 0 01 V ≤ VID –0.01 X Short circuit Open circuit H = high level, L = low level, ? = indeterminate OUTPUT Y L ? H Z H H X = irrelevant, Z = high impedance (off), AVAILABLE OPTIONS PACKAGE TA PLASTIC SMALL OUTLINE† (JEDEC MS-012) PLASTIC DUAL-IN-LINE (JEDEC MS-001) 0°C to 70°C SN75LBC173AD SN75LBC173AN – 40°C to 85°C SN65LBC173AD SN65LBC173AN † Add an R suffix for taped and reeled equivalent input and output schematic diagrams A Input B Input VCC 16 V 100 kΩ VCC 4 kΩ 18 kΩ Input Input 16 V G Input 4 kΩ 16 V 18 kΩ 4 kΩ 16 V G Input VCC 100 kΩ 4 kΩ VCC Y Output VCC 100 kΩ 1 kΩ Input 100 kΩ 8V 2 Input 8V 1 kΩ 5Ω 8V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 8V Output 8V SN65LBC173A, SN75LBC173A QUADRUPLE RS-485 DIFFERENTIAL LINE RECEIVERS SLLS456A – NOVEMBER 2000 – REVISED FEBRUARY 2001 absolute maximum ratings† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V Voltage range at any bus input (DC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10 V to 15 V Voltage range at any bus input (transient pulse through 100 Ω, see Figure 5) . . . . . . . . . . . . . . –30 V to 30 V Voltage input range at G and G, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Electrostatic discharge: Human body model (see Note 2): A and B to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 kV All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 kV Charged-device model (see Note 3): All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Power Dissipation Rating Table Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to GND, and are steady-state (unless otherwise specified). 2. Tested in accordance with JEDEC Standard 22, Test Method A114-A. 3. Tested in accordance with JEDEC Standard 22, Test Method C101. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR‡ ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING D 1080 mW 8.7 mW/°C 690 mW 560 mW N 1150 mW 9.2 mW/°C 736 mW 598 mW ‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. recommended operating conditions Supply voltage, VCC Voltage at any bus terminal High-level input voltage, VIH Low-level input voltage, VIL Output current Operating free free-air air temperature, temperature TA A, B G G G, MIN NOM MAX UNIT 4.75 5 5.25 V –7 12 V 2 VCC 0.8 V 0 Y –8 8 SN75LBC173A 0 70 SN65LBC173A –40 85 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 mA °C 3 SN65LBC173A, SN75LBC173A QUADRUPLE RS-485 DIFFERENTIAL LINE RECEIVERS SLLS456A – NOVEMBER 2000 – REVISED FEBRUARY 2001 electrical characteristics over recommended operating conditions PARAMETER TEST CONDITIONS VIT+ VIT– Positive-going differential input voltage threshold VHYS VIK Hysteresis voltage (VIT+ – VIT–) VOH High-level output voltage Negative-going differential input voltage threshold –7 7 V ≤ VCM ≤ 12 V (VCM = (VA + VB )/2) TYP† MAX –80 –10 –200 –120 II = –18 mA VID = 200 mV, IOH = –8 mA –1.5 –0.8 2.7 4.8 mV V See Figure 1 VOL Low-level output voltage VID = –200 mV, IOL = 8 mA IOZ High-impedance-state output current VO = 0 V to VCC II Line input current Other input in ut at 0 V, VCC = 0 V or 5 V IIH IIL High-level input current RI Input resistance ICC Supply current V 0.2 –1 VI = 12 V VI = –7 V 0.4 1 A, B inputs VID = 5 V No load µA 0.9 mA –0.7 100 Enable inputs G, G G UNIT mV 40 Input clamp voltage Low-level input current MIN µA –100 µA 12 kΩ 20 µA 11 16 mA TYP† MAX G at 0 V, G at VCC G at VCC, G at 0 V † All typical values are at VCC = 5 V and 25°C. switching characteristics over recommended operating conditions PARAMETER TEST CONDITIONS MIN UNIT tr tf Output rise time 2 4 ns Output fall time 2 4 ns tPLH tPHL Propagation delay time, low-to-high level output 9 12 16 ns 9 12 16 ns tPZH tPHZ Propagation delay time, high-impedance to high-level output 27 38 ns tPZL tPLZ Propagation delay time, high-impedance to low level output tsk(p) tsk(o) Pulse skew (| (tPLH – tPHL) |) VID = –3 3 V to 3 V V, See Figure 2 Propagation delay time, high-to-low level output Propagation delay time, high-level to high-impedance output Propagation delay time, low-level to high-impedance output See Figure 3 See Figure 4 Output skew (see Note 4) 7 16 ns 29 38 ns 12 16 ns 0.2 1 ns 2 ns tsk(pp) Part-to-part skew (see Note 5) 2 ns † All typical values are at VCC = 5 V and 25°C. NOTES: 4. Outputs skew (tsk(o)) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs connected together. 5. Part-to-part skew (tsk(pp)) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same input signals, the same supply voltages, at the same temperature, and have identical packages and test circuits. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LBC173A, SN75LBC173A QUADRUPLE RS-485 DIFFERENTIAL LINE RECEIVERS SLLS456A – NOVEMBER 2000 – REVISED FEBRUARY 2001 PARAMETER MEASUREMENT INFORMATION VA IO VID VB VO Figure 1. Voltage and Current Definitions 50 Ω Generator 3V Input B A 1.5 V Y 1.5 V 0V Input A B tPLH CL = 15 pF (Includes Probe and Jig Capacitance) 50 Ω Generator tPHL 1.5 V Output Y 90% 10% tr VOH 90% 10% VOL tf Generators: PRR = 1 MHz, 50% Duty Cycle, tr <6 ns, Zo = 50 Ω Figure 2. Switching Test Circuit and Waveforms VCC 1.5 V A 1 kΩ Y B CL = 15 pF (Includes Probe and Jig Capacitance) 3V G 1.5 V 0V tPHZ tPZH G Generator 50 Ω G Y VCC 1.5 V 1.5 V VOH VOH –0.5 V GND Generators: PRR = 1 MHz, 50% Duty Cycle, tr <6 ns, Zo = 50 Ω Figure 3. Test Circuit Waveforms, tPZH and tPHZ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN65LBC173A, SN75LBC173A QUADRUPLE RS-485 DIFFERENTIAL LINE RECEIVERS SLLS456A – NOVEMBER 2000 – REVISED FEBRUARY 2001 PARAMETER MEASUREMENT INFORMATION VCC A –1.5 V Y 1 kΩ B CL = 15 pF (Includes Probe and Jig Capacitance) 3V G 1.5 V 1.5 V 0V tPLZ tPZL G Generator 50 Ω VCC G Y 1.5 V VCC VOL + 0.5 V VOL Generators: PRR = 1 MHz, 50% Duty Cycle, tr <6 ns, Zo = 50 Ω Figure 4. Test Circuit Waveforms, tPZL and tPLZ 100 Ω VTEST 0V Pulse Generator, 15 µs Duration, 1% Duty Cycle 15 µs 1.5 ms Figure 5. Test Circuit and Waveform, Transient Over-Voltage Test 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VTEST SN65LBC173A, SN75LBC173A QUADRUPLE RS-485 DIFFERENTIAL LINE RECEIVERS SLLS456A – NOVEMBER 2000 – REVISED FEBRUARY 2001 TYPICAL CHARACTERISTICS BUS INPUT CURRENT vs BUS INPUT VOLTAGE OUTPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE 800 6 VCC = 5 V TA = 25°C 600 5 400 VO – Output Voltage – V Bus Input Current –µ A VCC = 0 V VCC = 5 V 200 0 –200 VIC = –7 V VIC = 0 V VIC = 12 V 4 VIC = –7 V VIC = 0 V VIC = 12 V 3 2 1 –400 –600 –10 –5 0 5 10 0 –150 15 –100 Bus Input Voltage – V –50 0 50 Differential Input Voltage – mV Figure 6 Figure 7 SUPPLY CURRENT vs SIGNALING RATE (ALL FOUR CHANNELS) PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 60 13.5 Propagation Delay Time – ns I CC – Supply Current – mA 50 40 VCC = 5.25 V, CL = 15 pF 30 VCC = 5 V, CL = 15 pF VCC = 4.75 V, CL = 15 pF 20 10 13 tPLH 12.5 tPHL 12 11.5 VCC = 5 V, No Load 0 1 10 100 Signaling Rate (All Four Channels) – Mbps 11 –40 –20 0 20 40 60 80 TA – Free-Air Temperature – °C Figure 8 Figure 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN65LBC173A, SN75LBC173A QUADRUPLE RS-485 DIFFERENTIAL LINE RECEIVERS SLLS456A – NOVEMBER 2000 – REVISED FEBRUARY 2001 TYPICAL CHARACTERISTICS 500 mV A, B –500 mV 20 ns 5V Y 0V Figure 10. Receiver Inputs and Outputs, 50 Mbps Signaling Rate 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LBC173A, SN75LBC173A QUADRUPLE RS-485 DIFFERENTIAL LINE RECEIVERS SLLS456A – NOVEMBER 2000 – REVISED FEBRUARY 2001 APPLICATION INFORMATION TMS320F243 DSP (Controller) SN65LBC174A SN65LBC173A SPISIMO TMS320F241 DSP (Embedded Application) SPISIMO IOPA1 (Enable) SPISTE SPISTE IOPA1 IOPA2 SPICLK SPICLK IOPA2 (Enable) IOPA0 (Handshake /Status) IOPA0 SPISOMI SPISOMI Figure 11. Typical Application Circuit, DSP-to-DSP Link via Serial Peripheral Interface Motion Controller Servo Drive SN65LBC173A Encoder Phase A Encoder Phase B Encoder Index Status Bit Figure 12. Typical Application Circuit, High-Speed Servomotor Encoder Interface POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN65LBC173A, SN75LBC173A QUADRUPLE RS-485 DIFFERENTIAL LINE RECEIVERS SLLS456A – NOVEMBER 2000 – REVISED FEBRUARY 2001 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0°–8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047 / D 10/96 NOTES: A. B. C. D. 10 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LBC173A, SN75LBC173A QUADRUPLE RS-485 DIFFERENTIAL LINE RECEIVERS SLLS456A – NOVEMBER 2000 – REVISED FEBRUARY 2001 MECHANICAL DATA N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 16 PINS SHOWN PINS ** 14 16 18 20 A MAX 0.775 (19,69) 0.775 (19,69) 0.920 (23,37) 0.975 (24,77) A MIN 0.745 (18,92) 0.745 (18,92) 0.850 (21,59) 0.940 (23,88) DIM A 16 9 0.260 (6,60) 0.240 (6,10) 1 8 0.070 (1,78) MAX 0.035 (0,89) MAX 0.325 (8,26) 0.300 (7,62) 0.020 (0,51) MIN 0.015 (0,38) Gauge Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.430 (10,92) MAX 0.010 (0,25) M 14/18 PIN ONLY 4040049/D 02/00 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 (20-pin package is shorter than MS-001). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. 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Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated TI product or service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use. Resale of TI’s products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use. Also see: Standard Terms and Conditions of Sale for Semiconductor Products. www.ti.com/sc/docs/stdterms.htm Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2001, Texas Instruments Incorporated