UC1843-HiRel www.ti.com .................................................................................................................................................. SLUS896A – AUGUST 2009 – REVISED AUGUST 2009 CURRENT MODE PWM CONTROLLER (KNOWN GOOD DIE) FEATURES 1 • • • • • • • • • • • • • DESCRIPTION –55°C to 125°C Known Good Die Controlled Baseline Optimized For Off-line and DC-to-DC Converters Low Start-Up Current (<1 mA) Automatic Feed Forward Compensation Pulse-by-Pulse Current Limiting Enhanced Load Response Characteristics Under-Voltage Lockout With Hysteresis Double Pulse Suppression High Current Totem Pole Output Internally Trimmed Bandgap Reference 500-kHz Operation Low RO Error Amp The UC1843 family of control devices provides the necessary features to implement off-line or dc-to-dc fixed frequency current mode control schemes with a minimal external parts count. Internally implemented circuits include under-voltage lockout featuring start up current less than 1 mA, a precision reference trimmed for accuracy at the error amp input, logic to insure latched operation, a PWM comparator which also provides current limit control, and a totem pole output stage designed to source or sink high peak current. The output stage, suitable for driving N-Channel MOSFETs, is low in the off state. The under-voltage lockout threshold is 8.4 V and maximum duty cycle range is around 100%. xxx BLOCK DIAGRAM Vcc 7 12 UVLO 34 V S/R GROUND 5 9 5V REF 8 14 VREF 5V 50 mA 2.50 V Internal BIAS VREF Good Logic 4 7 RT/CT OSC 2 COMP 1 CURRENT SENSE 3 6 10 OUTPUT T Error Amp VFB 7 11 VC S 2R 3 R R 1V 1 PWM LATCH CURRENT SENSE COMPARATOR 5 8 POWER GROUND 5 A/B ORDERING INFORMATION (1) (1) (2) TA PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING –55°C to 125°C KGD UC1843KGD1 NA For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated UC1843-HiRel SLUS896A – AUGUST 2009 – REVISED AUGUST 2009 .................................................................................................................................................. www.ti.com BARE DIE INFORMATION DIE THICKNESS BACKSIDE FINISH BACKSIDE POTENTIAL BOND PAD METALLIZATION COMPOSITION 15 mils. Silicon with backgrind GND Al-Si-Cu (0.5%) a c b d Origin BOND PAD COORDINATES (in Mils) 2 DESCRIPTION PAD NUMBER a b c d COMP 1 78.70 63.40 82.90 67.60 VFB 2 70.60 63.40 74.80 67.60 ISENSE 3 39.40 63.40 43.60 67.60 RT/CT 4 18.60 61.20 22.60 65.60 GROUND 5 17.80 11.70 22.00 15.90 GROUND 6 17.40 3.90 21.80 8.10 OUTPUT 7 32.60 6.40 36.80 10.60 VCC 8 47.50 6.40 51.70 10.60 VCC 9 54.60 6.40 58.80 10.60 VREF 10 68.70 6.40 72.90 10.60 NC TESTPAD 87.10 6.30 90.80 10.30 NC TESTPAD 87.10 12.60 90.80 16.60 NC TESTPAD 87.10 18.00 90.80 22.00 NC TESTPAD 87.10 24.30 90.80 28.30 NC TESTPAD 87.10 30.60 90.80 34.60 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UC1843-HiRel UC1843-HiRel ½ ½ 1803 mm ½ www.ti.com .................................................................................................................................................. SLUS896A – AUGUST 2009 – REVISED AUGUST 2009 COMP VREF VFB VCC ISENSE 2438 mm VCC OUTPUT RT/CT GROUND ½ GROUND ABSOLUTE MAXIMUM RATINGS UNIT Supply voltage Low impedance source ICC < 30 mA Output current 30 V Self Limiting ±1 A 5 µJ Output energy (capacitive load) Analog inputs (Pins 2, 3) –0.3 V to 6.3 V Error amp output sink current 10 mA Storage temperature range –65°C to 150°C Junction temperature range –55°C to 150°C Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UC1843-HiRel 3 UC1843-HiRel SLUS896A – AUGUST 2009 – REVISED AUGUST 2009 .................................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for –55°C ≤ TA ≤ 125°C; VCC = 15 V (1); RT = 10 kW; CT = 3.3 nF,TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REFERENCE SECTION Output Voltage TJ = 25°C, IO = 1 mA Line Regulation Load Regulation Temperature Stability See 4.95 5.00 5.05 12 ≤ VIN ≤ 25 V 6 20 1 ≤ I0 ≤ 20 mA 6 25 0.2 0.4 (2) (3) (2) Total Output Variation Line, load, tempature Output Noise Voltage 10 Hz≤ f ≤ 10 kHz, TJ = 25°C Long Term Stability TA = 125°C, 1000 Hrs 4.9 (2) –30 mV mV/°C V µV 50 (2) Output Short Circuit 5.1 V 5 25 mV –100 –180 mA 52 57 kHz 0.2% 1% OSCILLATOR SECTION Initial Accuracy TJ = 25°C (4) Voltage Stability 12 ≤ VCC ≤ 25 V Temperature Stability TMIN ≤ TA ≤ TMAX Amplitude VPIN 4 peak-to-peak 47 (2) 5% (2) 1.7 V ERROR AMP SECTION Input Voltage VPIN 1 = 2.5 V 2.45 Input Bias Current AVOL 2 ≤ VO ≤ 4 V 65 (2) Unity Gain Bandwidth TJ = 25°C PSRR 12 ≤ VCC ≤ 25 V Output Sink Current VPIN 2 = 2.7 V, VPIN 1 = 1.1 V Output Source Current VPIN 2 = 2.3 V, VPIN 1 = 5 V VOUT High VPIN 2 = 2.3 V, RL = 15 kΩ to ground VOUT Low VPIN 2 = 2.7 V, RL = 15 kΩ to Pin 8 Gain See (5) (6) Maximum Input Signal VPIN 1 PSRR 12 ≤ VCC ≤ 25 V 2.50 2.55 V –0.3 –1 µA 90 dB 0.7 1 MHz 60 70 dB 2 6 –0.5 –0.8 5 mA 6 0.7 1.1 2.85 3 3.15 0.9 1 1.1 V CURRENT SENSE SECTION =5V (5) VPIN 3 V (2) (5) 70 –2 –10 µA (2) 150 300 ns 0.1 0.4 1.5 2.2 Input Bias Current Delay to Output V/V = 0 V to 2 V dB OUTPUT SECTION Output Low Level Output High Level ISINK = 20 mA ISINK = 200 mA ISOURCE = 20 mA ISOURCE = 200 mA (2) Rise Time TJ = 25°C, CL = 1 nF Fall Time TJ = 25°C, CL = 1nF (2) (1) (2) (3) (4) (5) (6) 4 13 13.5 12 13.5 50 150 50 150 V ns Adjust VCC above the start threshold before setting at 15 V. These parameters, although specified, are not 100% tested in production. Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation: V (max) * VREF (min) Temp Stability + REF TJ(max) * TJ (min) VREF(max) and VREF(min) are the maximum and minimum reference voltages measured over the appropriate temperature range. Note that the extremes in voltage do not necessarily occur at the extremes in temperature. Output frequency equals oscillator frequency. Parameter measured at trip point of latch with VPIN 2 = 0. A + DVPIN 1 , 0 v VPIN 3 v 0.8 V DVPIN 3 Gain defined as: Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UC1843-HiRel UC1843-HiRel www.ti.com .................................................................................................................................................. SLUS896A – AUGUST 2009 – REVISED AUGUST 2009 ELECTRICAL CHARACTERISTICS (continued) Unless otherwise stated, these specifications apply for –55°C ≤ TA ≤ 125°C; VCC = 15 V; RT = 10 kW; CT = 3.3 nF,TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT UNDER-VOLTAGE LOCKOUT SECTION Start Threshold 7.8 8.4 9.0 Min. Operating Voltage After Turn On 7.0 7.6 8.2 95% 97% 100% V PWM SECTION Maximum Duty Cycle Minimum Duty Cycle 0% TOTAL STANDBY CURRENT Start-Up Current Operating Supply Current VPIN 2 = VPIN 3 = 0 V VCC Zener Voltager ICC = 25 mA 30 0.5 1 11 17 mA 34 V ERROR AMP CONFIGURATION Error amp can source or sink up to 0.5 mA. 2.5 V 0.5 mA + VFB ZI _ 2 COMP ZF 1 UNDER-VOLTAGE LOCKOUT During under-voltage lock-out, the output drive is biased to sink minor amounts of current. Pin 6 should be shunted to ground with a bleeder resistor to prevent activating the power switch with extraneous leakage currents. VCC VCC 7 ON/OFF Command to REST of IC <17 mA VON 8.4 V VOFF 7.6 V <1 mA VCC VOFF VON Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UC1843-HiRel 5 UC1843-HiRel SLUS896A – AUGUST 2009 – REVISED AUGUST 2009 .................................................................................................................................................. www.ti.com CURRENT SENSE CIRCUIT A small RC filter may be required to suppress switch transients. ERROR AMP 2R IS R 1 R CURRENT SENSE 3 RS 1V COMP CURRENT SENSE COMPARATOR C GND 5 5 Peak Current (IS ) is Determined By The Formula ,1.0 V ISMAX RS OSCILLATOR SECTION 8 30 4 CT GROUND 100 10 3 td - ms RT/CT Timing Resistance vs Frequency Deadtime vs CT (RT >5 k ) RT RT - (k W ) VREF 5 1 0.3 1 2.2 4.7 1.72 For RT> 5 K f ~ RTCT 10 22 CT - nF 47 30 10 3 100 100 1k 10 k 100 k 1M f - Frequenc y - Hz OUTPUT SATURATION CHARACTERISTICS 4 VCC = 15 V Saturation Voltage - V 3 TA = 25°C TA = -55 °C 2 SOURCE SAT (VCC - VOH) 1 SINK SAT (VOL) 0 .01 .02 .03 .04 .05 .07 .1 .2 .3 .4 .5 .7 1 Output Current, Source or Sink - A 6 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UC1843-HiRel UC1843-HiRel www.ti.com .................................................................................................................................................. SLUS896A – AUGUST 2009 – REVISED AUGUST 2009 80 0 60 -45 θ 40 -90 20 -135 Phase Margin - ° Voltage Gain - dB ERROR AMPLIFIER OPEN-LOOP FREQUENCY RESPONSE Av -180 0 10 100 1k 10 k 100 k 1M 10 M f - Frequenc y - Hz OPEN-LOOP LABORATORY FIXTURE High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypas capacitors should be conected close to pin 5 in a single point ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3. VREF R1 2N2222 4.7 kW A VCC 100 kW 1 kW ERROR AMP ADJUST 5 kW 4.7 kW ISENSE ADJUST 1 COMP 2 VFB 3 ISENSE OUTPUT 6 4 RT / CT GROUND 5 VREF 8 0.1 mF VCC 7 0.1 mF 1 kW 1 W OUTPUT GROUND CT SHUTDOWN TECHNIQUES Shutdown of the UC1843 can be accomplished by two methods; either raise pin 3 above 1 V or pull pin 1 below a voltage two diode drops above ground. Either method causses the output of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pin 1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SCR which will be reset by cycling VCC below the lower UVLO threshold. At this pint the reference turns off, allowing the SCR to reset. 1 kW 8 VREF 3 ISENSE 1 COMP SHUTDOWN 330 W 500 W SHUTDOWN To Current SENSE RESISTOR Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UC1843-HiRel 7 UC1843-HiRel SLUS896A – AUGUST 2009 – REVISED AUGUST 2009 .................................................................................................................................................. www.ti.com OFFLINE FLYBACK REGULATOR T1 R1 5 Ω1W 117 VAC D6 U9D946 L1 +6 V VARO VM 68 C9 3300 pF 600 V R12 4.7 kΩ 2W C1 250 mF 250 V R2 56 kΩ 2W C10 N5 4700 mF 10 V NP C11 4700 mF 10 V COM D4 1N3613 D7 UF81002 +12 V R4 4.7 kΩ D2 1N3612 R3 20 kΩ D3 1N3612 C12 2200 mF 16 V N12 N12 2 C2 100 mF 25 V 7 R5 150 kΩ R9 68 Ω 3W C3 22 mF C4 47 mF 25 V -12 V NC D8 UES1002 1 C14 UC1843M R7 22 Ω 100 pF 8 Q1 UFN833 6 R8 R6 10 kΩ C5 0.01 mF ±12 V COM C13 2200 mF 16 V C8 680 pF 600 V 3 4 5 1 kΩ USD1120 R13 20 kΩ C7 470 pF C6 0.0022 mF R10 0.55 Ω 1W D8 1N3613 R11 2.7 kΩ 2W Power Supply Specifications 1. Input Voltages a. 5VAC to 130VA (50 Hz/60 Hz) 2. Line Isolation: 3750 V 3. Switchng Frequency: 40 kHz 4. Efficiency at Full Load 70% 5. Output Voltage: a. +5 V, ±5%; 1A to 4A load Ripple voltage: 50 mV P-P Max b. +12 V, ±3%; 0.1A to 0.3A load Ripple voltage: 100 mV P-P Max c. –12 V, ±3%; 0.1A to 0.3A load Ripple voltage: 100 mV P-P Max SLOPE COMPENSATION A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for converters requiring duty cycles over 50%. VREF 8 0.1 mF RT / CT RT 4 CT UC1843M ISENSE R1 R2 ISENSE 3 C 8 Submit Documentation Feedback RSENSE Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UC1843-HiRel PACKAGE OPTION ADDENDUM www.ti.com 3-Jul-2010 PACKAGING INFORMATION Orderable Device UC1843MKGD1 Status (1) ACTIVE Package Type Package Drawing XCEPT KGD Pins Package Qty 0 100 Eco Plan TBD (2) Lead/ Ball Finish Call TI MSL Peak Temp (3) Samples (Requires Login) N / A for Pkg Type Contact TI Distributor or Sales Office (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. 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