TI TM497MBK36H

TM497MBK36H, TM497MBK36I
4194304 BY 36-BIT
DYNAMIC RAM MODULES
SMMS676 – MARCH 1997
D
D
D
D
D
D
D
D
D
D
Organization . . . 4 194 304 × 36
Single 5-V Power Supply (±10% Tolerance)
3-State Output
Performance Ranges:
ACCESS
TIME
tRAC
72-Pin Single-In-Line Memory Module
(SIMM) for Use With Sockets
Uses Eight 16M-bit Dynamic RAMs
(DRAMs) in Plastic Small-Outline J-Lead
(SOJ) Packages and Four 4M-bit DRAMs in
Plastic SOJ Packages
(MAX)
ACCESS ACCESS READ
TIME
TIME
OR
tCAC
tAA
WRITE
CYCLE
(MAX)
(MAX)
(MIN)
’497MBK36H / I-60 60 ns
’497MBK36H / I-70 70 ns
’497MBK36H / I-80 80 ns
D
D
Long Refresh Period . . . 32 ms
(2 048 Cycles)†
All Inputs, Outputs, and Clocks are Fully
TTL Compatible
D
D
Common CAS Control for Nine Common
Data-In and Data-Out Lines in Four Blocks
Separate RAS Control for Eighteen Data-In
and Data-Out Lines in Two Blocks
D
15 ns
18 ns
20 ns
30 ns
35 ns
40 ns
110 ns
130 ns
150 ns
Low Power Dissipation
Operating Free-Air Temperature
Range . . . 0°C to 70°C
Presence Detect
Gold-Tabbed Version Available
TM497MBK36H
Tin-Lead (Solder) Tabbed Version
Available: TM497MBK36I
description
The TM497MBK36H / I is a 144M-bit dynamic random-access memory (DRAM) device organized as four times
4 194 304 × 9 (bit 9 generally is used for parity) in a 72-pin leadless single-in-line memory module (SIMM). The
SIMM is composed of eight TMS417400ADJ, 4 194 304 × 4-bit DRAMs in 24/26-lead plastic SOJ packages,
and four TMS44100DJ, 4 194 304 × 1-bit DRAMs in 20/26-lead plastic SOJ packages mounted on a substrate
with decoupling capacitors. TMS417400ADJ and TMS44100DJ are described in the TMS417400A and
TMS44100 data sheets (literature numbers SMKS889 and SMHS561, respectively).
The TM497MBK36H / I is available in a double-sided, BK, leadless module for use with sockets. The
TM497MBK36H/ I features RAS access times of 60, 70, and 80 ns. This device is characterized for operation
from 0°C to 70°C.
operation
The TM497MBK36H / I operates as eight TMS417400ADJs and four TMS44100DJs connected as shown in the
functional block diagram and Table 1. See the TMS417400A and TMS44100 data sheets for details of operation.
The common I/O feature dictates the use of early write cycles to prevent contention on D and Q.
Table 1. Connection Table
DATA BLOCK
RASx
CASx
DQ0 – DQ8
RAS0
CAS0
DQ9 – DQ17
RAS0
CAS1
DQ18 – DQ26
RAS2
CAS2
DQ27 – DQ35
RAS2
CAS3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† A0 – A9 address lines must be refreshed every 16 ms.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TM497MBK36H, TM497MBK36I
4194304 BY 36-BIT
DYNAMIC RAM MODULES
SMMS676 – MARCH 1997
BK SINGLE-IN-LINE PACKAGE
( TOP VIEW )
2
VSS
DQ0
DQ18
DQ1
DQ19
DQ2
DQ20
DQ3
DQ21
VCC
NC
A0
A1
A2
A3
A4
A5
A6
A10
DQ4
DQ22
DQ5
DQ23
DQ6
DQ24
DQ7
DQ25
A7
NC
VCC
A8
A9
NC
RAS2
DQ26
DQ8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
DQ17
DQ35
VSS
CAS0
CAS2
CAS3
CAS1
RAS0
NC
NC
W
NC
DQ9
DQ27
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
DQ13
DQ31
VCC
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
NC
PD1
PD2
PD3
PD4
NC
VSS
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
(SIDE VIEW )
PIN NOMENCLATURE
A0 – A10
CAS0 – CAS3
DQ0 – DQ7, DQ9 – DQ16,
DQ18 – DQ25, DQ27 – DQ34
DQ8, DQ17, DQ26, DQ35
NC
PD1 – PD4
RAS0, RAS2
VCC
VSS
W
Address Inputs
Column-Address Strobe
Data Input/Output
Parity
No Connection
Presence Detect
Row-Address Strobe
5-V Supply
Ground
Write Enable
PRESENCE DETECT
SIGNAL
(PIN)
PD1
(67)
PD2
(68)
70 ns
VSS
VSS
60 ns
VSS
NC
80 ns
TM497MBK36H/I
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
PD3
(69)
PD4
(70)
NC
NC
NC
VSS
NC
VSS
NC
NC
TM497MBK36H, TM497MBK36I
4194304 BY 36-BIT
DYNAMIC RAM MODULES
SMMS676 – MARCH 1997
refresh
The refresh period is extended to 32 ms and, during this period, each of the 2 048 rows must be strobed with
RAS to retain data. Address line A10 must be used as the most significant refresh-address line (lowest
frequency) to ensure correct refresh for both TMS417400A and TMS44100. A0– A9 address lines must be
refreshed every 16 ms as required by the TMS44100 DRAM. CAS can remain high during the refresh sequence
to conserve power.
power up
To achieve proper operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is
required after full VCC level is achieved. These eight initialization cycles need to include at least one refresh
(RAS-only or CAS-before-RAS [CBR]) cycle.
single-in-line memory module and components
PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for TM497MBK36H: Nickel plate and gold plate over copper
Contact area for TM497MBK36I: Nickel plate and tin-lead over copper
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3
A0 – A10
11
RAS0
RAS2
W
CAS0
CAS1
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
11
11
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
4M × 1
A0 – A10
RAS
W
CAS
D
Q
11
DQ0 –
DQ3
11
DQ4 –
DQ7
11
DQ8
CAS3
CAS2
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
4M × 1
A0 – A10
RAS
W
CAS
D
Q
11
DQ9 –
DQ12
11
DQ13 –
DQ16
11
DQ17
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
4M × 1
A0 – A10
RAS
W
CAS
D
Q
11
DQ18 –
DQ21
11
DQ22 –
DQ25
11
DQ26
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
DQ27 –
DQ30
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
DQ31 –
DQ34
4M × 1
A0 – A10
RAS
W
CAS
D
Q
DQ35
Template Release Date: 7–11–94
TM497MBK36H, TM497MBK36I
4194304 BY 36-BIT
DYNAMIC RAM MODULES
SMMS676 – MARCH 1997
4
functional block diagram
TM497MBK36H, TM497MBK36I
4194304 BY 36-BIT
DYNAMIC RAM MODULES
SMMS676 – MARCH 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Input voltage range (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 W
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
5
UNIT
VCC
VIH
Supply voltage
4.5
5.5
V
High-level input voltage
2.4
6.5
V
VIL
TA
Low-level input voltage (see Note 2)
–1
0.8
V
0
70
°C
Operating free-air temperature
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output
voltage
IOH = – 5 mA
VOL
Low-level output
voltage
IOL = 4.2 mA
II
Input current
(leakage)
VCC = 5.5 V,
VI = 0 V to 6.5 V,
All other pins = 0 V to VCC
IO
Output current
(leakage)
VCC = 5.5 V,
CAS high
ICC1
Read- or write-cycle
current (see Note 3)
VCC = 5.5 V,
ICC2
Standby current
’497MBK36H / I-60
MIN
’497MBK36H / I-70
MAX
2.4
MIN
MAX
2.4
’497MBK36H / I-80
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
± 120
± 120
± 120
µA
VO = 0 V to VCC,
± 10
± 10
± 10
µA
Minimum cycle
1300
1160
1040
mA
VIH = 2.4 V (TTL),
After one memory cycle,
RAS and CAS high
24
24
24
mA
VIH = VCC – 0.2 V (CMOS),
After one memory cycle,
RAS and CAS high
12
12
12
mA
1300
1160
1040
mA
920
800
680
mA
ICC3
Average refresh
current (RAS-only
or CBR)
(see Note 3)
VCC = 5.5 V,
Minimum cycle,
RAS cycling,
CAS high (RAS-only);
CAS before RAS (CBR)
ICC4
Average page
current (see Note 4)
VCC = 5.5 V,
RAS low,
tPC = MIN
CAS cycling
NOTES: 3. ICC3 is measured with a maximum of one address change while RAS = VIL.
4. ICC4 is measured with a maximum of one address change while CAS = VIH.
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5
TM497MBK36H, TM497MBK36I
4194304 BY 36-BIT
DYNAMIC RAM MODULES
SMMS676 – MARCH 1997
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, address inputs
60
pF
Ci(C)
Input capacitance, CAS inputs
21
pF
Ci(R)
Input capacitance, RAS inputs
42
pF
Ci(W)
Input capacitance, write-enable input
84
pF
Co
Output capacitance
DQ pins
7
Parity pins
12
pF
NOTE 5: VCC = 5 V ± 0.5 V, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
’497MBK36H / I-60
PARAMETER
MIN
’497MBK36H / I-70
MAX
MIN
MAX
’497MBK36H / I-80
MIN
MAX
UNIT
tAA
tCAC
Access time from column address
30
35
40
ns
Access time from CAS low
15
18
20
ns
tCPA
tRAC
Access time from column precharge
35
40
45
ns
Access time from RAS low
60
70
80
ns
tCLZ
tOH
CAS to output in low-impedance state
0
0
0
Output disable time, start of CAS high
3
3
3
tOFF Output disable time after CAS high (see Note 6)
NOTE 6: tOFF is specified when the output is no longer driven.
0
15
0
18
0
ns
ns
20
ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’497MBK36H / I-60
MIN
tRC
Cycle time, random read or write (see Note 7)
tPC
’497MBK36H / I-70
MAX
MIN
MAX
’497MBK36H / I-80
MIN
MAX
UNIT
110
130
150
ns
Cycle time, page-mode read or write
(see Notes 7 and 8)
40
45
50
ns
tRASP
tRAS
Pulse duration, page-mode, RAS low
60
100 000
70
100 000
80
100 000
ns
Pulse duration, nonpage-mode, RAS low
60
10 000
70
10 000
80
10 000
ns
tCAS
tCP
Pulse duration, CAS low
15
10 000
18
10 000
20
10 000
ns
Pulse duration, CAS high
10
10
10
ns
tRP
tWP
Pulse duration, RAS high (precharge)
40
50
60
ns
Pulse duration, W low
10
10
10
ns
tASC
tASR
Setup time, column address before CAS low
0
0
0
ns
Setup time, row address before RAS low
0
0
0
ns
tDS
tRCS
Setup time, data before CAS low
0
0
0
ns
Setup time, W high before CAS low
0
0
0
ns
tCWL
tRWL
Setup time, W low before CAS high
15
18
20
ns
Setup time, W low before RAS high
15
18
20
ns
tWCS
tWRP
Setup time, W low before CAS low
Setup time, W high before RAS low (CBR refresh only)
0
0
0
ns
10
10
10
ns
NOTES: 7. All cycles assume tT = 5 ns.
8. To assure tPC min, tASC should be ≥ tCP.
6
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TM497MBK36H, TM497MBK36I
4194304 BY 36-BIT
DYNAMIC RAM MODULES
SMMS676 – MARCH 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
’497MBK36H / I-60
MIN
’497MBK36H / I-70
MAX
MIN
MAX
’497MBK36H / I-80
MIN
MAX
UNIT
tCAH
tRHCP
Hold time, column address after CAS low
10
15
15
ns
Hold time, RAS high from CAS precharge
35
40
45
ns
tDH
tRAH
Hold time, data after CAS low
10
15
15
ns
Hold time, row address after RAS low
10
10
10
ns
tRCH
tRRH
Hold time, W high after CAS high (see Note 9)
0
0
0
ns
Hold time, W high after RAS high (see Note 9)
0
0
0
ns
tWCH
tWRH
Hold time, W low after CAS low
10
15
15
ns
Hold time, W high after RAS low (CBR refresh only)
10
10
10
ns
tCHR
tCRP
Delay time, RAS low to CAS high (CBR refresh only)
10
10
10
ns
Delay time, CAS high to RAS low
5
5
5
ns
tCSH
tCSR
Delay time, RAS low to CAS high
60
70
80
ns
tRAD
tRAL
Delay time, RAS low to column address (see Note 10)
15
Delay time, column address to RAS high
30
35
40
tCAL
tRCD
Delay time, column address to CAS high
30
35
40
Delay time, RAS low to CAS low (see Note 10)
20
tRPC
tRSH
Delay time, RAS high to CAS low
5
5
5
ns
Delay time, CAS low to RAS high
15
18
20
ns
tREF
tT
Refresh time interval
Delay time, CAS low to RAS low (CBR refresh only)
5
5
30
45
15
20
32
Transition time
2
30
5
35
52
15
20
32
2
30
2
ns
40
ns
ns
ns
60
ns
32
ms
30
ns
NOTES: 9. Either tRRH or tRCH must be satisfied for a read cycle.
10. The maximum value is specified only to ensure access time.
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TM497MBK36H, TM497MBK36I
4194304 BY 36-BIT
DYNAMIC RAM MODULES
SMMS676 – MARCH 1997
MECHANICAL DATA
BK–72 PIN SINGLE-IN-LINE MEMORY MODULE
R–PSIP–N72
0.054 (1,37)
0.047 (1,19)
4.255 (108,08)
4.245 (107,82)
0.125 (3,18) TYP
0.128 (3,25)
0.120 (3,05)
1.005 (25,53)
0.995 (25,27)
0.010 (0,254) MAX
0.050 (1,27) TYP
0.400 (10,16) TYP
0.040 (1,02) TYP
0.208 (5,28) MAX
0.360 (9,14) MAX
NOTE A: All linear dimensions are in inches (millimeters).
device symbolization
TM497MBK36I
-SS
YY
MM
T
-SS
=
=
=
=
Year Code
Month Code
Assembly Site Code
Speed Code
NOTE A: Location of symbolization may vary.
8
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YYMMT
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