TI TM497FBK32G

TM497FBK32R, TM497FBK32G 4194304 BY 32-BIT
TM893GBK32R, TM893GBK32G 8388608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS672 – FEBRUARY 1997
D
D
D
D
D
D
D
D
D
D
Organization
– TM497FBK32R/G: 4 194 304 x 32
– TM893GBK32R/G: 8 388 608 x 32
Single 5-V Power Supply (±10% Tolerance)
72-Pin Single-In-Line Memory Module
(SIMM) for Use With Sockets
TM497FBK32R/G – Uses Eight 16M-Bit
Dynamic Random-Access Memories
(DRAMs) in Plastic Small-Outline J-Lead
(SOJ) Packages
TM893GBK32R/G – Uses Sixteen 16M-Bit
DRAMs in Plastic SOJ Packages
Long Refresh Period
32 ms (2 048 Cycles)
All Inputs, Outputs, Clocks Fully
TTL-Compatible
3-State Output
Common CAS Control for Eight Common
Data-In and Data-Out Lines in Four Blocks
Extended Data Out (EDO) Operation With
CAS-Before-RAS ( CBR), RAS-Only, and
Hidden Refresh
D
D
Presence Detect
Performance Ranges:
ACCESS ACCESS ACCESS EDO
TIME
TIME
TIME
CYCLE
tRAC
tAA
tCAC
tHPC
(MAX)
(MAX)
(MAX)
(MIN)
’497FBK32R/G-50 50 ns
40 ns
20 ns
35 ns
’497FBK32R/G-60 60 ns
30 ns
15 ns
25 ns
’497FBK32R/G-70 70 ns
35 ns
18 ns
30 ns
D
D
D
D
’893GBK32R/G-50 50 ns
’893GBK32R/G-60 60 ns
’893GBK32R/G-70 70 ns
40 ns
30 ns
35 ns
20 ns
15 ns
18 ns
35 ns
25 ns
30 ns
Low Power Dissipation
Operating Free-Air Temperature Range
0°C to 70°C
Gold-Tabbed Version Available:†
TM497FBK32G, TM893GBK32G
Tin-Lead (Solder-) Tabbed Version
Available: TM497FBK32R, TM893GBK32R
description
The TM497FBK32R/G, designed as 4 × 4 194 304 × 8-bits, is a 16M-byte, 72-pin, leadless, single-in-line
memory module (SIMM). The SIMM is composed of eight (8) TMS417409DJs, 4 194 304 × 4-bit DRAMs, each
in 24/26-lead, plastic, small-outline J-lead (SOJ) packages mounted on a substrate with decoupling capacitors.
See the TMS417409A data sheet (literature number SMKS893) for timing diagrams.
The TM497FBK32R/G SIMM is available in the single-sided BK leadless module for use with sockets. The
TM497FBK32R/G features RAS access times of 50, 60, and 70 ns. This device is designed for operation from
0°C to 70°C.
The TM893GBK32R/G, designed as 4 × 8 388 608 × 8-bits, is a 32M-byte, 72-pin, leadless SIMM. The SIMM
is composed of sixteen TMS417409DJs, 4 194 304 × 4-bit DRAMs, each in 24/26-lead, plastic, small-outline
J-lead (SOJ) packages mounted on a substrate with decoupling capacitors. See the TMS417409A data sheet
(literature number SMKS893) for timing diagrams.
The TM893GBK32R/G SIMM is available in the double-sided BK leadless module for use with sockets. The
TM893GBK32R/G features RAS access times of 50, 60, and 70 ns. This device is characterized for operation
from 0°C to 70°C.
operation
The TM497FBK32R / G operates as eight TMS417409DJs connected as shown in the functional block diagram
of TM497RBK32R/G and in Table 1. The common I/O feature dictates the use of early write cycles to prevent
contention on D and Q.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
1
TM497FBK32R, TM497FBK32G 4194304 BY 32-BIT
TM893GBK32R, TM893GBK32G 8388608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS672 – FEBRUARY 1997
operation (continued)
The TM893GBK32R / G operates as sixteen TMS417409DJs connected as shown in the functional block
diagram of TM893GBK32R/G and in Table 2. The common I/O feature dictates the use of early write cycles to
prevent contention on D and Q.
refresh
The refresh period is extended to 32 ms and, during this period, each of the 2 048 rows must be strobed with
RAS to retain data. CAS can remain high during the refresh sequence to conserve power.
power up
To achieve proper operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is
required after full VDD level is achieved. These eight initialization cycles need to include at least one refresh
(RAS-only or CBR ) cycle.
2
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TM497FBK32R, TM497FBK32G 4194304 BY 32-BIT
TM893GBK32R, TM893GBK32G 8388608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS672 – FEBRUARY 1997
BK SINGLE-IN-LINE PACKAGE
( TOP VIEW )
VSS
DQ0
DQ16
DQ1
DQ17
DQ2
DQ18
DQ3
DQ19
VDD
NC
A0
A1
A2
A3
A4
A5
A6
A10
DQ4
DQ20
DQ5
DQ21
DQ6
DQ22
DQ7
DQ23
A7
NC
VDD
A8
A9
NC
RAS2
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
NC
NC
VSS
CAS0
CAS2
CAS3
CAS1
RAS0
NC
NC
W
NC
DQ8
DQ24
DQ9
DQ25
DQ10
DQ26
DQ11
DQ27
DQ12
DQ28
VDD
DQ29
DQ13
DQ30
DQ14
DQ31
DQ15
NC
PD1
PD2
PD3
PD4
NC
VSS
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
TM497FBK32R/G
( SIDE VIEW )
TM893GBK32R/G
( SIDE VIEW )
PIN NOMENCLATURE
A0 – A10
CAS0 – CAS3
DQ0 – DQ31
NC
PD1 – PD4
RAS0 – RAS3
VDD
VSS
W
Address Inputs
Column-Address Strobe
Data In / Data Out
No Connection
Presence Detects
Row-Address Strobe
5-V Supply
Ground
Write Enable
PRESENCE DETECT
SIGNAL
(PIN)
70 ns
TM497FBK32R/G
60 ns
50 ns
TM893GBK32R/G
POST OFFICE BOX 1443
PD1
(67)
PD2
(68)
PD3
(69)
PD4
(70)
VSS
VSS
NC
VSS
NC
NC
VSS
NC
70 ns
VSS
NC
60 ns
50 ns
• HOUSTON, TEXAS 77251–1443
NC
NC
NC
NC
VSS
VSS
VSS
NC
NC
VSS
NC
NC
NC
VSS
3
TM497FBK32R, TM497FBK32G 4194304 BY 32-BIT
TM893GBK32R, TM893GBK32G 8388608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS672 – FEBRUARY 1997
Table 1. TM497FBK32R/G Connection Table
DATA BLOCK
RASx
CASx
DQ0 – DQ7
RAS0
CAS0
DQ8 – DQ15
RAS0
CAS1
DQ16 – DQ23
RAS2
CAS2
DQ24 – DQ31
RAS2
CAS3
Table 2. TM893GBK32R/G Connection Table
DATA BLOCK
RASx
CASx
Side 1
Side 2
DQ0 – DQ7
RAS0
RAS1
CAS0
DQ8 – DQ15
RAS0
RAS1
CAS1
DQ16 – DQ23
RAS2
RAS3
CAS2
DQ24 – DQ31
RAS2
RAS3
CAS3
single-in-line memory module and components
PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for TM497FBK32G and TM893GBK32G: Nickel plate and gold plate over copper
Contact area for TM497FBK32R and TM893GBK32R: Nickel plate and tin-lead over copper
4
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
RAS0
W
CAS0
A0 – A10
33 Ω
11
11
11
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
DQ4 –
DQ7
DQ0 –
DQ3
CAS1
functional block diagram of TM497RBK32R/G
11
11
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
DQ12 –
DQ15
DQ8 –
DQ11
CAS2
RAS2
33 Ω
11
11
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
DQ20 –
DQ23
DQ16 –
DQ19
CAS3
11
11
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
DQ28 –
DQ31
DQ24 –
DQ27
TM497FBK32R, TM497FBK32G 4 194 304 BY 32-BIT
TM893GBK32R, TM893GBK32G 8 388 608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS672 – FEBRUARY 1997
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
5
6
RAS1
W
CAS0
A0 – A10
side 2
RAS0
W
CAS0
A0 – A10
side 1
33 Ω
11
33 Ω
11
11
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
11
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1–
DQ4
11 4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1–
DQ4
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1–
DQ4
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1–
DQ4
DQ4 –
DQ7
DQ0 –
DQ3
CAS1
DQ4 –
DQ7
DQ0 –
DQ3
CAS1
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1–
DQ4
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1–
DQ4
11
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1–
DQ4
11 4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1–
DQ4
11
11
functional block diagrams of TM893GBK32R/G
33 Ω
33 Ω
DQ12 –
DQ15
DQ8 –
DQ11
CAS2
RAS3
DQ12 –
DQ15
DQ8 –
DQ11
CAS2
RAS2
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1–
DQ4
11
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1–
DQ4
11 4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1–
DQ4
11
11 4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1–
DQ4
DQ20 –
DQ23
DQ16 –
DQ19
CAS3
DQ20 –
DQ23
DQ16 –
DQ19
CAS3
11
11
11
11
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1–
DQ4
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1–
DQ4
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1–
DQ4
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1–
DQ4
DQ28 –
DQ31
DQ24 –
DQ27
DQ28 –
DQ31
DQ24 –
DQ27
Template Release Date: 7–11–94
TM497FBK32R, TM497FBK32G 4 194 304 BY 32-BIT
TM893GBK32R, TM893GBK32G 8 388 608 BY 32-BIT
EXTENDED
DATA OUT DYNAMIC RAM MODULES
SMMS672 – FEBRUARY 1997
TM497FBK32R, TM497FBK32G 4 194 304 BY 32-BIT
TM893GBK32R, TM893GBK32G 8 388 608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS672 – FEBRUARY 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
5
UNIT
VDD
VIH
Supply voltage
4.5
5.5
V
High-level input voltage
2.4
6.5
V
VIL
TA
Low-level input voltage (see Note 2)
–1
0.8
V
0
70
°C
Operating free-air temperature
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
VOH
VOL
High-level output voltage
II
Input current (leakage)
IO
ICC1
ICC2
Low-level output voltage
TEST CONDITIONS‡
IOH = – 5 mA
IOL = 4.2 mA
’497FBK32-50
MIN
MAX
2.4
’497FBK32-60
MIN
MAX
2.4
’497FBK32-70
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
VDD = 5.5 V,
VI = 0 V to 6.5 V,
All others = 0 V to VDD
± 10
± 10
± 10
µA
Output current (leakage)
VDD = 5.5 V,
CAS high
VO = 0 V to VDD,
± 10
± 10
± 10
µA
Average read- or write-cycle
current (see Note 3)
VDD = 5.5 V,
Minimum cycle
960
880
800
mA
16
16
16
mA
8
8
8
mA
Average standby current
VIH = 2.4 V (TTL),
After one memory cycle,
RAS and CAS high
VIH = VDD – 0.2 V (CMOS),
After one memory cycle,
RAS and CAS high
ICC3
Average refresh current
(RAS only or CBR)
(see Note 3)
VDD = 5.5 V,
Minimum cycle,
RAS cycling,
CAS high
(RAS only);
RAS low after
CAS low (CBR)
960
880
800
mA
ICC4
Average EDO
(see Note 4)
VDD = 5.5 V,
RAS low,
800
720
640
mA
tPC = MIN,
CAS cycling
‡ For test conditions shown as MIN / MAX, use the appropriate value specified under recommended operating conditions.
NOTES: 3. Measured with a maximum of one address change while RAS = VIL
4. Measured with a maximum of one address change while CAS = VIH
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
7
TM497FBK32R, TM497FBK32G 4 194 304 BY 32-BIT
TM893GBK32R, TM893GBK32G 8 388 608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS672 – FEBRUARY 1997
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TEST CONDITIONS†
PARAMETER
VOH
VOL
High-level output voltage
IOH = – 5 mA
IOL = 4.2 mA
Low-level output voltage
’893GBK32-50
MIN
’893GBK32-60
MAX
2.4
MIN
MAX
2.4
’893GBK32-70
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
± 20
± 20
± 20
µA
II
Input current (leakage)
VDD = 5.5 V,
VI = 0 V to 6.5 V,
All others = 0 V to VDD
IO
Output current (leakage)
VDD = 5.5 V,
CASx high
VO = 0 V to VDD,
± 20
± 20
± 20
µA
ICC1
Average read- or write-cycle
current (see Note 3)
VDD = 5.5 V,
Minimum cycle
976
896
816
mA
VIH = 2.4 V (TTL),
After one memory cycle,
RASx and CASx high
32
32
32
mA
VIH = VDD – 0.2 V (CMOS),
After one memory cycle,
RASx and CASx high
16
16
16
mA
ICC2
Average standby current
ICC3
Average refresh current
(RAS only or CBR)
(see Note 3)
VDD = 5.5 V,
RASx cycling,
(RASx only);
Minimum cycle
CASx low (CBR) CASx high
RASx low after
1920
1760
1600
mA
ICC4
Average EDO
(see Note 4)
VDD = 5.5 V,
RASx low,
1600
1440
1280
mA
tPC = MIN,
CASx cycling
† For test conditions shown as MIN / MAX, use the appropriate value specified under recommended operating conditions.
NOTES: 3. Measured with a maximum of one address change while RAS = VIL
4. Measured with a maximum of one address change while CAS = VIH
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
TM497FBK32R/G
PARAMETER
MIN
MAX
TM893GBK32R/G
MIN
MAX
UNIT
Ci(A)
Input capacitance, address inputs
50
80
pF
Ci(R)
Input capacitance, RAS inputs
28
33
pF
Ci(C)
Input capacitance, CAS inputs
17
28
pF
Ci(W)
Input capacitance, write-enable input
66
112
pF
Co(DQ)
Output capacitance on DQ pins
9
14
pF
NOTE 5: VDD = 5 V ± 0.5 V, and the bias on pins under test is 0 V.
8
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TM497FBK32R, TM497FBK32G 4 194 304 BY 32-BIT
TM893GBK32R, TM893GBK32G 8 388 608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS672 – FEBRUARY 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Note 6)
’497FBK32-50
’893GBK32-50
PARAMETER
MIN
MAX
’497FBK32-60
’893GBK32-60
MIN
MAX
’497FBK32-70
’893GBK32-70
MIN
UNIT
MAX
tAA
tCAC
Access time from column address
25
30
35
ns
Access time from CAS low
13
15
18
ns
tCPA
tRAC
Access time from column precharge
28
35
40
ns
Access time from RAS low
50
60
70
ns
tCLZ
tOH
CAS to output in low-impedance state
0
0
0
Output disable time from start of CAS high
3
3
3
tOFF Output disable time after CAS high (see Note 6)
NOTES: 6. With ac parameters, it is assumed that tT = 2 ns.
7. tOFF is specified when the output is no longer driven.
0
13
0
15
0
ns
ns
18
ns
EDO timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’497FBK32-50
’893GBK32-50
MIN
MAX
’497FBK32-60
’893GBK32-60
MIN
MAX
’497FBK32-70
’893GBK32-70
MIN
UNIT
MAX
tHPC
tPRWC
Cycle time, EDO page mode read or write
20
25
30
ns
Cycle time, EDO read-write
57
68
78
ns
tCSH
tDOH
Hold time, CAS after RAS
40
48
58
ns
Hold time, output after RAS
5
tCAS
tWPE
Pulse duration, CAS
8
Pulse duration, W (output disable only)
7
7
7
ns
8
10
10
ns
tCP
Precharge time, CAS
NOTE 6: With ac parameters, it is assumed that tT = 2 ns.
POST OFFICE BOX 1443
5
10 000
• HOUSTON, TEXAS 77251–1443
10
5
10 000
12
ns
10 000
ns
9
TM497FBK32R, TM497FBK32G 4 194 304 BY 32-BIT
TM893GBK32R, TM893GBK32G 8 388 608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS672 – FEBRUARY 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 6)
’497FBK32-50
’893GBK32-50
MIN
MAX
’497FBK32-60
’893GBK32-60
MIN
MAX
MIN
UNIT
MAX
tRC
tRASP
Cycle time, random read or write (see Note 8)
84
Pulse duration, page-mode, RAS low (see Note 8)
50
100 000
tRAS
tCAS
Pulse duration, non-page-mode, RAS low (see Note 8)
50
Pulse duration, CAS low
20
tCP
tRP
Pulse duration, CAS high
8
10
10
ns
30
40
50
ns
tWP
tASC
Pulse duration, W low
8
10
10
ns
Setup time, column address before CAS low
0
0
0
ns
tASR
tDS
Setup time, row address before RAS low
0
0
0
ns
Setup time, data before CAS low (see Note 9)
0
0
0
ns
tRCS
tCWL
Setup time, W high before CAS low
0
0
0
ns
Setup time, W-low before CAS high
8
10
12
ns
tRWL
tWCS
Setup time, W-low before RAS high
8
10
12
ns
Setup time, W-low before CAS low
0
0
0
ns
tWRP
Setup time, W-high before RAS low (CBR refresh only)
10
10
10
ns
tCAH
tRHCP
Hold time, column address after CAS low
8
10
12
ns
Hold time, RAS high after CAS precharge
28
35
40
ns
tDH
tRAH
Hold time, data after CAS low (see Note 9)
8
10
12
ns
Hold time, row address after RAS low
8
10
10
ns
tRCH
tRRH
Hold time, W high after CAS high (see Note 10)
0
0
0
ns
Hold time, W high after RAS high (see Note 10)
0
0
0
ns
tWCH
tWRH
Hold time, W low after CAS low (early-write only)
10
10
12
ns
Hold time, W high after RAS low (CBR refresh only)
10
10
10
ns
tCHR
tCRP
Delay time, RAS low to CAS high (CBR refresh only)
8
10
10
ns
Delay time, CAS high to RAS low
5
5
5
ns
tCSH
tCSR
Delay time, RAS low to CAS high
40
48
58
ns
5
5
5
ns
tRAD
tRAL
Delay time, RAS low to column address (see Note 11)
10
Delay time, column address to RAS high
25
tCAL
tRCD
Delay time, column address to CAS high
18
Delay time, RAS low to CAS low (see Note 11)
20
tRPC
tRSH
Delay time, RAS high to CAS low (CBR only)
5
Delay time, CAS low to RAS high
8
tREF
tT
Refresh time interval
Pulse duration, RAS high (precharge)
Delay time, CAS low to RAS low (CBR refresh only)
10
2
ns
70
100 000
ns
10 000
60
10 000
70
10 000
ns
10 000
15
10 000
18
10 000
ns
25
12
30
30
20
• HOUSTON, TEXAS 77251–1443
20
ns
52
30
2
ns
ns
12
32
ns
ns
5
10
2
35
25
45
5
30
12
35
20
37
With ac parameters, it is assumed that tT = 2 ns.
In a read-write cycle, tRWD and tRWL must be observed.
Referenced to the later of CAS or W in write operations.
Either tRRH or tRCH must be satisfied for a read cycle.
The maximum value is specified only to assure access time.
POST OFFICE BOX 1443
124
60 100 000
32
Transition time
NOTES: 6.
8.
9.
10.
11.
104
’497FBK32-70
’893GBK32-70
ns
32
ms
30
ns
TM497FBK32R, TM497FBK32G 4 194 304 BY 32-BIT
TM893GBK32R, TM893GBK32G 8 388 608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS672 – FEBRUARY 1997
MECHANICAL DATA
BK (R-PSIM-N72)
SINGLE-IN-LINE MEMORY MODULE
0.054 (1,37)
0.047 (1,19)
4.255 (108,08)
4.245 (107,82)
0.125 (3,18) TYP
1.005 (25,53)
0.995 (25,27)
0.128 (3,25)
0.120 (3,05)
0.050 (1,27)
0.010 (0,25) MAX
0.400 (10,16) TYP
0.040 (1,02) TYP
0.208 (5,28) MAX
0.360 (9,14) MAX
(For Double-Sided SIMM)
4040197 / B 02/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
device symbolization
TM497FBK32R
-SS
YY
MM
T
-SS
YYMMT
= Year Code
= Month Code
= Assembly Site Code
= Speed Code
NOTE: The location of the part number may vary.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
11
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