TI TM893NBM36H

TM893NBM36H, TM893NBM36I 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS677 – MARCH 1997
D
D
D
D
D
D
D
D
D
D
D
Organization
TM893NBM36H/I . . . 8 388 608 × 36
Single 5-V Power Supply (±10% Tolerance)
72-Pin Leadless Single In-Line Memory
Module (SIMM) for Use With Sockets
TM893NBM36H/ I – Uses Sixteen 16M-Bit
and Eight 4M-Bit DRAMs in Plastic
Small-Outline J-Lead (SOJ) Packages
Long Refresh Period
32 ms (2 048 Cycles)
All Inputs, Outputs, Clocks Fully
TTL-Compatible
3-State Output
Common CAS Control for Nine Common
Data-In and Data-Out Lines in Four Blocks
Enhanced Page-Mode Operation With
CAS-Before-RAS ( CBR), RAS-Only, and
Hidden Refresh
D
D
D
Present Detect
Operating Free-Air Temperature Range
0°C to 70°C
Performance Ranges:
ACCESS ACCESS ACCESS READ
TIME
TIME
TIME
OR
tRAC
tAA
tCAC WRITE
CYCLE
(MAX)
(MAX)
(MAX)
(MIN)
’893NBM36H / I-60 60 ns
30 ns
15 ns
110 ns
’893NBM36H / I-70 70 ns
35 ns
18 ns
130 ns
’893NBM36H / I-80 80 ns
40 ns
20 ns
150 ns
Gold-Tabbed Versions Available:†
TM893NBM36H
Tin-Lead (Solder)-Tabbed Versions
Available:
TM893NBM36I
description
The TM893NBM36H / I is a 32M-byte dynamic random-access memory (DRAM) organized as four times
8 388 608 × 9 (bit 9 is generally used for parity) in a 72-pin leadless SIMM. The SIMM is composed of sixteen
TMS417400ADJ 4 194 304 × 4-bit DRAMs, each in a 24 / 26-lead plastic SOJ package, and eight TMS44100DJ
4 194 304 × 1-bit DRAMs, each in a 20 / 26-lead plastic SOJ package, mounted on a substrate with decoupling
capacitors. The TMS417400ADJ and TMS44100DJ are described in the TMS417400A (literature number
SMKS889) and TMS44100 (literature number SMHS561) data sheets, respectively. The TM893NBM36A
SIMM is available in the double-sided, BM leadless module for use with sockets.
operation
The TM893NBM36H / I operates as sixteen TMS417400ADJ DRAMs and eight TMS44100DJ DRAMs
connected as shown in the functional block diagram and in Table 1. The common I / O feature dictates the use
of early-write cycles to prevent contention on D and Q.
Table 1. Connection Table
DATA BLOCK
RASx
CASx
SIDE 1
SIDE 2
DQ0 – DQ8
RAS0
RAS1
CAS0
DQ9 – DQ17
RAS0
RAS1
CAS1
DQ18 – DQ26
RAS2
RAS3
CAS2
DQ27 – DQ35
RAS2
RAS3
CAS3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† Part numbers in this data sheet refer only to the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
1
TM893NBM36H, TM893NBM36I 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS677 – MARCH 1997
refresh
The refresh period is extended to 32 ms, and, during this period, each of the 2 048 rows must be strobed with
RAS to retain data. Address line A10 must be used as the most significant refresh address line (lowest
frequency) to ensure correct refresh for both TMS417400A and TMS44100. Address lines A0 – A9 must be
refreshed every 16 ms as required by the TMS44100 DRAM. To conserve power, CAS can remain high during
the refresh sequence.
power up
To achieve proper operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is
required after full VCC level is achieved. These eight initialization cycles must include at least one refresh
(RAS-only or CBR-refresh) cycle.
single in-line memory module and components
PC substrate: 1, 27 ± 0,1 mm (0.05 inch) nominal thickness; inch / inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for TM893NBM36H: Nickel plate and gold plate over copper
Contact area for TM893NBM36I: Nickel plate and tin / lead over copper
2
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TM893NBM36H, TM893NBM36I 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS677 – MARCH 1997
VSS
DQ0
DQ18
DQ1
DQ19
DQ2
DQ20
DQ3
DQ21
VCC
NC
A0
A1
A2
A3
A4
A5
A6
A10
DQ4
DQ22
DQ5
DQ23
DQ6
DQ24
DQ7
DQ25
A7
NC
VCC
A8
A9
RAS3
RAS2
DQ26
DQ8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
DQ17
DQ35
VSS
CAS0
CAS2
CAS3
CAS1
RAS0
RAS1
NC
W
NC
DQ9
DQ27
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
DQ13
DQ31
VCC
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
NC
PD1
PD2
PD3
PD4
NC
VSS
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
TM893NBM36H/I
( SIDE VIEW )
Reference
BM SINGLE IN-LINE PACKAGE
( TOP VIEW )
PIN NOMENCLATURE
A0 – A10
CAS0 – CAS3
DQ0 – DQ35
NC
PD1 – PD4
RAS0 – RAS3
VCC
VSS
W
Address Inputs
Column-Address Strobe
Data In / Data Out
No Connection
Presence Detects
Row-Address Strobe
5-V Supply
Ground
Write Enable
PRESENCE DETECT
SIGNAL
(PIN)
TM893NBM36H/I
POST OFFICE BOX 1443
PD1
(67)
PD2
(68)
80 ns
NC
70 ns
NC
VSS
VSS
60 ns
NC
VSS
• HOUSTON, TEXAS 77251–1443
PD3
(69)
PD4
(70)
NC
VSS
NC
VSS
NC
NC
3
11
RAS0
RAS2
W
CAS0
CAS1
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
11
11
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
4M × 1
A0 – A10
RAS
W
CAS
D
Q
11
DQ0 –
DQ3
11
DQ4 –
DQ7
11
DQ8
CAS3
CAS2
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
4M × 1
A0 – A10
RAS
W
CAS
D
Q
11
DQ9 –
DQ12
11
DQ13 –
DQ16
11
DQ17
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
4M × 1
A0 – A10
RAS
W
CAS
D
Q
11
DQ18 –
DQ21
11
DQ22 –
DQ25
11
DQ26
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
DQ27 –
DQ30
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
DQ31 –
DQ34
4M × 1
A0 – A10
RAS
W
CAS
D
Q
DQ35
Template Release Date: 7–11–94
A0 – A10
TM893NBM36H, TM893NBM36I 8388688 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS677 – MARCH 1997
4
functional block diagram (TM893NBM36H/I, side 1)
functional block diagram (TM893NBM36H/I, side 2)
A0 – A10
11
RAS1
RAS3
W
CAS0
CAS1
11
11
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
4M × 1
A0 – A10
RAS
W
CAS
D
Q
11
DQ0 –
DQ3
11
DQ4 –
DQ7
11
DQ8
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
4M × 1
A0 – A10
RAS
W
CAS
D
Q
11
DQ9 –
DQ12
11
DQ13 –
DQ16
11
DQ17
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
4M × 1
A0 – A10
RAS
W
CAS
D
Q
11
DQ18 –
DQ21
11
DQ22 –
DQ25
11
DQ26
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
DQ27 –
DQ30
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
DQ31 –
DQ34
4M × 1
A0 – A10
RAS
W
CAS
D
Q
DQ35
SMMS677 – MARCH 1997
5
TM893NBM36H, TM893NBM36I 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
11
4M × 4
A0 – A10
RAS
W
CAS
OE
DQ1 –
DQ4
CAS3
CAS2
TM893NBM36H, TM893NBM36I 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS677 – MARCH 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation: TM893NBM36H, TM893NBM36I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 W
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
VCC
VIH
Supply voltage
4.5
5
5.5
V
High-level input voltage
2.4
6.5
V
VIL
TA
Low-level input voltage (see Note 2)
–1
0.8
V
0
70
°C
Operating free-air temperature
UNIT
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
6
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TM893NBM36H, TM893NBM36I 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS677 – MARCH 1997
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
TEST CONDITIONS†
PARAMETER
VOH
High-level output
voltage
IOH = – 5 mA
VOL
Low-level output
voltage
IOL = 4.2 mA
II
Input current
(leakage)
IO
ICC1
ICC2
’893NBM36H / I - 60
MIN
MAX
’893NBM36H / I - 70
MIN
2.4
MAX
2.4
’893NBM36H / I - 80
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
VCC = 5.5 V,
VI = 0 V to 6.5 V,
All other pins = 0 V to VCC
± 20
± 20
± 20
µA
Output current
(leakage)
VCC = 5.5 V,
CAS high
VO = 0 V to VCC,
± 20
± 20
± 20
µA
Read- or
write-cycle
current
(one RAS active,
see Note 3)
VCC = 5.5 V,
Minimum cycle
1324
1184
1064
mA
VIH = 2.4 V (TTL),
After 1 memory cycle,
RAS and CAS high
48
48
48
mA
VIH = VCC – 0.2 V (CMOS),
After 1 memory cycle,
RAS and CAS high
24
24
24
mA
1324
1184
1064
mA
944
824
704
mA
Standby current
ICC3
Average refresh
current
(RAS only or
CBR,
see Note 3)
VCC = 5.5 V,
Minimum cycle,
RAS cycling,
CAS high (RAS-only refresh);
RAS low after CAS low (CBR)
ICC4
Average page
current
(one RAS active,
see Note 4)
VCC = 5.5 V,
RAS low,
tPC = MIN,
CAS cycling
† For test conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
NOTES: 3. Measured with a maximum of one address change while RAS = VIL
4. Measured with a maximum of one address change while CAS = VIH
capacitance over recommended supply voltage range and operating free-air temperature range,
f = 1 MHz (see Note 5)
’893NMB36H / I
PARAMETER
Ci(A)
Input capacitance, A0 – A10
Ci(R)
Input capacitance, RAS inputs
Ci(C)
Input capacitance, CAS inputs
Ci(W)
Input capacitance, write-enable input
Co(DQ)
(DQ)
Output capacitance
MIN
MAX
UNIT
120
pF
42
pF
42
pF
168
pF
DQ pins
14
pF
Parity pins
24
pF
NOTE 5: VCC = 5 V ± 0.5 V, and the bias on pins under test is 0 V.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
7
TM893NBM36H, TM893NBM36I 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS677 – MARCH 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
’893NBM36H / I - 60
PARAMETER
MIN
’893NBM36H / I - 70
MAX
MIN
MAX
’893NBM36H / I - 80
MIN
MAX
UNIT
tAA
tCAC
Access time from column address
30
35
40
ns
Access time from CAS low
15
18
20
ns
tRAC
tCPA
Access time from RAS low
60
70
80
ns
45
ns
tCLZ
tOFF
CAS low to output in the low-impedance state
0
Output disable time after CAS high (see Note 6)
0
Access time from column precharge
35
tOH
Output disable time, start of CAS high
NOTE 6: tOFF is specified when the output is no longer driven.
40
0
15
0
3
0
18
3
0
ns
20
3
ns
ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’893NBM36H / I - 60
MIN
tRC
Cycle time, random read or write (see Note 7)
tPC
MAX
’893NBM36H / I - 70
MIN
MAX
’893NBM36H / I - 80
MIN
MAX
UNIT
110
130
150
ns
Cycle time, page-mode read or write
(see Notes 7 and 8)
40
45
50
ns
tRASP
tRAS
Pulse duration, page mode, RAS low
60
100 000
70
100 000
80
100 000
ns
Pulse duration, nonpage mode, RAS low
60
10 000
70
10 000
80
10 000
ns
tCAS
tCP
Pulse duration, CAS low
15
10 000
18
10 000
20
10 000
ns
Pulse duration, CAS high
10
10
10
ns
tRP
tWP
Pulse duration, RAS high (precharge)
40
50
60
ns
Pulse duration, W low
10
10
10
ns
tASC
tASR
Setup time, column address before CAS low
0
0
0
ns
Setup time, row address before RAS low
0
0
0
ns
tDS
tRCS
Setup time, data before CAS low
0
0
0
ns
Setup time, W high before CAS low
0
0
0
ns
tCWL
tRWL
Setup time, W low before CAS high
15
18
20
ns
Setup time, W low before RAS high
15
18
20
ns
tWCS
Setup time, W low before CAS low
0
0
0
ns
tWRP
Setup time, W high before RAS low
(CBR refresh only)
10
10
10
ns
tCAH
tRHCP
Hold time, column address after CAS low
10
15
15
ns
Hold time, RAS high from CAS precharge
35
40
45
ns
tDH
tRAH
Hold time, data after CAS low
10
15
15
ns
Hold time, row address after RAS low
10
10
10
ns
tRCH
tRRH
Hold time, W high after CAS high (see Note 9)
0
0
0
ns
0
0
0
ns
tWCH
tWRH
Hold time, W low after CAS low
10
15
15
ns
Hold time, W high after RAS low (CBR refresh only)
10
10
10
ns
Hold time, W high after RAS high (see Note 9)
NOTES: 7. All cycle times assume tT = 5 ns.
8. To assure tPC min, tASC should be ≥ tCP .
9. Either tRRH or tRCH must be satisfied for a read cycle.
8
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TM893NBM36H, TM893NBM36I 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS677 – MARCH 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
’893NBM36H / I - 60
MIN
MAX
’893NBM36H / I - 70
MIN
MAX
’893NBM36H / I - 80
MIN
MAX
UNIT
tCHR
tCRP
Delay time, RAS low to CAS high (CBR refresh only)
10
10
10
ns
Delay time, CAS high to RAS low
5
5
5
ns
tCSH
tCSR
Delay time, RAS low to CAS high
60
70
80
ns
5
5
5
ns
Delay time, CAS low to RAS low (CBR refresh only)
Delay time, RAS low to column address
(see Note 10)
15
tRAL
tCAL
Delay time, column address to RAS high
30
35
40
ns
Delay time, column address to CAS high
30
35
40
ns
tRCD
tRPC
Delay time, RAS low to CAS low (see Note 10)
20
tRSH
tREF
Delay time, CAS low to RAS high
tRAD
Delay time, RAS high to CAS low (CBR refresh only)
30
45
5
20
POST OFFICE BOX 1443
3
52
30
• HOUSTON, TEXAS 77251–1443
15
20
60
30
3
ns
ns
ns
20
32
3
40
5
18
32
tT
Transition time
NOTE 10: The maximum value is specified only to assure access time.
35
5
15
Refresh time interval
15
ns
32
ms
30
ns
9
TM893NBM36H, TM893NBM36I 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS677 – MARCH 1997
MECHANICAL DATA
BM (R-PSIM-N72)
SINGLE/DOUBLE-SIDED IN-LINE MEMORY MODULE
4.255 (108,08)
0.054 (1,37)
0.047 (1,19)
4.245 (107,82)
0.125 (3,18) TYP
1.305 (33,15)
1.295 (32,89)
0.050 (1,27)
0.128 (3,25)
0.120 (3,05)
0.010 (0,25) MAX
0.400 (10,16) TYP
0.040 (1,02) TYP
0.208 (5,28) MAX
0.360 (9,14) MAX
4088175/A 4/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
device symbolization (TM497MBM36H illustrated)
TM497MBM36H
YY
MM
T
-SS
–SS
=
=
=
=
YYMMT
Year Code
Month Code
Assembly Site Code
Speed Code
NOTE A: Location of symbolization may vary.
10
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  1998, Texas Instruments Incorporated