TM124MBK36B, TM124MBK36R 1048576 BY 36-BIT TM248NBK36B, TM248NBK36R 2097152 BY 36-BIT DYNAMIC RAM MODULE SMMS137E – JANUARY 1991 – REVISEDJUNE 1995 D D D D D D D D D D Organization TM124MBK36B . . . 1 048 576 × 36 TM248NBK36B . . . 2 097 152 × 36 Single 5-V Power Supply (±10% Tolerance) 72-pin Leadless Single In-Line Memory Module (SIMM) for Use With Sockets TM124MBK36B–Utilizes Eight 4-Megabit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages and One 4-Megabit Quad-CAS DRAM in a Plastic Small-Outline J-Lead (SOJ) Package TM248NBK36B–Utilizes Sixteen 4-Megabit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages and Two 4-Megabit Quad-CAS DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages Long Refresh Period 16 ms (1024 Cycles) All Inputs, Outputs, Clocks Fully TTL Compatible 3-State Output Common CAS Control for Nine Common Data-In and Data-Out Lines, in Four Blocks Enhanced Page Mode Operation with CAS-Before-RAS ( CBR), RAS-Only, and Hidden Refresh D D Presence Detect Performance Ranges: ACCESS TIME tRAC D D D D ’124MBK36B-60 ’124MBK36B-70 ’124MBK36B-80 ’248NBK36B-60 ’248NBK36B-70 ’248NBK36B-80 (MAX) 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns ACCESS ACCESS READ TIME TIME OR tAA tCAC WRITE CYCLE (MAX) (MAX) (MIN) 30 ns 15 ns 110 ns 35 ns 18 ns 130 ns 40 ns 20 ns 150 ns 30 ns 15 ns 110 ns 35 ns 18 ns 130 ns 40 ns 20 ns 150 ns Low Power Dissipation Operating Free-Air Temperature Range 0°C to 70°C Gold-Tabbed Versions Available:† – TM124MBK36B – TM248NBK36B Tin-Lead (Solder) Tabbed Versions Available: – TM124MBK36R – TM248NBK36R description TM124MBK36B The TM124MBK36B is a dynamic random-access memory (DRAM) organized as four times 1 048 576 × 9 (bit 9 is generally used for parity) in a 72-pin leadless single in-line memory module (SIMM). The SIMM is composed of eight TMS44400DJ, 1 048 576 × 4-bit DRAMs, each in 20/26-lead plastic small-outline J-lead packages (SOJs), and one TMS44460DJ, 1 048 576 × 4-bit Quad-CAS DRAM in a 24/26-lead plastic small-outline J-lead package (SOJ), mounted on a substrate with decoupling capacitors. Each TMS44400DJ and TMS44460DJ is described in the TMS44400 or TMS44460 data sheet, respectively. The TM124MBK36B is available in the single-sided BK leadless module for use with sockets. The TM124MBK36B features RAS access times of 60 ns, 70 ns, and 80 ns. This device is rated for operation from 0°C to 70°C. TM248NBK36B The TM248NBK36B is a DRAM organized as four times 2 097 152 × 9 (bit 9 is generally used for parity) in a 72-pin leadless SIMM. The SIMM is composed of sixteen TMS44400DJ, 1 048 576 × 4-bit DRAMs, each in 20/26-lead plastic small-outline J-lead packages (SOJs), and two TMS44460DJ, 1 048 576 × 4-bit Quad-CAS DRAMs, each in a 24/26-lead plastic small-outline J-lead package (SOJ), mounted on a substrate with decoupling capacitors. Each TMS44400DJ and TMS44460DJ is described in the TMS44400 and TMS44460 data sheet, respectively. † Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 TM124MBK36B, TM124MBK36R 1048576 BY 36-BIT TM248NBK36B, TM248NBK36R 2097152 BY 36-BIT DYNAMIC RAM MODULE SMMS137E – JANUARY 1991 – REVISEDJUNE 1995 TM248NBK36B (continued) The TM124NBK36B is available in the double-sided BK leadless module for use with sockets. The TM124NBK36B features RAS access times of 60 ns, 70 ns, and 80 ns. This device is rated for operation from 0°C to 70°C operation TM124MBK36B The TM124MBK36B operates as eight TMS44400DJs and one TMS44460DJ connected as shown in the functional block diagram and Table 1. The parity bits are provided by the TMS44460DJ and are controlled by RAS2. To ensure proper parity bit operation all memory accesses should include a RAS2 pulse. Refer to the TMS44400 and TMS44460 data sheets for details of operation. The common I/O feature dictates the use of early write cycles to prevent contention on D and Q. TM248NBK36B The TM248NBK36B operates as sixteen TMS44400DJs and two TMS44460DJs connected as shown in the functional block diagram and Table 1. The parity bits are provided by the TMS44460DJ and are controlled by RAS2 on side 1 and RAS3 on side 2. To ensure proper parity bit operation, all memory accesses should include a RAS2 or RAS3 pulse. Refer to the TMS44400 and TMS44460 data sheets for details of operation. The common I/O feature dictates the use of early write cycles to prevent contention on D and Q. 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TM124MBK36B, TM124MBK36R 1048576 BY 36-BIT TM248NBK36B, TM248NBK36R 2097152 BY 36-BIT DYNAMIC RAM MODULE SMMS137E – JANUARY 1991 – REVISEDJUNE 1995 BK SINGLE IN-LINE MEMORY MODULE (TOP VIEW) VSS DQ0 DQ18 DQ1 DQ19 DQ2 DQ20 DQ3 DQ21 VCC NC A0 A1 A2 A3 A4 A5 A6 NC DQ4 DQ22 DQ5 DQ23 DQ6 DQ24 DQ7 DQ25 A7 NC VCC A8 A9 RAS3 RAS2 DQ26 DQ8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 DQ17 DQ35 VSS CAS0 CAS2 CAS3 CAS1 RAS0 RAS1 NC W NC DQ9 DQ27 DQ10 DQ28 DQ11 DQ29 DQ12 DQ30 DQ13 DQ31 VCC DQ32 DQ14 DQ33 DQ15 DQ34 DQ16 NC PD1 PD2 PD3 PD4 NC VSS 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 TM124MBK36B (SIDE VIEW) TM248NBK36B (SIDE VIEW) PIN NOMENCLATURE A0 – A9 CAS0 – CAS3 DQ0 – DQ35 NC PD1 – PD4 RAS0 – RAS3 VCC VSS W Address Inputs Column-Address Strobe Data In/Data Out No Connection Presence Detects Row-Address Strobe 5-V Supply Ground Write Enable PRESENCE DETECT SIGNAL (PIN) PD1 (67) PD2 (68) VSS VSS VSS VSS 80 ns VSS NC VSS NC 70 ns NC NC 60 ns NC NC 80 ns TM124MBK36B 70 ns 60 ns TM248NBK36B POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 PD3 (69) PD4 (70) NC VSS NC VSS NC NC VSS NC NC VSS NC NC 3 TM124MBK36B, TM124MBK36R 1048576 BY 36-BIT TM248NBK36B, TM248NBK36R 2097152 BY 36-BIT DYNAMIC RAM MODULE SMMS137E – JANUARY 1991 – REVISEDJUNE 1995 Table 1. Connection Table DATA BLOCK RASx CASx SIDE 1 SIDE 2† DQ0 – DQ7 DQ8 RAS0 RAS2 RAS1 RAS3 CAS0 CAS0 DQ9 – DQ16 DQ17 RAS0 RAS2 RAS1 RAS3 CAS1 CAS1 DQ18 – DQ25 DQ26 RAS2 RAS2 RAS3 RAS3 CAS2 CAS2 DQ27 – DQ34 DQ35 RAS2 RAS2 RAS3 RAS3 CAS3 CAS3 † Side 2 applies to the TM248NBK36B only. single-in-line memory module and components PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area for TM124MBK36B and TM248NBK36B: Nickel plate and gold plate over copper Contact area for TM124MBK36R and TM248NBK36R: Nickel plate and tin-lead over copper 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 functional block diagram (TM124MBK36B and TM248NBK36B, side 1) A0 – A9 10 RAS0 RAS2 W CAS0 CAS1 10 DQ0 – DQ3 10 DQ4 – DQ7 1M × 4 A0 – A9 RAS W CAS OE DQ1 – DQ4 1M × 4 A0 – A9 RAS W CAS OE DQ1 – DQ4 10 DQ9 – DQ12 10 DQ13 – DQ16 1M × 4 A0 – A9 RAS W CAS OE DQ1 – DQ4 1M × 4 A0 – A9 RAS W CAS OE DQ1 – DQ4 10 DQ18 – DQ21 10 DQ22 – DQ25 10 1M × 4 A0 – A9 RAS W CAS OE DQ1 – DQ4 1M × 4 A0 – A9 RAS W CAS OE DQ1 – DQ4 1M × 4 A0 – A9 RAS W CAS4 DQ4 CAS3 DQ3 CAS2 DQ2 DQ1 CAS1 OE DQ27 – DQ30 DQ31 – DQ34 DQ35 DQ26 DQ17 DQ8 5 TM124MBK36B, TM124MBK36R 1048576 BY 36-BIT TM248NBK36B, TM248NBK36R 2097152 BY 36-BIT DYNAMIC RAM MODULE 1M × 4 A0 – A9 RAS W CAS OE DQ1 – DQ4 10 SMMS137E – JANUARY 1991 – REVISED JUNE 1995 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 10 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 CAS3 CAS2 10 RAS1 RAS3 W CAS0 CAS1 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 10 1M × 4 A0 – A9 RAS W CAS OE DQ1 – DQ4 1M × 4 A0 – A9 RAS W CAS OE DQ1 – DQ4 10 DQ0 – DQ3 10 DQ4 – DQ7 CAS3 CAS2 1M × 4 A0 – A9 RAS W CAS OE DQ1 – DQ4 1M × 4 A0 – A9 RAS W CAS OE DQ1 – DQ4 10 DQ9 – DQ12 10 DQ13 – DQ16 1M × 4 A0 – A9 RAS W CAS OE DQ1 – DQ4 1M × 4 A0 – A9 RAS W CAS OE DQ1 – DQ4 10 DQ18 – DQ21 10 DQ22 – DQ25 10 1M × 4 A0 – A9 RAS W CAS OE DQ1 – DQ4 1M × 4 A0 – A9 RAS W CAS OE DQ1 – DQ4 1M × 4 A0 – A9 RAS W CAS4 DQ4 CAS3 DQ3 CAS2 DQ2 DQ1 CAS1 OE DQ27 – DQ30 DQ31 – DQ34 DQ35 DQ26 DQ17 DQ8 Template Release Date: 7–11–94 A0 – A9 TM124MBK36B, TM124MBK36R 1048576 BY 36-BIT TM248NBK36B, TM248NBK36R 2097152 BY 36-BIT DYNAMIC RAM MODULE SMMS137E – JANUARY 1991 – REVISED JUNE 1995 6 functional block diagram (TM248NBK36B, side 2) TM124MBK36B, TM124MBK36R 1048576 BY 36-BIT TM248NBK36B, TM248NBK36R 2097152 BY 36-BIT DYNAMIC RAM MODULE SMMS137E – JANUARY 1991 – REVISEDJUNE 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V Voltage range on VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX 5 UNIT VCC VIH Supply voltage 4.5 5.5 V High-level input voltage 2.4 6.5 V VIL TA Low-level input voltage (see Note 2) –1 0.8 V 0 70 °C Operating free-air temperature NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only. electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VOH High-level output voltage IOH = – 5 mA VOL Low-level output voltage IOL = 4.2 mA II Input current (leakage) IO ICC1 ICC2 ’124MBK36B-60 TEST CONDITIONS MIN ’124MBK36B-70 MAX 2.4 MIN MAX 2.4 ’124MBK36B-80 MIN MAX 2.4 UNIT V 0.4 0.4 0.4 V VCC = 5.5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC ± 10 ± 10 ± 10 µA Output current (leakage) VCC = 5.5 V, CAS high VO = 0 V to VCC, ± 10 ± 10 ± 10 µA Read or write cycle current (see Note 3) VCC = 5.5 V, Minimum cycle 945 810 720 mA 18 18 18 mA Standby current After 1 memory cycle, RAS and CAS high, VIH = 2.4 V (TTL) After 1 memory cycle, RAS and CAS high, VIH = VCC – 0.2 V (CMOS) 9 9 9 mA ICC3 Average refresh current (RAS only or CBR) (see Note 3) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only), RAS low after CAS low (CBR) 945 810 720 mA ICC4 Average page current (see Note 4) VCC = 5.5 V, RAS low, 810 720 630 mA tPC = minimum, CAS cycling NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 7 TM124MBK36B, TM124MBK36R 1048576 BY 36-BIT TM248NBK36B, TM248NBK36R 2097152 BY 36-BIT DYNAMIC RAM MODULE SMMS137E – JANUARY 1991 – REVISEDJUNE 1995 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VOH High-level output voltage IOH = – 5 mA VOL Low-level output voltage IOL = 4.2 mA II Input current (leakage) IO ICC1 ICC2 ’248NBK36B-60 TEST CONDITIONS MIN MAX 2.4 ’248NBK36B-70 MIN ’248NBK36B-80 MAX MIN 2.4 MAX 2.4 UNIT V 0.4 0.4 0.4 V VCC = 5.5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC ± 20 ± 20 ± 20 µA Output current (leakage) VCC = 5.5 V, CAS high VO = 0 V to VCC, ± 20 ± 20 ± 20 µA Read or write cycle current (see Note 3) VCC = 5.5 V, Minimum cycle 963 828 738 mA 36 36 36 mA 18 18 18 mA 1890 1620 1440 mA 828 738 648 mA Standby current ICC3 Average refresh current (RAS only or CBR) (see Note 3) ICC4 Average page current (see Note 4) After 1 memory cycle, RAS and CAS high, VIH = 2.4 V (TTL) After 1 memory cycle, RAS and CAS high, VIH = VCC – 0.2 V (CMOS) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only), RAS low after CAS low (CBR) VCC = 5.5 V, tPC = minimum, RAS low, CAS cycling NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 5) ’124MBK36B PARAMETER MIN MAX ’248NBK36B MIN MAX UNIT Ci(A) Input capacitance, A0 – A9 45 90 pF Ci(R) Input capacitance, RAS 35 35 pF Ci(C) Input capacitance, CAS 21 42 pF Ci(W) Input capacitance, W 63 126 pF Co(DQ) Output capacitance on DQ pins 7 14 pF NOTE 5: VCC = 5 V ± 0.5 V and the bias on pins under test is 0 V. 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TM124MBK36B, TM124MBK36R 1048576 BY 36-BIT TM248NBK36B, TM248NBK36R 2097152 BY 36-BIT DYNAMIC RAM MODULE SMMS137E – JANUARY 1991 – REVISEDJUNE 1995 switching characteristics over recommended ranges of supply voltage and operating free-air temperature ’124MBK36B-60 ’248NBK36B-60 PARAMETER MIN ’124MBK36B-70 ’248NBK36B-70 MAX MIN MAX ’124MBK36B-80 ’248NBK36B-80 MIN UNIT MAX tCAC tAA Access time from CAS low 15 18 20 ns Access time from column address 30 35 40 ns tRAC tCPA Access time from RAS low 60 70 80 ns Access time from column precharge 35 40 45 ns tCLZ tOFF CAS to output in low impedance 0 Output disable time after CAS high (see Note 6) 0 0 15 0 0 18 0 ns 20 ns NOTE 6: tOFF is specified when the output is no longer driven. timing requirements over recommended ranges of supply voltage and operating free-air temperature ’124MBK36B-60 ’248NBK36B-60 MIN ’124MBK36B-70 ’248NBK36B-70 MAX MIN MAX ’124MBK36B-80 ’248NBK36B-80 MIN UNIT MAX tRC tRWC Cycle time, random read or write (see Note 7) 110 130 150 ns Cycle time, read write 130 153 175 ns tPC tRASP Cycle time, page-mode read or write (see Note 8) 40 Pulse duration, page mode, RAS low 60 100 000 70 100 000 80 100 000 ns tRAS tCAS Pulse duration, nonpage mode, RAS low 60 10 000 70 10 000 80 10 000 ns Pulse duration, CAS low 15 10 000 18 10 000 20 10 000 ns tCP tRP Pulse duration, CAS high 10 10 10 ns Pulse duration, RAS high (precharge) 40 50 60 ns tWP tASC Pulse duration, write 15 15 15 ns Setup time, column address before CAS low 0 0 0 ns tASR tDS Setup time, row address before RAS low 0 0 0 ns Setup time, data 0 0 0 ns tRCS tCWL Setup time, read before CAS low 0 0 0 ns Setup time, W low before CAS high 15 18 20 ns tRWL tWCS Setup time, W low before RAS high 15 18 20 ns tWSR Setup time, W high (see Note 9) Setup time, W low before CAS low 45 50 ns 0 0 0 ns 10 10 10 ns NOTES: 7. All cycles assume tT = 5 ns. 8. To assure tPC min, tASC should be ≥ 5 ns. 9. CBR refresh only POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 9 TM124MBK36B, TM124MBK36R 1048576 BY 36-BIT TM248NBK36B, TM248NBK36R 2097152 BY 36-BIT DYNAMIC RAM MODULE SMMS137E – JANUARY 1991 – REVISEDJUNE 1995 timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued) ’124MBK36B-60 ’248NBK36B-60 MIN MAX ’124MBK36B-70 ’248NBK36B-70 MIN MAX ’124MBK36B-80 ’248NBK36B-80 MIN UNIT MAX tCAH tDHR Hold time, column address after CAS low 10 15 15 ns Hold time, data after RAS low (see Note 10) 50 55 60 ns tDH tAR Hold time, data 10 15 15 ns Hold time, column address after RAS low (see Note 10) 50 55 60 ns tCLCH tRAH Hold time, CAS low to CAS high tRCH tRRH Hold time, read after CAS high (see Note 11) 0 tWCH tWCR Hold time, write after CAS low 15 Hold time, write after RAS low (see Note 10) 50 tWHR tCHR Hold time, W high (see Note 9) 10 Delay time, RAS low to CAS high (see Note 9) 15 tCRP tCSH Delay time, CAS high to RAS low 0 Delay time, RAS low to CAS high 60 tCSR tRAD Delay time, CAS low to RAS low (see Note 9) 10 Delay time, RAS low to column address (see Note 12) 15 tRAL tCAL Delay time, column address to RAS high 30 Delay time, column address to CAS high 30 tRCD tRPC Delay time, RAS low to CAS low (see Note 12) 20 tRSH tREF Delay time, CAS low to RAS high tT Transition time Hold time, row address after RAS low Hold time, read after RAS high (see Note 11) Delay time, RAS high to CAS low (see Note 9) 5 5 5 ns 10 10 10 ns 0 0 0 ns 0 0 ns 15 15 ns 55 60 ns 10 10 ns 15 20 ns 0 0 ns 70 80 ns 15 10 35 35 20 0 0 18 20 2 16 50 2 50 CBR refresh only The minimum value is measured when tRCD is set to tRCD min as a reference. Either tRRH or tRCH must be satisfied for a read cycle. The maximum value is specified only to assure access time. device symbolization (TM124MBK36B illustrated) TM124MBK36B –SS YY MM T –SS = = = = Year Code Month Code Assembly Site Code Speed Code NOTE: Location of symbolization may vary. 10 POST OFFICE BOX 1443 20 • HOUSTON, TEXAS 77251–1443 YYMMT 2 ns ns 40 52 0 16 ns 40 40 35 45 15 15 Refresh time interval NOTES: 9. 10. 11. 12. 10 30 ns 60 ns ns ns 16 ms 50 ns IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated