TPIC1501A QUAD AND HEX POWER DMOS ARRAY SLIS046A – MAY 1995 – REVISED JUNE 1996 D D D D Low rDS(on): 0.1 Ω Typ (Full H-Bridge) 0.4 Ω Typ (Triple Half H-Bridge) Pulsed Current: 12 A Per Channel (Full H-Bridge) 6 A Per Channel (Triple Half H-Bridge) Matched Sense Transistor for Class A-B Linear Operation Fast Commutation Speed DW PACKAGE (TOP VIEW) OUTPUT3 GND GATE3B GATE2B SENSE OUTPUT2 GATE4B GATE2A GATE5B VDD2 OUTPUT4 SOURCE description The TPIC1501A is a monolithic power array that consists of ten electrically isolated N-channel enhancement-mode power DMOS transistors, four of which are configured as a full H-bridge and six as a triple half H-bridge. The lower stage of the full H-bridge features an integrated sense FET to allow biasing of the bridge in class A-B operation. 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VDD3 GND GATE3A GATE1B GATE2C OUTPUT1 GATE4A GATE1A GATE5A VDD1 VDD3 OUTPUT5 The TPIC1501A is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for operation over the case temperature range of – 40°C to 125°C. schematic VDD1 15 VDD2 10 Q1A 17 GATE1A 8 GATE2A Q3A 22 GATE3A 6 OUTPUT2 1 OUTPUT3 Q2A 19 OUTPUT1 D1 D2 Q1B 21 GATE1B SENSE VDD3 14, 24 Q2B 4 GATE2B D3 Q3B 3 GATE3B Q4A 18 GATE4A Q5A 16 GATE5A 11 OUTPUT4 13 OUTPUT5 Q4B 7 GATE4B Q5B 9 GATE5B 5 12 SOURCE Q2C 20 GATE2C 2, 23 GND NOTES: A. Pins 2 and 23 must be externally connected. B. Pins 14 and 24 must be externally connected. C. No output may be taken greater than 0.5 V below GND. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TPIC1501A QUAD AND HEX POWER DMOS ARRAY SLIS046A – MAY 1995 – REVISED JUNE 1996 absolute maximum ratings, TC = 25°C (unless otherwise noted)† Supply-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V Source-to-GND voltage (Q3A, Q4A, Q5A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V Output-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V Sense-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V Gate-to-source voltage range, VGS (Q1A, Q1B, Q2A, Q2B, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) . . . . . ± 20 V Gate-to-source voltage range, VGS (Q2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.7 V to 6 V Continuous drain current, each output (Q1A, Q1B, Q2A, Q2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 A Continuous drain current, each output (Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) . . . . . . . . . . . . . . . . . . . . . . . . 1.5 A Continuous drain current (Q2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 mA Continuous source-to-drain diode current (Q1A, Q1B, Q2A, Q2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 A Continuous source-to-drain diode current (Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) . . . . . . . . . . . . . . . . . . . . . 1.5 A Continuous source-to-drain diode current (Q2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 mA Pulsed drain current, each output, Imax (Q1A, Q1B, Q2A, Q2B) (see Note 1 and Figure 24) . . . . . . . . 12 A Pulsed drain current, each output, Imax (Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) (see Note 1 and Figure 25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 A Pulsed drain current, Imax (Q2C) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 mA Continuous total power dissipation, TC = 70°C (see Note 2 and Figures 24 and 25) . . . . . . . . . . . . . 2.86 W Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Pulse duration = 10 ms, duty cycle = 2% 2. Package is mounted in intimate contact with infinite heat sink. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPIC1501A QUAD AND HEX POWER DMOS ARRAY SLIS046A – MAY 1995 – REVISED JUNE 1996 electrical characteristics, Q1A, Q1B, Q2A, Q2B, TC = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS ID = 250 µA, ID = 1 mA, See Figure 5 V(BR)DSX Drain-to-source breakdown voltage VGS(th) Gate-to-source threshold voltage VGS(th)match Gate-to-source threshold voltage matching V(BR) Reverse drain-to-GND breakdown voltage VDS(on) Drain-to-source on-state voltage ID = 2 A, See Notes 3 and 4 VF Forward on-state voltage, GND-to-VDD1, GND-to-VDD2 ID = 3 A (D1, D2) See Notes 3 and 4 VF(SD) Forward on-state on state voltage, voltage source-to-drain source to drain VGS = 0 VDS = VGS, ID = 1 mA, VDS = VGS Drain-to-GND current = 250 µA (D1, D2) VGS = 16 V, IGSSR Reverse-gate current, drain short circuited to source Ilk lkg Leakage g current,, VDD1-to-GND,, VDD2-to-GND, gate shorted to source Short-circuit output capacitance, common source Crss Short-circuit reverse transfer capacitance, common source 40 mV 0.2 0.24 V V 1 05 1.05 V 11 1.1 0.05 1 0.5 10 VDS = 0 10 100 nA VSG = 16 V, VDS = 0 10 100 nA VDGND = 16 V TC = 25°C TC = 125°C 0.05 1 0.5 10 VGS = 10 V, ID = 2 A,, See Notes 3 and 4 and Figure 9 TC = 25°C 0.1 0.12 TC = 125°C 0.14 0.18 VGS = 10 V, ID = 3 A,, See Notes 3 and 4 and Figures 7 and 9 TC = 25°C 0.1 0.12 TC = 125°C 0.14 0.18 VDS = 14 V, See Notes 3 and 4 ID = 1 A, VDS = 14 V, ID = 1.5 A, See Notes 3 and 4 and Figure 13 Coss V V 09 0.9 Forward-gate current, drain short circuited to source Short-circuit input capacitance, common source 2.1 20 IS = 3 A, VGS = 0, See Notes 3 and 4 and Figure 19 IGSSF Ciss 1.7 0 85 0.85 TC = 25°C TC = 125°C F d transconductance t d t Forward 1.4 UNIT V IS = 2 A, VGS = 0, See Notes 3 and 4 and Figure 19 VDS = 16 V,, VGS = 0 gfs MAX 1.8 Zero gate voltage drain current Zero-gate-voltage drain to source on-state on state resistance Static drain-to-source TYP 20 VGS = 10 V, IDSS rDS(on) DS( ) MIN µA µA Ω 1.5 2.5 2 31 3.1 S 240 VDS = 14 V, f = 1 MHz, VGS = 0, See Figure 17 130 αs Sense-FET drain current ratio VDS = 6 V, ID(Q2C) = 40 µA 75 130 NOTES: 3. Technique should limit TJ – TC to 10°C maximum. 4. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. POST OFFICE BOX 655303 pF 170 • DALLAS, TEXAS 75265 200 3 TPIC1501A QUAD AND HEX POWER DMOS ARRAY SLIS046A – MAY 1995 – REVISED JUNE 1996 source-to-drain diode characteristics, Q1A, Q2A, TC = 25°C PARAMETER trr Reverse-recovery time QRR Total diode charge trr QRR Reverse-recovery time Total diode charge TEST CONDITIONS IS = 1.5 A, VDS = 14 V, V See Figures 1 and 23 VGS = 0, di/dt = 100 A/µs A/µs, IS = 2 A, VDS = 14 V, VGS = 0, di/dt = 100 A/µs MIN TYP MAX UNIT 70 ns 90 nC 75 ns 110 nC resistive-load switching characteristics, Q1A, Q1B, Q2A, Q2B, TC = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX td(on) td(off) Turn-on delay time tr tf Rise time Fall time 25 Qg Total gate charge 5.6 7 0.8 1 1.4 1.75 Turn-off delay time 20 VDD = 14 V,, tdis = 10 ns, VDS = 14 V, V See Figure 4 RL = 9.3 Ω,, See Figure 3 ID = 1.5 1 5 A, A ten = 10 ns,, 30 VGS = 10 V, V Threshold gate-to-source charge Qgd Gate-to-drain charge L(drain) L(source) Internal drain inductance 5 Internal source inductance 5 r(gate) Internal gate resistance 0.25 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns 15 Qgs(th) 4 UNIT nC nH Ω TPIC1501A QUAD AND HEX POWER DMOS ARRAY SLIS046A – MAY 1995 – REVISED JUNE 1996 electrical characteristics, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B, TC = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS ID = 250 µA, ID = 1 mA, See Figure 6 V(BR)DSX Drain-to-source breakdown voltage VGS(th) Gate-to-source threshold voltage VGS(th)match V(BR) Gate-to-source threshold voltage matching VDS(on) Drain-to-source on-state voltage ID = 1.5 A, See Notes 3 and 4 VF Forward on-state voltage, GND-to-VDD3 ID = 1.5 A (D3) See Notes 3 and 4 VF(SD) Reverse drain-to-GND breakdown voltage on state voltage, voltage source-to-drain source to drain Forward on-state 1.4 ID = 1 mA, VDS = VGS Drain-to-GND current = 250 µA (D3) 20 Reverse-gate current, drain short circuited to source Ilk lkg Leakage g current,, VDD3-to-GND,, gate shorted to source Crss Short-circuit reverse transfer capacitance, common source V 0.6 0.68 V V V 0.05 1 0.5 10 VDS = 0 10 100 nA VSG = 16 V, VDS = 0 10 100 nA VDGND = 16 V TC = 25°C TC = 125°C 0.05 1 0.5 10 VGS = 10 V, ID = 0.3 A,, See Notes 3 and 4 and Figure 10 TC = 25°C 0.35 0.39 TC = 125°C 0.5 0.56 VGS = 10 V, ID = 1.5 A,, See Notes 3 and 4 and Figures 8 and 10 TC = 25°C 0.4 0.45 TC = 125°C 0.56 0.65 VDS = 14 V, See Notes 3 and 4 ID = 500 mA, µA µA Ω 03 0.3 08 0.8 0.4 0.93 S VDS = 14 V, ID = 750 mA, See Notes 3 and 4 and Figure 14 Short-circuit output capacitance, common source mV 13 1.3 IGSSR Coss 40 11 1.1 VGS = 16 V, Short-circuit input capacitance, common source V IS = 2 A, VGS = 0, See Notes 3 and 4 and Figure 20 Forward-gate current, drain short circuited to source Ciss 2.1 12 1.2 IGSSF Forward transconductance 1.7 1 TC = 25°C TC = 125°C UNIT V IS = 1.5 A, VGS = 0, See Notes 3 and 4 and Figure 20 VDS = 16 V,, VGS = 0 gfs MAX 1.7 Zero gate voltage drain current Zero-gate-voltage Static drain-to-source drain to source on-state on state resistance TYP 20 VGS = 10 V, IDSS rDS(on) DS( ) MIN VGS = 0 V VDS = VGS, 96 VDS = 14 V, f = 1 MHz, VGS = 0, See Figure 18 98 pF 65 NOTES: 3. Technique should limit TJ – TC to 10°C maximum. 4. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TPIC1501A QUAD AND HEX POWER DMOS ARRAY SLIS046A – MAY 1995 – REVISED JUNE 1996 source-to-drain diode characteristics, Q3A, Q4A, Q5A, TC = 25°C PARAMETER trr Reverse-recovery time QRR Total diode charge trr QRR Reverse-recovery time Total diode charge TEST CONDITIONS IS = 750 mA, VDS = 14 V, V See Figures 2 and 23 VGS = 0, di/dt = 100 A/µs A/µs, IS = 1.5 A, VDS = 14 V, VGS = 0, di/dt = 100 A/µs MIN TYP MAX UNIT 60 ns 55 nC 120 ns 150 nC resistive-load switching characteristics, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B, TC = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX td(on) td(off) Turn-on delay time tr tf Rise time Fall time 20 Qg Total gate charge 1.6 2 0.26 0.32 0.42 0.52 Turn-off delay time UNIT 18 VDD = 14 V,, tdis = 10 ns, VDS = 14 V, V See Figure 4 RL = 18.7 Ω,, See Figure 3 ID = 750 mA, A 25 ten = 10 ns,, ns 13 VGS = 10 V, V Qgs(th) Threshold gate-to-source charge Qgd Gate-to-drain charge L(drain) L(source) Internal drain inductance 5 Internal source inductance 5 r(gate) Internal gate resistance nC nH Ω 0.25 thermal resistance PARAMETER TEST CONDITIONS MIN TYP RθJA Junction-to-ambient thermal resistance See Notes 5 and 8 90 RθJB Junction-to-board thermal resistance See Notes 6 and 8 38 RθJP Junction-to-pin thermal resistance See Notes 7 and 8 NOTES: 5. Package is mounted on a FR4 printed-circuit board with no heat sink. 6. Package is mounted on a 24 in2, 4-layer FR4 printed-circuit board. 7. Package is mounted in intimate contact with infinite heat sink. 8. All outputs have equal power. 28 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT °C/W TPIC1501A QUAD AND HEX POWER DMOS ARRAY SLIS046A – MAY 1995 – REVISED JUNE 1996 PARAMETER MEASUREMENT INFORMATION 3 VDS = 16 V VGS = 0 TJ = 25°C Q1A, Q2A 2 I S – Source-to-Drain Diode Current – A Reverse di/dt = 100 A/µs 1 0 25% of IRM† –1 Shaded Area = QRR –2 IRM† –3 trr –4 –5 0 100 200 300 400 500 Time – ns † IRM = maximum recovery current Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diodes POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TPIC1501A QUAD AND HEX POWER DMOS ARRAY SLIS046A – MAY 1995 – REVISED JUNE 1996 PARAMETER MEASUREMENT INFORMATION 3 VDS = 16 V VGS = 0 TJ = 25°C Q3A, Q4A, Q5A I S – Source-to-Drain Diode Current – A 2 Reverse di/dt = 100 A/µs 1 0 25% of IRM† –1 Shaded Area = QRR IRM† –2 –3 trr –4 –5 0 100 200 300 Time – ns 400 500 † IRM = maximum recovery current Figure 2. Reverse-Recovery-Current Waveform of Source-to-Drain Diodes VDD = 14 V RL Pulse Generator ten VDS 10 V VGS VGS 0 DUT Rgen tdis 50 Ω td(on) CL 30 pF (see Note A) 50 Ω td(off) tr tf VDD VDS VDS(on) VOLTAGE WAVEFORMS TEST CIRCUIT NOTE A: CL includes probe and jig capacitance. Figure 3. Resistive-Switching Test Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPIC1501A QUAD AND HEX POWER DMOS ARRAY SLIS046A – MAY 1995 – REVISED JUNE 1996 PARAMETER MEASUREMENT INFORMATION Current Regulator 12-V Battery 0.2 µF Qg Same Type as DUT 50 kΩ 10 V 0.3 µF VDS Qgs(th) VDD = 14 V VGS DUT IG = 100 µA 0 Qgd Gate Voltage Time IG CurrentSampling Resistor ID CurrentSampling Resistor VOLTAGE WAVEFORM TEST CIRCUIT Figure 4. Gate-Charge Test Circuit and Voltage Waveform TYPICAL CHARACTERISTICS 2.5 VDS = VGS Q1A, Q1B, Q2A, Q2B 2 ID = 5 mA 1.5 ID = 100 µA 1 ID = 1 mA 0.5 0 – 40 – 20 0 20 40 60 80 100 120 140 160 GATE-TO-SOURCE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE VGS(th) – Gate-to-Source Threshold Voltage – V VGS(th) – Gate-to-Source Threshold Voltage – V GATE-TO-SOURCE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 2.5 ID = 5 mA 2 1.5 ID = 100 µA 1 ID = 1 mA 0.5 VDS = VGS Q3A, Q3B, Q4A, Q4B, Q5A, Q5B 0 – 40 – 20 TJ – Junction Temperature – °C 0 20 40 60 80 100 120 140 160 TJ – Junction Temperature – °C Figure 5 Figure 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TPIC1501A QUAD AND HEX POWER DMOS ARRAY SLIS046A – MAY 1995 – REVISED JUNE 1996 TYPICAL CHARACTERISTICS STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE 0.175 ID = 1.5 A Q3A, Q3B, Q4A, Q4B, Q5A, Q5B r DS(on) – Static Drain-to-Source VGS = 10 V 0.125 VGS = 15 V 0.100 0.075 VGS = 12 V 0.050 0.025 0 – 40 – 20 0 20 40 60 0.5 On-State Resistance – Ω r DS(on) – Static Drain-to-Source On-State Resistance – Ω 0.150 0.6 ID = 3 A Q1A, Q1B, Q2A, Q2B VGS = 10 V 0.4 VGS = 15 V VGS = 12 V 0.3 0.2 0.1 0 – 40 – 20 80 100 120 140 160 TJ – Junction Temperature – °C 0 20 Figure 7 1 0.9 0.8 0.7 VGS = 10 V VGS = 15 V VGS = 12 V 0.1 1 10 ID – Drain Current – A 100 TJ = 25°C Q3A, Q3B, Q4A Q4B, Q5A, Q5B 0.6 On-State Resistance – Ω r DS(on) – Static Drain-to-Source On-State Resistance – Ω r DS(on) – Static Drain-to-Source TJ = 25°C Q1A, Q1B, Q2A, Q2B VGS = 12 V 0.5 0.4 0.3 VGS = 10 V VGS = 15 V 0.2 0.1 0.01 Figure 9 10 80 100 120 140 160 STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT 10 0.01 0.01 60 Figure 8 STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT 0.1 40 TJ – Junction Temperature – °C 0.1 1.0 ID – Drain Current – A Figure 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10 TPIC1501A QUAD AND HEX POWER DMOS ARRAY SLIS046A – MAY 1995 – REVISED JUNE 1996 TYPICAL CHARACTERISTICS DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE 12 8 6 VGS = 4 V 4 VGS = 3 V 2 VGS = 7 V 5 I D – Drain Current – A 10 I D – Drain Current – A 6 ∆VGS = 0.5 V (unless otherwise noted) TJ = 25°C Q1A, Q1B, Q2A, Q2B ∆VGS = 1 V (unless otherwise noted) TJ = 25°C Q3A, Q3B, Q4A, Q4B, Q5A, Q5B 4 3 VGS = 5 V 2 1 VGS = 3 V 0 0 2 3 4 5 6 7 8 9 VDS – Drain-to-Source Voltage – V 10 0 7 8 9 2 3 4 5 6 VDS – Drain-to-Source Voltage – V 1 Figure 11 DISTRIBUTION OF FORWARD TRANSCONDUCTANCE DISTRIBUTION OF FORWARD TRANSCONDUCTANCE 15 gfs – Forward Transconductance – S 0.97 0.96 0.95 3.5 3.4 3.3 3.2 3.1 3 2.9 0 2.8 0 2.7 5 2.6 5 0.94 10 0.93 10 20 0.9 15 25 Total Number of Units = 1200 VDS = 14 V TJ = 25°C ID = 750 mA Q3A, Q3B, Q4A, Q4B, Q5A, Q5B 0.89 Percentage of Units – % 30 20 2.5 Percentage of Units – % 25 35 Total Number of Units = 1200 VDS = 14 V TJ = 25°C ID = 1.5 A Q1A, Q1B, Q2A, Q2B 0.88 35 30 10 Figure 12 0.92 1 0.91 0 gfs – Forward Transconductance – S Figure 13 Figure 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TPIC1501A QUAD AND HEX POWER DMOS ARRAY SLIS046A – MAY 1995 – REVISED JUNE 1996 TYPICAL CHARACTERISTICS DRAIN CURRENT vs GATE-TO-SOURCE VOLTAGE DRAIN CURRENT vs GATE-TO-SOURCE VOLTAGE 12 6 TJ = – 40°C 11 TJ = 25°C 9 TJ = 75°C 8 TJ = 125°C 7 Q1A, Q1B, Q2A, Q2B 6 TJ = 25°C 5 TJ = 150°C 5 4 3 TJ = 125°C TJ = 75°C I D – Drain Current – A 10 I D – Drain Current – A TJ = – 40°C TJ = 150°C 4 3 2 Q3A, Q3B, Q4A, Q4B, Q5A, Q5B 1 2 1 0 0 0 1 2 3 4 5 0 6 2 VGS – Gate-to-Source Voltage – V 4 Figure 15 10 12 14 CAPACITANCE vs DRAIN-TO-SOURCE VOLTAGE 500 150 VGS = 0 f = 1 MHz TJ = 25°C Q1A, Q1B, Q2A, Q2B 450 400 135 350 300 Ciss 250 Coss 200 Coss 120 Capacitance – pF Capacitance – pF 8 Figure 16 CAPACITANCE vs DRAIN-TO-SOURCE VOLTAGE 105 Ciss 90 Crss 75 60 VGS = 0 f = 1 MHz TJ = 25°C Q3A, Q3B, Q4A, Q4B, Q5A, Q5B 45 Crss 150 30 100 15 50 0 2 4 6 8 10 12 14 16 0 0 2 VDS – Drain-to-Source Voltage – V 4 6 8 Figure 18 POST OFFICE BOX 655303 10 12 VDS – Drain-to-Source Voltage – V Figure 17 12 6 VGS – Gate-to-Source Voltage – V • DALLAS, TEXAS 75265 14 16 TPIC1501A QUAD AND HEX POWER DMOS ARRAY SLIS046A – MAY 1995 – REVISED JUNE 1996 TYPICAL CHARACTERISTICS SOURCE-TO-DRAIN DIODE CURRENT vs SOURCE-TO-DRAIN VOLTAGE SOURCE-TO-DRAIN DIODE CURRENT vs SOURCE-TO-DRAIN VOLTAGE 10 I SD – Source-to-Drain Diode Current – A VGS = 0 Q1A, Q1B, Q2A, Q2B 6 4 2 1 0.6 TJ = 125°C TJ = – 40°C 0.4 TJ = 150°C TJ = 25°C 0.2 TJ = 75°C VGS = 0 Q3A, Q3B, Q4A, Q4B, Q5A, Q5B 6 4 2 1 0.6 TJ = 125°C TJ = – 40°C 0.4 TJ = 150°C TJ = 25°C 0.2 TJ = 75°C 0.1 0.1 0.1 10 1 VSD – Source-to-Drain Voltage – V Figure 19 Figure 20 DRAIN-TO-SOURCE VOLTAGE AND GATE-TO-SOURCE VOLTAGE vs GATE CHARGE DRAIN-TO-SOURCE VOLTAGE AND GATE-TO-SOURCE VOLTAGE vs GATE CHARGE 14 16 16 14 14 12 12 VDD = 10 V 10 10 8 8 6 6 VDD = 12 V 4 4 VDD = 14 V 2 2 VDD = 12 V 0 0 0 1 2 3 4 5 6 7 VDS – Drain-to-Source Voltage – V ID = 1.5 A TJ = 25°C Q1A, Q1B, Q2A, Q2B See Figure 4 VGS – Gate-to-Source Voltage – V 16 10 1 VSD – Source-to-Drain Voltage – V 16 ID = 0.75 A TJ = 25°C Q3A, Q3B, Q4A, Q4B, Q5A, Q5B See Figure 4 VDD = 14 V 12 14 12 10 10 VDD = 10 V 8 8 6 6 VDD = 12 V 4 4 VDD = 14 V VDD = 12 V 2 VGS – Gate-to-Source Voltage – V 0.1 VDS – Drain-to-Source Voltage – V I SD – Source-to-Drain Diode Current – A 10 2 0 0 0 0.2 0.4 Qg – Gate Charge – nC 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Qg – Gate Charge – nC Figure 21 Figure 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TPIC1501A QUAD AND HEX POWER DMOS ARRAY SLIS046A – MAY 1995 – REVISED JUNE 1996 TYPICAL CHARACTERISTICS REVERSE RECOVERY TIME vs REVERSE di/dt trr – Reverse Recovery Time – ns 100 TJ = 25°C See Figures 1 and 2 80 IS = 1.5 A Q1A, Q2A 60 IS = 750 mA Q3A, Q4A, Q5A 40 20 0 0 100 200 300 400 Reverse di/dt – A/µs Figure 23 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 500 TPIC1501A QUAD AND HEX POWER DMOS ARRAY SLIS046A – MAY 1995 – REVISED JUNE 1996 THERMAL INFORMATION MAXIMUM DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE 100 I D – Maximum Drain Current – A TC = 25°C Q1A, Q1B, Q2A, Q2B 500 µs† 10 10 ms† 1 ms† 1 ÁÁ ÁÁ θJP§ θJA‡ DC Conditions 0.1 0.1 1 10 100 VDS – Drain-to-Source Voltage – V Figure 24 MAXIMUM DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE 100 I D – Maximum Drain Current – A TC = 25°C Q3A, Q3B, Q4A, Q4B, Q5A, Q5B ÁÁ ÁÁ 10 10 ms† 1 θJP§ DC Conditions 0.1 0.1 θJA‡ 1 10 100 VDS – Drain-to-Source Voltage – V Figure 25 † Less than 10% duty cycle ‡ Device is mounted on a 24 in2, 4 layer FR4 printed-circuit board. § Device is mounted in intimate contact with infinite heat sink. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TPIC1501A QUAD AND HEX POWER DMOS ARRAY SLIS046A – MAY 1995 – REVISED JUNE 1996 THERMAL INFORMATION DW PACKAGE† JUNCTION-TO-BOARD THERMAL RESISTANCE vs PULSE DURATION 100 RθJB – Junction-to-Board Thermal Resistance – °C/W DC Conditions d = 0.5 10 d = 0.2 d = 0.1 d = 0.05 d = 0.02 1 d = 0.01 tc tw Single Pulse ID 0 0.1 0.0001 0.001 0.01 0.1 tw – Pulse Duration – s † Device is mounted on 24 in2, 4-layer FR4 printed-circuit board with no heat sink. NOTE A: ZθB(t) = r(t) RθJB tw = pulse duration tc = cycle time d = duty cycle = tw/tc Figure 26 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 10 100 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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