UCC27322-EP www.ti.com SLUSAA1 – SEPTEMBER 2010 SINGLE 9-A HIGH-SPEED LOW-SIDE MOSFET DRIVER WITH ENABLE Check for Samples: UCC27322-EP FEATURES 1 • • • • • • • • Industry-Standard Pinout With Addition of Enable Function High-Peak Current Drive Capability of ±9 A at the Miller Plateau Region Using TrueDrive™ Efficient Constant Current Sourcing Using a Unique Bipolar and CMOS Output Stage TTL-/CMOS-Compatible Inputs Independent of Supply Voltage 20-ns Typical Rise and 15-ns Typical Fall Times With 10-nF Load Typical Propagation Delay Times of 25 ns With Input Falling and 35 ns With Input Rising 4-V to 15-V Supply Voltage Pb-Free Finish (NiPdAu) SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS • • • • • • • Controlled Baseline One Assembly/Test Site One Fabrication Site Rated From –40°C to 105°C Extended Product Life Cycle Extended Product-Change Notification Product Traceability APPLICATIONS • • • • • • Switch-Mode Power Supplies DC/DC Converters Motor Controllers Line Drivers Class D Switching Amplifiers Pulse Transformer Driver DGK PACKAGE (TOP VIEW) VDD IN ENBL AGND 1 8 2 7 3 6 4 5 VDD OUT OUT PGND DESCRIPTION The UCC27322 delivers 9 A of peak drive current in an industry standard pinout. These drivers can drive the largest of MOSFETs for systems requiring extreme Miller current due to high dV/dt transitions. This eliminates additional external circuits and can replace multiple components to reduce space, design complexity and assembly cost. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated UCC27322-EP SLUSAA1 – SEPTEMBER 2010 VDD www.ti.com 1 8 7 VDD INPUT/OUTPUT TABLE ENBL IN OUT 0 0 0 0 1 0 1 0 0 1 1 1 OUT VDD 2 IN ENBL 3 AGND 4 6 OUT 5 PGND RENBL 100 kΩ Using a design that inherently minimizes shoot-through current, the outputs of these can provide high gate drive current where it is most needed at the Miller plateau region during the MOSFET switching transition. A unique hybrid output stage paralleling bipolar and MOSFET transistors (TrueDrive) allows efficient current delivery at low supply voltages. With this drive architecture, UCC27322 can be used in industry standard 6-A, 9-A and many 12-A driver applications. Latch up and ESD protection circuits are also included. Finally, the UCC27322 provides an enable (ENBL) function to have better control of the operation of the driver applications. ENBL is implemented on pin 3 which was previously left unused in the industry standard pin-out. It is internally pulled up to VDD for active high logic and can be left open for standard operation. ORDERING INFORMATION (1) PACKAGE (2) TA = TJ –40°C to 105°C (1) DGK Reel of 2500 ORDERABLE PART NUMBER TOP-SIDE MARKING UCC27322TDGKREP QTK For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. (2) Table 1. TERMINAL FUNCTIONS TERMINAL 2 I/O DESCRIPTION NO. NAME 4 AGND — 3 ENBL I Enable input for the driver with logic compatible threshold and hysteresis. The driver output can be enabled and disabled with this pin. It is internally pulled up to VDD with 100-kΩ resistor for active high operation. The output state when the device is disabled will be low regardless of the input state. 2 IN I Input signal of the driver which has logic compatible threshold and hysteresis. 6, 7 OUT O Driver outputs that must be connected together externally. The output stage is capable of providing 9-A peak drive current to the gate of a power MOSFET. 5 PGND — Common ground for output stage. This ground should be connected very closely to the source of the power MOSFET which the driver is driving. Grounds are separated to minimize ringing affects due to output switching di/dt which can affect the input threshold. 1, 8 VDD I Common ground for input stage. This ground should be connected very closely to the source of the power MOSFET which the driver is driving. Grounds are separated to minimize ringing affects due to output switching di/dt which can affect the input threshold. Supply voltage and the power input connections for this device. Three pins must be connected together externally. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated UCC27322-EP www.ti.com SLUSAA1 – SEPTEMBER 2010 ABSOLUTE MAXIMUM RATINGS (1) (2) over operating free-air temperature range (unless otherwise noted) VDD Supply voltage IO Output current, OUT VI Input voltage –0.3 V to 16 V 0.6 A IN -5 V to 6 V or VDD + 0.3 V (whichever is larger) ENBL -5 V to 6 V or VDD + 0.3 V (whichever is larger) PD Power dissipation at TA = 25°C 3W TJ Junction operating temperature –40°C to 105°C Tstg Storage temperature –65°C to 150°C (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive into and negative out of the specified terminal. POWER DISSIPATION RATINGS (1) (2) PACKAGE qJC (°C/W) qJA (°C/W) POWER RATING (1) TA = 70°C (mW) DERATING FACTOR (1) TA > 70°C (mW/°C) DGK 78 172 (2) 319 5.8 125°C operating junction temperature is used for power rating calculations qJA given for High-K PCB board. OVERALL ELECTRICAL CHARACTERISTICS VDD = 4.5 V to 15 V, TJ = TA = –40°C to 105°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN IN = Low, ENBL = High, VDD = 15 V IDD Static operating current IN = High, ENBL = High, VDD = 15 V TYP MAX 150 225 450 650 75 125 675 1000 TYP MAX UNIT µA INPUT (IN) ELECTRICAL CHARACTERISTICS VDD = 4.5 V to 15 V, TJ = TA = –40°C to 105°C (unless otherwise noted) PARAMETER VIH Logic 1 input threshold VIL Logic 0 input threshold Input current Latch-up protection (1) (1) TEST CONDITIONS MIN 2 0 V ≤ VIN ≤ VDD –10 UNIT V 0 1 V 10 µA 500 mA Specified by design Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 3 UCC27322-EP SLUSAA1 – SEPTEMBER 2010 www.ti.com OUTPUT (OUT) ELECTRICAL CHARACTERISTICS VDD = 4.5 V to 15 V, TJ = TA = –40°C to 105°C (unless otherwise noted) PARAMETER Peak output current (1) TEST CONDITIONS (2) MIN VDD = 14 V TYP MAX 9 UNIT A VOH High-level output voltage VOH = VDD – VOUT, IOUT = –10 mA 150 300 mV VOL Low-level output voltage IOUT = 10 mA 11 25 mV Output resistance high (3) IOUT = –10 mA, VDD = 14 V 15 25 Ω Output resistance low (3) IOUT = 10 mA, VDD = 14 V 1.1 2.5 Ω Latch-up protection (1) (2) (3) (1) 500 mA Specified by design The pullup/pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The pulsed output current rating is the combined current from the bipolar and MOSFET transistors. The pullup/pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the RDS(ON) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. ENABLE (ENBL) ELECTRICAL CHARACTERISTICS VDD = 4.5 V to 15 V, TJ = TA = –40°C to 105°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VEN_H Enable rising threshold voltage Low to high transitions 1.7 2.2 2.7 V VEN_L Enable falling threshold voltage High to low transition 1.1 1.6 2 V 0.25 0.55 0.90 V 75 100 135 kΩ Hysteresis R(ENBL) Enable impedance VDD = 14 V, ENBL = Low tD3 Propagation delay time CLOAD = 10 nF (see Figure 2) 60 90 ns tD4 Propagation delay time CLOAD = 10 nF (see Figure 2) 60 90 ns SWITCHING CHARACTERISTICS VDD = 4.5 V to 15 V, TJ = TA = –40°C to 105°C (unless otherwise noted) (see Figure 2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tR Rise time (OUT) CLOAD = 10 nF 20 70 ns tF Fall time (OUT) CLOAD = 10 nF 20 30 ns tD1 Delay time, IN rising (IN to OUT) CLOAD = 10 nF 25 70 ns tD2 Delay time, IN falling (IN to OUT) CLOAD = 10 nF 35 70 ns 4 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated UCC27322-EP www.ti.com SLUSAA1 – SEPTEMBER 2010 10000.00 Wirebond Voiding Fail Mode Estimated Life (Years) 1000.00 100.00 Electromigration Fail Mode 10.00 1.00 0.10 80 90 100 110 120 130 140 150 160 Continuous TJ (°C) Notes: 1. See data sheet for absolute maximum and minimum recommended operating conditions. 2. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life). 3. Enhanced plastic product disclaimer applies. 4. Electromigration calculation is based on operating the part at 2.5 MHz at a 50% duty cycle. Figure 1. UCC27322 Operating Life Derating Chart Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 5 UCC27322-EP SLUSAA1 – SEPTEMBER 2010 www.ti.com (a) (b) 5V IN VTH 0V tD1 VTH IN VTH tD2 VTH tD1 tD2 tF VDD 80% 80% 80% tR OUT 80% tR OUT 20% tF 20% 0V A. The 20% and 80% thresholds depict the dynamics of the Bipolar output devices that dominate the power MOSFET transition through the Miller regions of operation. Figure 2. Switching Waveforms for (a) Inverting Driver and (b) Noninverting Driver 5V ENBL VIN_L VIN_H 0V tD3 tD4 VDD 80% 80% tR OUT tF 20% 0V A. The 20% and 80% thresholds depict the dynamics of the Bipolar output devices that dominate the power MOSFET transition through the Miller regions of operation. Figure 3. Switching Waveforms for Enable to Output 6 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated UCC27322-EP www.ti.com SLUSAA1 – SEPTEMBER 2010 TYPICAL CHARACTERISTICS INPUT CURRENT IDLE vs TEMPERATURE (UCCx7322) INPUT CURRENT IDLE vs SUPPLY VOLTAGE (UCCx7322) 700 800 ENBL = 0 V IN = 5 V 500 IDD − Input Current Idle − µA IDD − Input Current Idle − µA ENBL = HI IN = HI 700 600 400 ENBL = 0 V IN = 0 V 300 ENBL = VDD IN = 5 V 200 ENBL = VDD, IN = 0 V 600 ENBL = LO IN = HI 500 400 ENBL = LO IN = LO 300 ENBL = HI IN = LO 200 100 100 0 0 2 4 6 8 10 12 VDD − Supply Voltage − V 14 0 −50 16 −25 0 25 50 75 TJ −Temperature − °C Figure 4. 100 125 Figure 5. RISE TIME vs SUPPLY VOLTAGE FALL TIME vs SUPPLY VOLTAGE 70 70 CLOAD = 10 nF 60 60 tA = −40°C 50 tF − Fall Time − ns tR − Rise Time − ns 50 40 tA = 105°C tA = 25°C 30 20 40 30 tA = 105°C tA = 25°C 20 tA = 0°C 10 10 0 4 6 8 10 12 14 16 tA = 0°C tA = −40°C 0 VDD − Supply Voltage − V 8 10 12 VDD − Supply Voltage − V Figure 6. Figure 7. Copyright © 2010, Texas Instruments Incorporated 4 6 14 Submit Documentation Feedback 16 7 UCC27322-EP SLUSAA1 – SEPTEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) RISE TIME vs LOAD CAPACITANCE 40 FALL TIME vs OUTPUT CAPACITANCE 200 VDD = 5 V VDD = 5 V 160 VDD = 10 V tF − Fall Time − ns tR − Rise Time − ns 30 VDD = 10 V VDD = 15 V 20 VDD = 15 V 120 80 10 40 0 0 1 10 1 100 10 CLOAD − Load Capacitance − nF CLOAD − Load Capacitance − nF Figure 8. Figure 9. tD1 DELAY TIME vs SUPPLY VOLTAGE tD2 DELAY TIME vs SUPPLY VOLTAGE 100 70 70 CLOAD = 10 nF CLOAD = 10 nF 60 tA = 105°C 60 tA = 25°C 50 50 tD2 − Delay Time − ns tD1 − Delay Time − ns tA = 105°C tA = 25°C 40 30 20 40 30 tA = 0°C 20 tA = −40°C tA = −40°C 10 10 tA = 0°C 0 0 4 8 6 8 10 12 14 16 4 6 8 10 12 VDD − Supply Voltage − V VDD − Supply Voltage − V Figure 10. Figure 11. Submit Documentation Feedback 14 16 Copyright © 2010, Texas Instruments Incorporated UCC27322-EP www.ti.com SLUSAA1 – SEPTEMBER 2010 TYPICAL CHARACTERISTICS (continued) tD2 DELAY TIME vs LOAD CAPACITANCE tD1 DELAY TIME vs LOAD CAPACITANCE 70 70 VDD = 5 V 60 50 tD2 − Delay Time − ns tD1 − Delay Time − ns 60 VDD = 10 V VDD = 5 V 40 30 20 50 40 30 VDD = 15 V 20 VDD = 15 V 10 10 0 1 10 0 100 1 CLOAD − Load Capacitance − nF 10 CLOAD − Load Capacitance − nF Figure 12. tD2 40 Propagation Time − ns tRISE 35 30 25 20 15 10 tFALL tD1 INPUT THRESHOLD vs TEMPERATURE 2.0 VDD = 15 V CLOAD = 10 nF TA = 25°C VON − Input Threshold Voltage − V 45 100 Figure 13. PROPAGATION TIMES vs PEAK INPUT VOLTAGE 50 VDD = 10 V 1.9 VDD = 15 V 1.8 1.7 1.6 1.5 VDD = 10 V VDD = 4.5 V 1.4 1.3 5 0 0 5 10 VIN(peak) − Peak Input Voltage − V Figure 14. Copyright © 2010, Texas Instruments Incorporated 15 1.2 −50 −25 0 25 50 75 100 125 TJ − Temperature − °C Figure 15. Submit Documentation Feedback 9 UCC27322-EP SLUSAA1 – SEPTEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) ENABLE THRESHOLD AND HYSTERESIS vs TEMPERATURE ENABLE RESISTANCE vs TEMPERATURE 3.0 150 140 130 RENBL − Enable Resistance − Ω Enable threshold and hysteresis − V ENBL − ON 2.5 2.0 1.5 1.0 ENBL − OFF 120 110 100 0.5 ENBL − HYSTERESIS 0 −50 −25 90 80 70 60 0 25 50 75 TJ − Temperature − °C 100 50 −50 125 −25 0 25 50 Figure 16. Figure 17. OUTPUT BEHAVIOR vs VDD (UCC37322) OUTPUT BEHAVIOR vs VDD (UCC37322) OUT 0V 10 100 125 IN = VDD ENBL = VDD VDD − Input Voltage − V 1 V/div VDD − Input Voltage − V 1 V/div IN = VDD ENBL = VDD VDD 75 TJ − Temperature − °C VDD OUT 0V 10 nF Between Output and GND 50 µs/div 10 nF Between Output and GND 50 µs/div Figure 18. Figure 19. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated UCC27322-EP www.ti.com SLUSAA1 – SEPTEMBER 2010 TYPICAL CHARACTERISTICS (continued) OUTPUT BEHAVIOR vs VDD (NON-INVERTING) OUTPUT BEHAVIOR vs VDD (NON-INVERTING) IN = GND ENBL = VDD VDD OUT 0V VDD − Supply Voltage − V 1 V/div VDD − Supply Voltage − V 1 V/div IN = GND ENBL = VDD VDD OUT 0V 10 nF Between Output and GND 50 µs/div Figure 20. Copyright © 2010, Texas Instruments Incorporated 10 nF Between Output and GND 50 µs/div Figure 21. Submit Documentation Feedback 11 UCC27322-EP SLUSAA1 – SEPTEMBER 2010 www.ti.com APPLICATION INFORMATION General Information The UCC27322 driver serves as an interface between low-power controllers and power MOSFETs. It can also be used as an interface between DSPs and power MOSFETs. High-frequency power supplies often require high-speed, high-current drivers such as the UCC27322. A leading application is the need to provide a high power buffer stage between the PWM output of the control device and the gates of the primary power MOSFET or IGBT switching devices. In other cases, the device drives the power device gates through a drive transformer. Synchronous rectification supplies also have the need to simultaneously drive multiple devices which can present an extremely large load to the control circuitry. MOSFET gate drivers are generally used when it is not feasible to have the primary PWM regulator device directly drive the switching devices for one or more reasons. The PWM device may not have the brute drive capability required for the intended switching MOSFET, limiting the switching performance in the application. In other cases there may be a desire to minimize the effect of high frequency switching noise by placing the high current driver physically close to the load. Also, newer devices that target the highest operating frequencies may not incorporate onboard gate drivers at all. Their PWM outputs are only intended to drive the high impedance input to a driver such as the UCC27322. Finally, the control device may be under thermal stress due to power dissipation, and an external driver can help by moving the heat from the controller to an external package. Input Stage The IN threshold has a 3.3-V logic sensitivity over the full range of VDD voltages; yet, it is equally compatible with 0 V to VDD signals. The inputs of UCC27322 driver is designed to withstand 500-mA reverse current without either damage to the device or logic upset. In addition, the input threshold turn-off of the UCC27322 has been slightly raised for improved noise immunity. The input stage of each driver should be driven by a signal with a short rise or fall time. This condition is satisfied in typical power supply applications, where the input signals are provided by a PWM controller or logic gates with fast transition times (<200 ns). The IN input of the driver functions as a digital gate, and it is not intended for applications where a slow changing input voltage is used to generate a switching output when the logic threshold of the input section is reached. While this may not be harmful to the driver, the output of the driver may switch repeatedly at a high frequency. Users should not attempt to shape the input signals to the driver in an attempt to slow down (or delay) the signal at the output. If limiting the rise or fall times to the power device is desired, then an external resistance can be added between the output of the driver and the load device, which is generally a power MOSFET gate. The external resistor may also help remove power dissipation from the device package. Output Stage The TrueDrive output stage is capable of supplying ±9-A peak current pulses and swings to both VDD and GND and can encourage even the most stubborn MOSFETs to switch. The pull-up/pull-down circuits of the driver are constructed of bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the RDS(ON) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. Each output stage also provides a very low impedance to overshoot and undershoot due to the body diode of the internal MOSFET. This means that in many cases, external-schottky-clamp diodes are not required. This unique Bipolar and MOSFET hybrid output architecture (TrueDrive) allows efficient current sourcing at low supply voltages. The UCC27322 delivers 9 A of gate drive where it is most needed during the MOSFET switching transition – at the Miller plateau region – providing improved efficiency gains. Source/Sink Capabilities During Miller Plateau Large power MOSFETs present a large load to the control circuitry. Proper drive is required for efficient, reliable operation. The UCC27322 driver has been optimized to provide maximum drive to a power MOSFET during the Miller plateau region of the switching transition. This interval occurs while the drain voltage is swinging between the voltage levels dictated by the power topology, requiring the charging/discharging of the drain-gate capacitance with current supplied or removed by the driver. 12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated UCC27322-EP www.ti.com SLUSAA1 – SEPTEMBER 2010 Two circuits are used to test the current capabilities of the UCC27322 driver. In each case, external circuitry is added to clamp the output near 5 V while the device is sinking or sourcing current. An input pulse of 250 ns is applied at a frequency of 1 kHz in the proper polarity for the respective test. In each test, there is a transient period when the current peaked up and then settled down to a steady-state value. The noted current measurements are made at a time of 200 ns after the input pulse is applied, after the initial transient. The circuit in Figure 22 is used to verify the current sink capability when the output of the driver is clamped at approximately 5 V, a typical value of gate-source voltage during the Miller plateau region. The UCC27322 is found to sink 9 A at VDD = 15 V. VDD UCC27322 INPUT 1 VDD VDD 8 IN DSCHOTTKY OUT 2 10Ω 7 C2 1 µF OUT 3 ENBL 6 4 AGND PGND 5 C3 + 100 µF VSUPPLY 5.5 V VSNS 1 µF CER 100 µF AL EL RSNS 0.1 Ω Figure 22. Sink Current Test Circuit The circuit in Figure 23 is used to test the current source capability with the output clamped to approximately 5 V with a string of Zener diodes. The UCC27322 is found to source 9 A at VDD = 15 V. VDD UCC27322 INPUT 1 VDD VDD 8 IN OUT DSCHOTTKY 2 7 C2 1 µF OUT 3 4 ENBL AGND 6 C3 100 µF 4.5 V DADJ PGND 5 VSNS 1 µF CER 100 µF AL EL RSNS 0.1 Ω Figure 23. Source Current Test Circuit It should be noted that the current-sink capability is slightly stronger than the current source capability at lower VDD. This is due to the differences in the structure of the bipolar-MOSFET power output section, where the current source is a P-channel MOSFET and the current sink has an N-channel MOSFET. In a large majority of applications, it is advantageous that the turn-off capability of a driver is stronger than the turn-on capability. This helps to ensure that the MOSFET is held off during common power-supply transients that may turn the device back on. Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 13 UCC27322-EP SLUSAA1 – SEPTEMBER 2010 www.ti.com Operational Circuit Layout It can be a significant challenge to avoid the overshoot/undershoot and ringing issues that can arise from circuit layout. The low impedance of these drivers and their high di/dt can induce ringing between parasitic inductances and capacitances in the circuit. Utmost care must be used in the circuit layout. In general, position the driver physically as close to its load as possible. Place a 1-µF bypass capacitor as close to the output side of the driver as possible, connecting it to pins 1 and 8. Connect a single trace between the two VDD pins (pin 1 and pin 8); connect a single trace between PGND and AGND (pin 5 and pin 4). If a ground plane is used, it may be connected to AGND; do not extend the plane beneath the output side of the package (pins 5 - 8). Connect the load to both OUT pins (pins 7 and 6) with a single trace on the adjacent layer to the component layer; route the return current path for the output on the component side, directly over the output path. Extreme conditions may require decoupling the input power and ground connections from the output power and ground connections. The UCC27322 has a feature that allows the user to take these extreme measures, if necessary. There is a small amount of internal impedance of about 15 Ω between the AGND and PGND pins; there is also a small amount of impedance (∼30 Ω) between the two VDD pins. In order to take advantage of this feature, connect a 1-µF bypass capacitor between VDD and PGND (pins 5 and 8) and connect a 0.1-µF bypass capacitor between VDD and AGND (pins 1 and 4). Further decoupling can be achieved by connecting between the two VDD pins with a jumper that passes through a 40-MHz ferrite bead and connect bias power only to pin 8. Even more decoupling can be achieved by connecting between AGND and PGND with a pair of anti-parallel diodes (anode connected to cathode and cathode connected to anode). VDD Although quiescent VDD current is very low, total supply current is higher, depending on OUT current and the programmed oscillator frequency. Total VDD current is the sum of quiescent VDD current and the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT current can be calculated from: IOUT = Qg × f Where f is frequency For the best high-speed circuit performance, two VDD bypass capacitors are recommended to prevent noise problems. The use of surface-mount components is highly recommended. A 0.1-µF ceramic capacitor should be located closest to the VDD to ground connection. In addition, a larger capacitor (such as 1-µF) with relatively low ESR should be connected in parallel, to help deliver the high current peaks to the load. The parallel combination of capacitors should present a low-impedance characteristic for the expected current levels in the driver application. Drive Current and Power Requirements The UCC27322 is capable of delivering 9-A of current to a MOSFET gate for a period of several hundred nanoseconds. High peak current is required to turn an N-channel device ON quickly. Then, to turn the device OFF, the driver is required to sink a similar amount of current to ground. This repeats at the operating frequency of the power device. An N-channel MOSFET is used in this discussion because it is the most common type of switching device used in high frequency power conversion equipment. References 1 and 2 contain detailed discussions of the drive current required to drive a power MOSFET and other capacitive-input switching devices. Much information is provided in tabular form to give a range of the current required for various devices at various frequencies. The information pertinent to calculating gate drive current requirements are summarized here; the original document is available from the TI web site (www.ti.com). When a driver is tested with a discrete capacitive load, it is a fairly simple matter to calculate the power that is required from the bias supply. The energy that must be transferred from the bias supply to charge the capacitor is given by: E = ½CV2 Where C is the load capacitor and V is the bias voltage feeding the driver 14 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated UCC27322-EP www.ti.com SLUSAA1 – SEPTEMBER 2010 There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to a power loss given by: P = 2 × ½CV2f Where f is the switching frequency This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the driver and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is charged, and the other half is dissipated when the capacitor is discharged. An actual example using the conditions of the previous gate drive waveform should help clarify this. With VDD = 12 V, CLOAD = 10 nF, and f = 300 kHz, the power loss can be calculated as: P = 10 nF × (12)2 × (300 kHz) = 0.432 W With a 12-V supply, this equates to a current of: I = P / V = 0.432 W / 12 V = 0.036 A The switching load presented by a power MOSFET can be converted to an equivalent capacitance by examining the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the added charge needed to swing the drain of the device between the on and off states. Most manufacturers provide specifications that provide the typical and maximum gate charge, in nC, to switch the device under specified conditions. Using the gate charge Qg, one can determine the power that must be dissipated when charging a capacitor. This is done by using the equivalence Qg = CeffV to provide the following equation for power: P = C × V2 × f = Qg × V × f This equation allows a power designer to calculate the bias power required to drive a specific MOSFET gate at a specific bias voltage. ENABLE UCC27322 provides an Enable input for improved control of the driver operation. This input also incorporates logic compatible thresholds with hysteresis. It is internally pulled up to VDD with 100-kΩ resistor for active high operation. When ENBL is high, the device is enabled and when ENBL is low, the device is disabled. The default state of the ENBL pin is to enable the device and therefore can be left open for standard operation. The output state when the device is disabled is low regardless of the input state. See the truth table below for the operation using enable logic. ENBL input is compatible with both logic signals and slow changing analog signals. It can be directly driven or a power-up delay can be programmed with a capacitor between ENBL and AGND. Table 2. Input/Ouput Table UCC27322 ENBL IN OUT 0 0 0 0 1 0 1 0 0 1 1 1 References 1. Power Supply Seminar SEM-1400 Topic 2: Design And Application Guide For High Speed MOSFET Gate Drive Circuits, Laszlo Balogh (SLUP133) 2. Practical Considerations in High Performance MOSFET, IGBT and MCT Gate Drive Circuits, Bill Andreycak (SLUA105) 3. PowerPad Thermally Enhanced Package (SLMA002) 4. PowerPAD Made Easy (SLMA004) Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 15 UCC27322-EP SLUSAA1 – SEPTEMBER 2010 www.ti.com Related Products Table 3. Related Products PRODUCT DESCRIPTION PACKAGES UCC37323/4/5 Dual 4-A Low-Side Drivers MSOP-8 PowerPAD, SOIC-8, PDIP-8 UCC27423/4/5 Dual 4-A Low-Side Drivers with Enable MSOP-8 PowerPAD, SOIC-8, PDIP-8 TPS2811/12/13 Dual 2-A Low-Side Drivers with Internal Regulator TSSOP-8, SOIC-8, PDIP-8 TPS2814/15 Dual 2-A Low-Side Drivers with Two Inputs per Channel TSSOP-8, SOIC-8, PDIP-8 TPS2816/17/18/19 Single 2-A Low-Side Driver with Internal Regulator 5-Pin SOT-23 TPS2828/29 Single 2-A Low-Side Driver 5-Pin SOT-23 16 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 4-Oct-2010 PACKAGING INFORMATION Orderable Device UCC27322TDGKREP Status (1) ACTIVE Package Type Package Drawing MSOP DGK Pins Package Qty 8 2500 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) Purchase Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF UCC27322-EP : • Catalog: UCC27322 • Automotive: UCC27322-Q1 NOTE: Qualified Version Definitions: Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 4-Oct-2010 • Catalog - TI's standard catalog product • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 8-Oct-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device UCC27322TDGKREP Package Package Pins Type Drawing MSOP DGK 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 3.4 1.4 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Oct-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC27322TDGKREP MSOP DGK 8 2500 346.0 346.0 29.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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