UCD7230A www.ti.com SLUS995 – NOVEMBER 2009 Digital Control Compatible Synchronous Buck Gate Driver with Current Sense Conditioning Amplifier Check for Samples: UCD7230A FEATURES APPLICATIONS • • 1 2 • • • • • • • • • Input from Digital Controller Sets Operating Frequency and Duty Cycle Up to 2-MHz Switching Frequency Dual Current Limit Protection with Independently Adjustable Thresholds Fast Current Sense Circuit with Adjustable Blanking Interval Prevents Catastrophic Current Levels Digital Output Current Limit Flag Low Offset, Gain of 48, Differential Current Sense Amplifier 3.3-V, 10-mA Internal Regulator Dual TrueDrive™ High-Current Drivers 10-ns Typical Rise/Fall Times with 2.2-nF Loads 4.5-V to 15.5-V Supply Voltage Range • • • Digitally-Controlled Synchronous-Buck Power Stages for Single and Multi-Phase Applications Especially Suited for Use with UCD91xx or UCD92xx Contollers High-Current Multi-Phase VRM/EVRD Regulators for Desktop, Server, Telecom and Notebook Processors Digitally-Controlled Synchronous-Buck Power Supplies Using μCs or the TMS320™ DSP Family DESCRIPTION The UCD7230A is one in the UCD7k family of digital control compatible drivers for applications utilizing digital control techniques or applications requiring fast local peak current limit protection. The UCD7230A is a MOSFET gate driver specifically designed for synchronous buck applications. It is ideally suited to provide the bridge between digital controllers such as the UCD91xx or the UCD92xx and the power stage. With cycle-by-cycle current limit protection, the UCD7230A device protects the power stage from faulty input signals or excessive load currents. VIN VOUT 18 16 17 VDD CSBIAS CS+ BIAS 1 2 13 14 BST OUT1 15 SW 3V3 AGND UCD7230A IMAX 4 ILIM CLF 5 CLF 12 11 10 PVDD OUT2 PGND POS 8 NEG 9 AO 7 ILOAD IN 20 PWM SRE 19 IO 6 DLY 3 SRE IDLY UDG-09162 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TMS320, TrueDrive are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated UCD7230A SLUS995 – NOVEMBER 2009 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DESCRIPTION (CONTINUED) The UCD7230A includes high-side and low-side gate drivers which utilize Texas Instrument’s TrueDrive™ output architecture. This architecture delivers rated current into the gate capacitance of a MOSFET during the Miller plateau region of the switching. Furthermore, the UCD7230A offers a low offset differential amplifier with a fixed gain of 48. This amplifier greatly simplifies the task of conditioning small current sense signals inherent in high efficiency buck converters. The UCD7230A includes a 3.3-V, 10-mA linear regulator to provide power to digital controllers such as the UCD91xx. The UCD7230A is compatible with standard 3.3-V I/O ports of the UCD91xx, the TMS320™ family DSPs, microprocessors, or ASICs. The UCD7230A is offered in the space-saving QFN package. Package pin out has been carefully designed for optimal board layout ORDERING INFORMATION (1) TEMPERATURE RANGE -40°C to + 125°C (1) (2) 2 PACKAGED DEVICES QFN-20 (RGW) (2) PACKAGE QUANTITY DELIVERY MEDIA DEVICE NUMBER 250 Small tape and reel UCD7230ARGWT 3000 Large tape and reel UCD7230ARGWR These products are packaged in Pb-Free and green lead finish of Pd-Ni-Au which is compatible with MSL level 1 between 255°C and 260°C peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations. QFN-20 (RGW) package is available taped and reeled only. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UCD7230A UCD7230A www.ti.com SLUS995 – NOVEMBER 2009 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN Input voltage Supply current Output gate drive voltage Output gate drive current MAX VDD 16 BST VSW+16 V VDD 20 OUT1 200 OUT1, BST -1 36 OUT2 -1 VVDD+0.3 OUT1 (sink) 4.0 OUT1 (source) -2.0 OUT2 (sink) 4.0 OUT2 (source) UNIT V mA V A -4.0 SW -1 20 CS+ -0.3 20 CSBIAS -0.3 16 POS, NEG -0.3 5.6 ILIM, DLY, I0 -0.3 3.6 Analog output A0 -0.3 3.6 Digital I/O’s IN, SRE, CLF -0.3 3.6 V 2 kV 500 V Analog input voltage Electrostatic discharge, human body model(HBM) Electrostatic discharge, charged device model (CDM) V Operating junction temperature, TJ -55 150 Storage temperature, Tstg -65 150 Lead temperature (soldering, 10 sec) (1) V °C 300 °C Stresses beyond those listed in this table may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. Consult company packaging information for thermal limitations and considerations of packages. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN TYP MAX 4.75 12 15 Switching Frequency 200 500 2000 kHz Operating ambient temperature -40 85 °C Input voltage TA VDD UNIT V DISSIPATION RATINGS TABLE (2 OZ. TRACE AND COPPER PAD WITH SOLDER) (1) (1) PACKAGE TA < 25°C POWER RATING (W) DERATING FACTOR ABOVE TA = 25°C (mW/°C) θJA (°C/W) 20-pin RGW 2.4 24.0 41.7 For more information on the RGW package and the test method, refer to TI technical brief, literature number SZZA017. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UCD7230A 3 UCD7230A SLUS995 – NOVEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS VDD = PVDD = 12 V, 4.7 μF from VDD to AGND, 1 μF from PVDD to PGND, 0.1 μF from CSBIAS to AGND, 0.22 μF from BST to SW, TA = TJ = -40°C to +125°C, RCS+ = 5 kΩ, RDLY = 50 kΩ over operating free-air temperature range (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY IVDD Supply current, off VDD = 4.2 V 4 5.2 mA IVDD Supply current Outputs not switching IN = LOW 5 8 mA LOW-VOLTAGE UNDER-VOLTAGE LOCKOUT VDD UVLO ON VDD rising 4.25 4.50 4.75 VDD UVLO OFF VDD falling 4.00 4.25 4.50 100 250 400 3.267 3.3 3.333 3.234 3.3 3.366 VDD UVLO hysteresis V mV REFERENCE / EXTERNAL BIAS SUPPLY 3V3 initial set point TA = 25°C 3V3 over temperature 3V3 load regulation ILOAD = 1 mA to 10 mA, VDD = 5V 1 7 3V3 line regulation VDD = 4.75 V to 12 V, ILOAD = 10 mA 3 10 Short circuit current VDD = 4.75 V to 12 V 11 3V3 OK threshold, ON 3.3 V rising 2.8 3 3.2 3V3 OK threshold, OFF 3.3 V falling 2.6 2.8 3.0 20 V mV mA V INPUT SIGNAL (IN) INHigh Positive-going input threshold voltage 1.6 1.9 2.2 INLow Negative-going input threshold voltage 1.0 1.3 1.6 INHigh – INLow Input voltage hysteresis 0.4 0.6 0.8 Input resistance to AGND 50 100 150 Frequency ceiling tMIN PWM minimum pulse width to force OUT1 gate pulse 2 V kΩ MHz CLOAD = 2.2 nF, VDD = 12 V 120 ns VILIM= OPEN 0.47 0.50 0.53 V 20 42 65 kΩ CURRENT LIMIT (ILIM) ILIM internal voltage setpoint ILIM input impedance CLF output high level ILOAD = 4 mA CLF output low level ILOAD = 4 mA Propagation delay from IN to reset CLF 2nd IN rising to CLF falling after a current limit event 2.7 0.6 15 35 V ns CURRENT SENSE COMPARATOR (OUTPUT SENSE) VCS (1) 4 CS threshold (POS - NEG) VILIM = open 40 50 60 VILIM = 3.3 V 80 100 120 VILIM = 0.75 V 60 75 90 VILIM = 0.25 V 15 25 35 Propagation delay from POS to OUT1 falling (1) VILIM = open, VCS = threshold + 60 mV 90 Propagation delay from POS to CLF (1) VILIM = open, VCS = threshold + 60 mV 100 mV ns As designed and characterized. Not 100% tested in production. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UCD7230A UCD7230A www.ti.com SLUS995 – NOVEMBER 2009 ELECTRICAL CHARACTERISTICS (continued) VDD = PVDD = 12 V, 4.7 μF from VDD to AGND, 1 μF from PVDD to PGND, 0.1 μF from CSBIAS to AGND, 0.22 μF from BST to SW, TA = TJ = -40°C to +125°C, RCS+ = 5 kΩ, RDLY = 50 kΩ over operating free-air temperature range (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX RDLY = 24.3 kΩ (CSBIAS-CS+) 170 235 300 RDLY = 49.9 kΩ (CSBIAS-CS+) 90 114 140 UNIT CURRENT SENSE COMPARATOR (INPUT SENSE) CS threshold CS blanking time (2) RDLY = 24.3 kΩ , IN rising to OUT1, IN falling to OUT2, VDD = 6 V 120 RDLY = 49.9 kΩ , IN rising to OUT1, IN falling to OUT2, VDD = 6 V 230 RDELAY range (2) Propagation delay from CS+ to OUT1 (2) Propagation delay from CS+ to CLF (2) mV ns 24.3 50.0 100.0 kΩ 80 VCS = threshold + 60 mV ns 70 CURRENT SENSE AMPLIFIER VOO Output offset voltage I0 = OPEN; (VPOS = VNEG)= 1.25 V; measure AO - IO Closed loop dc gain -100 0 100 mV I0 = FLOAT; VPOS = 1.26 V; VNEG = 1.25 V, RPOS = RNEG = 0 C 46 48 50 V/V Input impedance VPOS = 1.25 V, VNEG = 1.29 V, R = (VPOS - VNEG) / (IPOS - INEG) 5.5 8.3 12 kΩ VCM Input Common Mode Voltage Range VCM(max) is limited to (VDD-1.2V), RPOS = 0 0.3 5.6 V A0_Vol Minimum Output Voltage VPOS = 1.2 V; VNEG = 1.3 V; A0_ISINK = 250 μA Maximum Output Voltage VPOS =1.3 V; VNEG = 1.2 V; A0_ ISOURCE = 500 μA Input Bias Current, POS or NEG I0 = FLOAT; VPOS = VNEG = 0.8 V to 5.0 V, RPOS = RNEG = 0 V A0_Voh 3 0.15 0.3 3.1 3.5 -2 V 30 μA ZERO CURRENT REFERENCE (IO) IO (2) Reference voltage Measured at I0 0.54 0.6 0.66 V Input transition voltage Output impedance With respect to IO reference 10 60 120 mV IZERO = 0.6 V 10 15 21 kΩ As designed and characterized. Not 100% tested in production. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UCD7230A 5 UCD7230A SLUS995 – NOVEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VDD = PVDD = 12 V, 4.7 μF from VDD to AGND, 1 μF from PVDD to PGND, 0.1 μF from CSBIAS to AGND, 0.22 μF from BST to SW, TA = TJ = -40°C to +125°C, RCS+ = 5 kΩ, RDLY = 50 kΩ over operating free-air temperature range (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOW-SIDE OUTPUT DRIVER (OUT2) Source current (3) Sink current (3) Source current Sink current Rise time (3) (3) VDD = 12 V, IN = high, VOUT2 = 5 V 2.2 VDD = 12 V, IN = low, VOUT2 = 5 V 3.5 VDD = 4.75 V, IN = high, VOUT2 = 0 1.6 VDD = 4.75 V, IN = low, VOUT2 = 4.75 V (3) A 2 CLOAD = 2.2 nF, VDD = 12 V 15 Fall time (3) CLOAD = 2.2 nF, VDD = 12 V 15 Output with VDD <UVLO VDD = 1.0 V, Isink = 10 mA 0.8 Propagation delay from IN to OUT2 (3) CLOAD = 2.2 nF, IN rising, SW = 2.5 V, BST = PVDD = VDD = 12 V 30 VDD = 12 V, BST = 12 V IN = High, VOUT1 = 5 V 1.7 VDD = 12 V, BST = 12 V IN = Low, VOUT1 = 5 V 3.5 VDD = 4.75 V = BST = 4.75 V, IN = High, VOUT1 =0 1 VDD = 4.75 V, BST = 4.75 V, IN = Low, VOUT1 = 4.75 V 2.4 CLOAD = 2.2 nF OUT1 to SW, VDD = 12 V 20 CLOAD = 2.2 nF OUT1 to SW, VDD = 12 V 15 CLOAD = 2.2 nF, IN falling, SW = 2.5 V, BST = PVDD = VDD = 12 V 30 ns 1.2 V ns HIGH-SIDE OUTPUT DRIVER (OUT1) Source current (3) Sink current (3) Source current Sink current (3) (3) Rise time (3) Fall time (3) Propagation delay from IN to OUT1 (3) (3) 6 A ns As designed and characterized. Not 100% tested in production. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UCD7230A UCD7230A www.ti.com SLUS995 – NOVEMBER 2009 DEVICE INFORMATION IN SRE VDD CS– CSBIAS RGW Package (Top View) 20 19 18 17 16 2 14 OUT1 DLY 3 13 BST ILIM 4 12 PVDD CLF 5 11 OUT2 6 7 8 9 10 PGND AGND NEG SW POS 15 A0 1 I0 3V3 TERMINAL FUNCTIONS NAME No. I/O DESCRIPTION 3V3 1 O Regulated 3.3-V rail. The onboard linear voltage regulator is capable of sourcing up to 10 mA of current. Bypass with 0.22-μF ceramic capacitance from this pin to analog ground, AGND. AO 7 O Current sense linear amplifier output. The output voltage level on this pin represents the average output current. Any value below the level on the I0 pin represents negative output current. AGND 2 - Analog ground return. BST 13 I Floating OUT1 driver supply powered by an external Schottky diode from the PVDD pin during the synchronous MOSFET on time. CLF 5 O Current Limit Flag. The CLF signal is a 3.3-V digital output which is latched high after an over current event, triggered by either of the two current sense comparators and reset after two rising edges received on the IN pin. CLF is also asserted on power-up while VDD is below the UVLO threshold. CLF goes low when VDD crosses the UVLO threshold. CSBIAS 16 I Supply pin for the high-side current sense comparator. CS+ 17 I Non-inverting Input for the high side current sense comparator. A resistor connected between this pin and the high side MOSFET drain, in conjunction with the DLY resistor sets the high-side current limit threshold. DLY 3 I Requires a resistor to AGND for setting the current sense blanking time for both the high-side and low-side current sense comparators. The value of this resistor in conjunction with the resistor in series with the CS+ pin sets the high side current sense threshold. ILIM 4 I Output current limit threshold set pin. The output current threshold is 1/10th of the value set on this pin. If left floating the voltage on this pin is 0.55 V. The voltage on the ILIM pin can range from 0.25 V to 1V to set the threshold from 25 mV to 100 mV. IN 20 I The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up to 2 MHz. A Schmitt trigger input comparator desensitizes this pin from external noise. IO 6 I Sets the current sense linear amplifier “Zero” output level. The default value is 0.6 V which allows negative current measurement. OUT1 14 I The high-side high-current TrueDrive™ driver output. Drives the gate of the high-side buck MOSFET between SW and BST. OUT2 11 I The low-side high-current TrueDrive™ driver output. Drives the gate of the low-side synchronous MOSFET between PVDD and PGND. NEG 9 I Inverting input of the output current sense amplifier and current limit comparator. PGND 10 - Power ground return. This pin should be connected close to the source of the low-side synchronous rectifier MOSFET. POS 8 I Non-inverting input of the output current sense amplifier and current limit comparator. PPAD PAD – Thermal pad. Connect directly to AGND for thermal performance and EMI reduction. PVDD 12 - Supply pin provides power for the output drivers. It is not connected internally to the VDD supply rail. The bypass capacitor for this pin should be returned to PGND. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UCD7230A 7 UCD7230A SLUS995 – NOVEMBER 2009 www.ti.com TERMINAL FUNCTIONS (continued) NAME No. I/O SRE 19 I SW 15 I/O VDD 18 - DESCRIPTION Synchronous Rectifier Enable. The SRE pin is a high impedance digital input capable of accepting 3.3-V logic level signals, used to disable the synchronous rectifier switch. The synchronous rectifier is disabled when this signal is low. A Schmitt trigger input comparator desensitizes this pin from external noise. OUT1 gate drive return and square wave input to output inductor. Supply input pin to power the internal circuitry except the driver outputs. The UCD7230A accepts an input range of 4.5 V to 15.5 V. FUNCTIONAL BLOCK DIAGRAM VDD CSBIAS 18 16 CS+ 17 BST OUT1 SW 13 14 15 PVDD OUT2 PGND 12 11 10 + UVLO IDLY Enable 3V3 1 + CLF 5 AGND 2 POS 9 NEG 7 AO Overcurrent Current Limit Logic ILIM/10 + UCD7230A 8 8 Drive and Deadtime Control Logic (D, 1-D) 3V3 Reg 48 x 4 IO + 0.6 V Blanking ILIM 6 20 IN 3 DLY 19 SRE UDG-09163 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UCD7230A UCD7230A www.ti.com SLUS995 – NOVEMBER 2009 APPLICATION INFORMATION Introduction The UCD7230A is a synchronous buck driver with peak-current limiting. It is a member of the UCD7K family of digital compatible drivers suitable either for applications utilizing digital control techniques or analog applications that require local fast peak current limit protection. In systems using the UCD7230A, the feedback loop is closed externally and the IN signal represents the PWM information required to regulate the output voltage. The PWM signal may be implemented by either a digital or analog controller. The UCD7230A has two over-current protection features, one that limits the peak current in the high-side switch and one that limits the output current. Both limits are individually programmable. The internal current sense blanking enables ease of design with real-world signals. In addition to over current limit protection, current sense signals can be conditioned by the on board amplifier for use by the system controller. VIN UCD7230A 18 VDD CS+ 17 19 SRE CSBIAS 16 UCD9112 ADC3 VD25 RB0 DPWMA0 20 IN SW 15 RPOS AD33 VOUT EAP GSENSE EAM RST AVSS DPWMB0 RB1/TMRI1 1 3V3 2 AGND 3 DLY PVDD 12 4 ILIM OUT2 11 5 CLF PGND 10 6 IO VOUT OUT1 14 GSENSE BST 13 RNEG COMMUNICATION (Programming and Status Reporting) ADC2 7 AO NEG 9 POS 8 UDG-09164 Figure 1. Single-Phase Synchronous Buck Converter using UCD9112 and one UCD7230A Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UCD7230A 9 UCD7230A SLUS995 – NOVEMBER 2009 www.ti.com VIN RB0 UCD7230A 18 VDD CS+ 17 19 SRE CSBIAS 16 UCD9112 RB0 ADC3 VD25 20 IN DPWMA0 SW 15 VOUT EAP GSENSE EAM RST VOUT RPOS1 AD33 AVSS DPWMB0 RB1/TMRI1 1 3V3 OUT1 14 2 AGND 3 DLY PVDD 12 4 ILIM OUT2 11 5 CLF PGND 10 6 IO BST 13 GSENSE RNEG1 COMMUNICATION (Programming and Status Reporting) 7 AO ADC2 NEG 9 POS 8 UCD7230A RB0 DPWMA1 18 VDD CS+ 17 19 SRE CSBIAS 16 20 IN SW 15 RPOS2 1 3V3 2 AGND 3 DLY PVDD 12 DPWMB1 4 ILIM OUT2 11 RB3/TMRI0 5 CLF PGND 10 6 IO OUT1 14 BST 13 RNEG2 ADC5 7 AO NEG 9 POS 8 UDG-09165 Figure 2. Multi-Phase Synchronous Buck Converter using UCD9112 and two UCD7230A Supply Requirements The UCD7230A operates on a supply range of 4.5 V to 15.5 V. The supply voltage should be applied to three pins, PVDD, VDD, and CSBIAS. PVDD is the supply pin for the lower driver, and has the greatest current demands. The supply connection to PVDD is also the point where an external Schottky diode provides current to the high side flying driver. PVDD should be bypassed to PGND with a low ESR ceramic capacitor. In the same fashion, the flying driver should be bypassed between BST and SW. VDD and CSBIAS are less demanding supply pins, and should be resistively coupled to the supply voltage for isolation from noise generated by high current switching and parasitic board inductance. Use a value of 10 Ω for CSBIAS and 1 Ω for VDD. VDD should be bypassed to AGND with a 4.7-μF ceramic capacitor while CSBIAS should be bypassed to AGND with 0.1 μF. Although the three supply pins are not internally connected, they must be biased to the same voltage. It is important that all bypassing be done with low parasitic inductance techniques to good ground planes. 10 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UCD7230A UCD7230A www.ti.com SLUS995 – NOVEMBER 2009 PGND and AGND are the ground return connections to the chip. Ground plane construction should be used for both pins. For a MOSFET driver operating at high frequency, it is critical to minimize the stray inductance to minimize overshoot, undershoot, and ringing. The low output impedance of the drivers produces waveforms with high di/dt. This induces ringing in the parasitic inductances. It is highly desirable that the UCD7230A and the MOSFETs be collocated. PGND and the AGND pins should be connected to the PowerPAD™ of the package with two thin traces. It is critical to ensure that the voltage potential between these two pins does not exceed 0.3 V. Although quiescent VDD current is low, total supply current depends on the gate drive output current required for the capacitive load and the switching frequency. Total supply current is the sum of quiescent VDD current and the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT current can be calculated from (IOUT = Qg x f), where f is the operating frequency. Reference / External Bias Supply The UCD7230A includes a series pass regulator to provide a regulated 3.3 V at the 3V3 pin that can be used to power other circuits such as the UCD91xx, a microcontroller or an ASIC. 3V3 can source 10 mA of current. For normal operation, place a 0.22-μF ceramic capacitor between 3V3 and AGND. Control Inputs The IN and SRE pins are high impedance digital inputs designed for 3.3-V logic-level signals. They both have 100-kΩ pull-down resistors. Schmitt Trigger input stage design immunizes the internal circuitry from external noise. IN is the command input for the upper driver, OUT1, and can function up to 2 MHz. SRE controls the function of the lower driver, OUT2. When SRE is false (low), OUT2 is held low. When SRE is true, OUT2 is inverted from OUT1 with appropriate delays that preclude cross conduction in the Buck MOSFETs. Driver Stages The driver outputs utilize Texas Instruments’ TrueDrive™ architecture, which delivers rated current into the gate of a MOSFET when it is most needed, during the Miller plateau region of the switching transition. This provides best switching speeds and reduces switching losses. TrueDrive™ consists of pull-up/ pull-down circuits using bipolar and MOSFET transistors in parallel. This hybrid output stage also allows relatively constant current sourcing even at reduced supply voltages. The low-side high-current output stage of the UCD7230A device is capable of sourcing 1.7-A and sinking 3.5-A current pulses and swings from PVDD to PGND. The high-side floating output driver is capable of sourcing 2.2-A and sinking 3.5-A peak-current pulses. This ratio of gate currents, common to synchronous buck applications, minimizes the possibility of parasitic turn on of the low-side power MOSFET due to dv/dt currents during the rising edge switching transition. See the typical curves of sink and source current in Figure 3 and Figure 4 . If further limiting of the rise or fall times to the power device is desired, an external resistance can be added between the output of the driver and the power MOSFET gate. The external resistor also helps remove power dissipation from the driver. Driver outputs follow IN and SRE as previously described provided that VDD and 3V3 are above their respective under-voltage lockout thresholds. When the supplies are insufficient, the chip holds both OUT1 and OUT2 low. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UCD7230A 11 UCD7230A SLUS995 – NOVEMBER 2009 www.ti.com It is worth reiterating the need mentioned in the supply section for sound high frequency design techniques in the circuit board layout and bypass capacitor selection and placement. Some applications may generate excessive ringing at the switch-inductor node. This ringing can drag SW to negative voltages that might cause functional irregularities. To prevent this, carefull board layout and appropriate snubbing are essential. In addition, it may be appropriate to couple SW to the inductor with a 1-Ω resistor, and then bypass SW to PGND with a low impedance Schottky diode. SINK/SOURCE CURRENT vs HIGH-SIDE DRIVER OUTPUT VOLTAGE SINK/SOURCE CURRENT vs LOW-SIDE DRIVER OUTPUT VOLTAGE 5.0 ISINK 4.5 ISOURCE/ISINK – Source Current/Sink Current – A ISOURCE/ISINK – Source Current/Sink Current – A 5.0 VVDD = 12 V 4.0 ISOURCE 3.5 3.0 2.5 2.0 ISINK 1.5 1.0 VVDD = 5 V 0.5 ISOURCE 0 4.5 ISOURCE VVDD = 12 V 4.0 ISINK 3.5 3.0 2.5 2.0 ISINK 1.5 VVDD = 5 V 1.0 ISOURCE 0.5 0 0 1 2 3 4 5 OUT1 – High-Side Driver Output Voltage – V 6 0 1 2 3 4 5 6 OUT2 – Low-Side Driver Output Voltage – V Figure 3. Figure 4. Current Sensing and Overload Protection Since the UCD7230A is physically collocated with the high-current elements of the power converter, it is logical that current be monitored by the chip. An internal instrumentation amplifier conditions current sense signals so that they can be used by the control chip generating the PWM signal. POS and NEG are inputs to an instrumentation amplifier circuit. This amplifier has a nominal gain of 48 and presents its output at AO. This can be used to monitor either an external current sense shunt or a parallel RC around the buck inductor shown in Figure 5. The shunt yields the highest accuracy and is insensitive to inductor core saturation effects. It comes with the price of added power dissipation. Using the shunt, AO is calculated in Equation 1. AO = (48 ´ IOUT ´ RSHUNT ) + IO (1) The internal configuration of the instrumentation amplifier is such that AO is 0.6 V when POS – NEG = 0. Because of this output offset, the amplifier can accurately pass information for both positive and negative load current. The offset is controlled by IO. If IO is left to float, the offset is 0.6 V. 0.6 V is present at IO through an internal 10-kΩ resistor and should be bypassed to AGND. If a higher value of offset is desired, a voltage in excess of 0.66 V can be externally applied to IO. Once IO is forced above 0.66 V, the internal 10 kΩ is disconnected, and the AO output offset is now equal to the voltage applied to IO. 12 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UCD7230A UCD7230A www.ti.com SLUS995 – NOVEMBER 2009 SW IO + POS 8.33 kΩ I/O Buffer Amplifier 400 kΩ 8 + RSHUNT NEG VOUT 8.33 kΩ 6 Current Sense Amplifier AO 400 kΩ 9 7 COUT UDG-09171 Figure 5. Current Sense Using External Shunt SW IO + POS RPOS 8.33 kΩ I/O Buffer Amplifier 400 kΩ 8 L + R + C NEG VOUT 8.33 kΩ 6 Current Sense Amplifier AO 400 kΩ 9 7 RNEG COUT UDG-09172 Figure 6. Lossless Average Output Current Sensing Using DC Resistance of the Output Inductor Figure 6 also shows lossless current sensing utilizing an RC across the buck inductor to generate an analog of the IR drop in the copper of the inductor. As long as the RPOS x C time constant is the same as the L/R of the inductor and its parasitic equivalent series resistance, then the voltage on C is the same as the IR drop on the parasitic inductor resistance. A resistor, RNEG = RPOS is used for amplifier bias current cancellation. The transfer function of the amplifier is calculated in Equation 2. AO = (A ´ IOUT ´ RCOPPER ) + IO (2) With the addition of RPOS and RNEG, the natural gain, A, of the current sense is predictably decreased as shown in Equation 3. 48 A= æ R ö 1 + ç POS ÷ è 8.33kW ø (3) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UCD7230A 13 UCD7230A SLUS995 – NOVEMBER 2009 www.ti.com For RPOS << 8.33 kΩ, the gain is 48. While the 400 kΩ and 8.33 kΩ are well matched, it is important to keep RPOS as small as possible since they have absolute variation from chip-to-chip and over temperature. The graph in Figure 7 shows the band of expected gain for A as a function of RPOS. The gain variation at RPOS = 1 kΩ results in around ±4% error. However, the tolerance of the value of R in the inductor has a more significant effect on measurement accuracy as does the temperature coefficient of R. Copper has a temperature coefficient of approximately 3800 ppm/°C. For a 100°C rise in winding temperature, the dc resistance of the inductor increases by 38%. The worst case scenario would be a cracked core or under-designed inductor in which cases the core could tend towards saturation. In that scenario, inductor current could change slope drastically and is not correctly modeled by the capacitor voltage. . CURRENT SENSE AMPIFIER GAIN vs POS INPUT RESISTANCE 49 Current Sense Amplifier Gain – V/V 47 Nominal Maximum Gain Tolerance 45 43 41 39 Minimum Gain Tolerance 37 35 0 500 1000 1500 2000 RPOS – POS Input Resistance – W Figure 7. Current Sense Amplifier Gain as a Function of RPOS The RC time constant is . The LR time constant is shown in Equation 5. tR C = R P O S ´ C (4) L tLR = R (5) When Equation 4 equals Equation 5, the voltage across the capacitor is the same as the voltage drop across the equivalent resistance of the inductor. If the time constraints don’t match, (Equation 4 does not equal Equation 5) the calculation of the ripple current amplitude can be incorrect. Load transients result in overshoot when tRC is much shorter than tLR. Load transients result in undershoot when tRC is much longer than tLR. While the amplifier faithfully passes the sensed dc current signal, it should be noted that the amplifier is bandwidth limited for normal switching frequencies. Therefore, AO represents a moving average of the sensed current. 14 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UCD7230A UCD7230A www.ti.com SLUS995 – NOVEMBER 2009 The amplifier output can go up to 3.3 V, so reasonable designs limit full scale to 3.0 V. Should attenuation be necessary, use a resistive divider between AO and the control chip A/D input as shown in Figure 8. To A/D 7 A0 UDG-09166 Figure 8. Attenuating and Filtering the Voltage Representation of the Average Output Current While the current sense amplifier is useful for accurate current monitoring or controlling overload conditions, extreme overload conditions must be handled in timeframes that are generally much shorter than the A/D of a control chip can achieve. Therefore, there are two comparators on the UCD7230A to sense extreme overload and protect the driven power MOSFETs. Extreme current overload is handled in two ways by the UCD7230A. One is a comparator that monitors the voltage between POS and NEG, or effectively the output current of the converter.. The other is a comparator that monitors the voltage drop across the high-side MOSFET, or effectively the input current. Should either condition exceed a preset value, OUT1 is immediately turned off for the remainder of the cycle. To program the high-side MOSFET current limit threshold, a value of resistance from DLY to AGND must first be chosen to establish a blanking time during which the comparator outputs are ignored or blanked. Blanking is required because the high amplitude ringing that occurs on the rising edge of SW would otherwise cause false triggering of the fault comparators. The required amount of blanking time is a function of the switching speed of the high-side FET, the PCB layout, and whether or not a snubber network is being used. A value of 100ns after the rising edge of SW is a typical starting point. In the UCD7230A, the blanking interval timing begins at the rising edge of IN. Due to propagation delays and anti-cross-conduction intervals, there is approximately 45ns delay from the rising edge of IN to the rising edge of SW. This propagation delay must be added to the required amount of blanking time after the rising edge of SW when calculating the overall blanking time. The overall blanking time is calculated in Equation 6. tBLANK (ns ) » 5 ´ RDLY (kW ) (6) where • RDLY is the resistor from DLY to AGND RDLY should be limited to a range between 25 kΩ and 100 kΩ. The blanking interval should be kept as short as possible, consistent with reliable fault detection. The blanking interval (minus the 45-ns propagation delay) sets the minimum duty cycle pulse width where high-side fault detection is possible. When the on-time of the IN pulses are narrower than the blanking time, the high-side fault detection comparator is held off for the entire on-time and is, therefore, blind to any high-side faults. Once RDLY has been chosen, the value of RCS+ can be calculated. RCS+ is the resistor from the CS+ pin to the drain of the high-side FET which sets the high-side fault detection threshold. When the high-side FET is on, the current flow in the FET produces a voltage drop across the device. The magnitude of this voltage is equal to the RDS(on) times the current through the FET. An absolute maximum current level can be set during the design stage and the resultant voltage drop across the FET can be calculated. This maximum voltage drop, ΔVMAX, sets the high-side fault threshold. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UCD7230A 15 UCD7230A SLUS995 – NOVEMBER 2009 www.ti.com Internally, a high-speed comparator monitors the voltage between the SW pin and the CS+ pin when the high-side FET is on. Whenever the voltage on the SW pin is lower than the voltage on the CS+ pin, a fault is flagged. To prevent false tripping during the ringing that accompanies the rising edge of SW, the output of the comparator is held off (blanked) for a time interval set by the DLY pin. The voltage on the CS+ pin is set by a resistor connected from the pin to the high-side FET drain. The RCS+ resistor value is calculated from Equation 7. DVMAX ´ RDLY RCS+ = 1200 (7) where • • ΔVMAX is in mV RCS+ and RDLY are in kΩ For example, if ΔVMAX is 100 mV and RDLY is 50 kΩ, then RCS+ is 4.2 kΩ. Equation 7 can be restated as Equation 8. RCS+ = (R DS(on )HOT ) ´ IMAX ´ RDLY 1200 (8) where • • • • IMAX is the peak current flowing through the high-side FET when it is on RCS+ and RDLY in kΩ RDS(on) in mΩ IMAX is in amperes IMAX is the sum of the load current and one half of the inductor ripple current. As a general rule, the value of IMAX should be set to about 150% of the expected maximum steady-state load current. This allows some headroom to avoid nuisance fault events due to transient load currents and the inductor ripple current. With low inductor values and lower switching frequencies, the magnitude of the inductor ripple current can be quite high. Be certain to account for it in the IMAX calculation. Also, keep in mind that the RDS(on) of a FET has a large positive temperature coefficient of approximately 4000 ppm/°C. The junction temperature of the FET is elevated when operating at currents near the IMAX threshold. In Equation 9, use a value of RDS(on)HOT that is approximately 140% of its typical room temperature value. Note that the FET, when turned on, is driven to a VGS enhancement voltage of approximately the value of VDD. Most FET data sheets provide RDS(on) values for VGS values of 4.5 V and 10 V. Most manufacturers provide a graph of RDS(on)) vs VGS. If provided, use the graph with the value of VGS = VDD to determine the room temperature RDS(on) value. A current sink proportional to RDLY pulls current through RCS+. This sets up a reference voltage drop equal to ΔVMAX. It is important to connect the far end of the RCS+ resistor directly to the drain of the high-side FET. This should be made with a separate, non-current-carrying trace. This ensures that only the RDS(on) of the FET influences the fault threshold voltage and not the resistance of the PC board traces. The blanking time for the output comparator is identical to the input comparator. The output comparator threshold is calculated in Equation 9. V VCS(out ) = ILIM 10 (9) where • • VCS(out) is the threshold of allowed voltage between the POS and NEG pins VILIM is the voltage on the ILIM pin Note that the ILIM is internally connected to 0.5 V through a 42-kΩ resistor. Any voltage between 0.25 V and 1.0 V can be applied to ILIM. For voltages above 1.0 V, the maximum VCS(OUT) threshold is clamped to 0.1 V. Possible methods for setting ILIM are shown in Figure 9. When using the output comparator to monitor the voltage on the parallel sensing capacitor across the inductor, the same caveats apply as described for the current sense amplifier. Figure 9 through Figure 12 show different methods of setting the current limit voltage. Table 1 lists the current limit value settings when using the GPIO outputs as show in Figure 9 only. 16 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UCD7230A UCD7230A www.ti.com SLUS995 – NOVEMBER 2009 UCD7230A Digital Controller VCC GND UCD7230A Digital Controller 1 3V3 2 AGND GND 4 ILIM PWM VCC 1 3V3 2 AGND 4 ILIM RF 40 kW GPIO1 20 kW GPIO2 10 kW UDG-09168 GPIO3 2.5 kW GPIO4 UDG-09167 Figure 9. Setting the ILIM Voltage GPIO Outputs Figure 10. Setting the ILIM Voltage Using a PWM Output UCD7230A Digital Controller VCC GND R1 1 3V3 2 AGND UCD7230A R2 4 ILIM 1 3V3 2 AGND 4 ILIM CF UDG-09169 UDG-09170 Figure 11. Setting the ILIM Voltage Using a Resistor Divider Figure 12. Setting the ILIM Voltage Using an Internal Setpoint Table 1. Current Limit Value Settings CURRENT LIMIT (ILIM) SETPOINT (mV) GPIO3 GPIO2 GPIO1 GPIO4 500 OPEN OPEN OPEN OPEN ILIM0 0 0 0 1 0 ILIM1 140 0 0 0 0 ILIM2 290 0 1 1 0 ILIM3 430 0 1 0 0 ILIM4 570 1 0 1 0 ILIM5 720 1 0 0 0 ILIM6 860 1 1 1 0 ILIM7 1000 1 1 0 0 ILIM (open) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UCD7230A 17 UCD7230A SLUS995 – NOVEMBER 2009 www.ti.com If either comparator threshold is exceeded, OUT1 is immediately turned off for the remainder of the cycle and CLF is asserted true. Upon the rising edge of IN, the switches resume normal operation, but the CLF assertion is maintained. If a fault is not detected in this switching cycle, then the next rising edge of IN removes the CLF assertion. However, if one of the comparators detects a fault, then CLF assertion continues. The control device monitors CLF and decides how to handle the fault condition. During this monitoring period, the protection comparators protect the power MOSFET switches on a cycle-by-cycle basis. If the output-sense comparator (POS - NEG) detects continuous overcurrent, then the driver assumes 0% duty cycle until the current drops to a safe value. Note that when a fault condition causes OUT1 to be driven low, OUT2 behaves as if the input pulse had been terminated normally. In some fault conditions, it is advantageous to drive OUT2 low. SRE can be used to cause OUT2 to remain low at the discretion of the control chip. This can be used to achieve faster discharge of the inductor and also to fully disconnect the converter from the output voltage. Startup Handshaking The UCD7230A has a built-in handshaking feature to facilitate efficient start-up of the digitally controlled power supply. At start-up the CLF flag is held high until all the internal and external supply voltages of the device are within their operating range. Once the supply voltages are within acceptable limits, CLF goes low and the device processes input commands. The digital controller should monitor CLF at start-up and wait for CLF to go low before sending pwm information to the UCD7230A. Thermal Management The usefulness of a driver is greatly affected by the drive power requirements of the load and the thermal characteristics of the device package. In order for a power driver to be used over a particular temperature range, the package must allow for the efficient removal of the heat while keeping the junction temperature (TJ) within rated limits. The UCD7230A is available in the QFN package with an exposed pad that removes thermal energy from the semiconductor junction. As illustrated in Reference [3 & 4], the QFN package offers a lead-frame die pad that is exposed at the base of the package. This pad is soldered to the copper on the PC board (PCB) directly underneath the device package, reducing the θJA. The PC board must be designed with thermal lands and thermal vias to complete the heat removal subsystem, as summarized in Reference [3]. Note that the PowerPAD™ is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate which is the ground of the device. The PowerPAD™ should be connected to the quiet ground (AGND) of the circuit. REFERENCES 1. Power Supply Seminar SEM-1600 Topic 6: A Practical Introduction to Digital Power Supply Control, by Laszlo Balogh, Texas Instruments Literature No. SLUP224 2. Power Supply Seminar SEM–1400 Topic 2: Design and Application Guide for High Speed MOSFET Gate Drive Circuits, by Laszlo Balogh, Texas Instruments Literature No. SLUP133. 3. Application Report, Quad Flatpack No-Lead Logic Packages, Texas Instruments Literature No. SCBA017 4. Application Report, QFN/SON PCB Attachment, Texas Instruments Literature No. SLUA271 RELATED PRODUCTS DEVICE DESCRIPTION Literature Number UCD9240 Digital PWM System Controller SLUS766C UCD9220 Digital PWM System Controller SLUS904 UCD9112 Digital Dual-Phase Synchronous Buck Controller SLVS711 18 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): UCD7230A PACKAGE OPTION ADDENDUM www.ti.com 18-Dec-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty UCD7230ARGWR ACTIVE VQFN RGW 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCD7230ARGWT ACTIVE VQFN RGW 20 250 CU NIPDAU Level-2-260C-1 YEAR Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant UCD7230ARGWR VQFN RGW 20 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 UCD7230ARGWR VQFN RGW 20 3000 330.0 12.4 5.25 5.25 1.1 8.0 12.0 Q2 UCD7230ARGWT VQFN RGW 20 250 180.0 12.4 5.25 5.25 1.1 8.0 12.0 Q2 UCD7230ARGWT VQFN RGW 20 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCD7230ARGWR VQFN RGW 20 3000 367.0 367.0 35.0 UCD7230ARGWR VQFN RGW 20 3000 370.0 355.0 55.0 UCD7230ARGWT VQFN RGW 20 250 195.0 200.0 45.0 UCD7230ARGWT VQFN RGW 20 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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