www.ti.com SN54HC195 4-BIT PARALLEL-ACCESS SHIFT REGISTERS SCLS124A – DECEMBER 1992 – REVISED NOVEMBER 2007 FEATURES 1 • • • • • • SN54HC195 . . . J PACKAGE (TOP VIEW) Synchronous Parallel Load Positive-Edge-Triggered Clocking J and K Inputs to First Stage Complementary Outputs From Last Stage Package Options: Plastic and Ceramic DIPS and Ceramic Chip Carriers Dependable Texas lnstruments Quality and Reliability CLR J K A B C D GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA QB QC QD QD CLK SH/LD DESCRIPTION/ORDERING INFORMATION These 4-bit registers feature parallel inputs, parallel outputs, J-K serial inputs, shift/load control input, and a direct overriding clear. The registers have two modes of operation: parallel (broadside) load, and shift (in the direction QA and QD). J CLR NC VCC QA SN54HC195 . . . FK PACKAGE (TOP VIEW) K A NC B C 3 2 1 20 19 18 5 6 17 16 7 8 15 14 9 10 11 12 13 D GND NC SH/LD Shifting is accomplished synchronously when the shift/load control input is high. Serial data for this mode is entered at the J-K inputs. These inputs permit the first stage to perform as a J-K, D, or T type flip-flop as shown in the function table. 4 QB QC NC QD QD CLK Parallel loading is accomplished by applying the 4-bits of data and taking the shift/load control input low. The data is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited. NC − No internal connection LOGIC SYMBOL† The SN54HC195 is characterized for operation over the full military temperature range of –55°C to 125°C. CLR SH/LD CLK J K A B C D (1) (9) (10) (2) (3) (4) (5) R SRG4 M1 (SHIFT) M2 (LOAD) C3/1 1,3J 1,3K 2,3D 2,3D (15) (14) (6) (13) (7) (12) (11) † QA QB QC QD QD This symbol is in accordance with ANSI/IEEE Std 91−1984 and IEC Publication 617−12. Pin numbers shown are for J package. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1992–2007, Texas Instruments Incorporated SN54HC195 4-BIT PARALLEL-ACCESS SHIFT REGISTERS www.ti.com SCLS124A – DECEMBER 1992 – REVISED NOVEMBER 2007 LOGIC DIAGRAM (POSITIVE LOGIC) CLR CLK SH/LD J (1) (10) (9) (2) TG TG R K A (3) C1 1D TG (15) QA TG (4) TG R B (5) C1 1D (14) QB TG TG R C (6) C1 1D R D QC TG TG (7) (15) (13) C1 1D (12) (11) QD QD TG Pin numbers shown are for J package. 2 Submit Documentation Feedback Copyright © 1992–2007, Texas Instruments Incorporated Product Folder Link(s): SN54HC195 SN54HC195 4-BIT PARALLEL-ACCESS SHIFT REGISTERS www.ti.com SCLS124A – DECEMBER 1992 – REVISED NOVEMBER 2007 FUNCTION TABLE INPUTS CLR SH/LD CLK OUTPUTS SERIAL PARALLEL J K A B C D QA QB QC QD QD H L X X X X X X X X L L L L H L ↑ X X a b c d a b c d d H H L X X X X X X QA0 QB0 QC0 QD0 Q D0 H H ↑ L H X X X X QA0 QA0 QBn QCn Q Cn H H ↑ L L X X X X L QAn QBn QCn Q Cn H H ↑ H H X X X X H QAn QBn QCn Q Cn H H ↑ H L X X X X Q An QAn QBn QCn Q Cn TYPICAL CLEAR, SHIFT, AND LOAD SEQUENCES CLK CLR Serial Inputs J K SH/LD Parallel Data Inputs A H B L C H D L QA QB Outputs QC QD Serial Shift Clear Serial Shift Load Submit Documentation Feedback Copyright © 1992–2007, Texas Instruments Incorporated Product Folder Link(s): SN54HC195 3 SN54HC195 4-BIT PARALLEL-ACCESS SHIFT REGISTERS www.ti.com SCLS124A – DECEMBER 1992 – REVISED NOVEMBER 2007 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX –0.5 7 UNIT VCC Supply voltage range IIK Input clamp current VI < 0 or VI > VCC ±20 mA IOK Output clamp current VO < 0 or VO > VCC ±20 mA IO Continuous output current VO = 0 to VCC 25 mA 50 mA Lead temperature 1,6 mm (1/16 in) from case for 60 s: FK or J package 300 °C Lead temperature 1,6 mm (1/16 in) from case for 10 s: N package 260 °C 150 °C Continuous current through VCC or GND pins Tstg (1) Storage temperature range –65 V Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS VCC Supply voltage VCC = 2 V VIH High-level input voltage MIN NOM MAX 2 5 6 UNIT V 1.5 VCC = 4.5 V 3.15 V VCC = 6 V 4.2 VCC = 2 V 0 0.3 VCC = 4.5 V 0 0.9 VCC = 6 V VIL Low-level input voltage 0 1.2 VI Input voltage 0 VCC V VO Output voltage 0 VCC V VCC = 2 V 0 1000 tt Input transition (rise and fall) times VCC = 4.5 V 0 500 VCC = 6 V 0 400 –55 125 TA Operating free-air temperature V ns °C ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TA = 25°C MIN TYP SN54HC195 MAX MIN 2V 1.9 1.998 1.9 VI = VIH or VIL, IOH = –20 µA 4.5 V 4.4 4.499 4.4 6V 5.9 5.999 5.9 VI = VIH or VIL, IOH = –4 mA 4.5 V 3.98 4.30 3.7 VI = VIH or VIL, IOH = –5.2 mA 6V 5.48 VOH VI = VIH or VIL, IOL = 20 µA VOL 4 VCC VI = VIH or VIL, IOL = 4 mA VI = VIH or VIL, IOL = 5.2 mA II VI = VCC or 0 ICC VI = VCC or 0, CI VI = VCC or GND IO = 0 5.80 MAX UNIT V 5.2 2V 0.002 0.1 0.1 4.5 V 0.001 0.1 0.1 6V 0.001 0.1 0.1 4.5 V 0.17 0.26 0.4 6V 0.15 0.26 0.4 6V ±0.1 ±100 ±1000 nA 8 160 µA 10 10 pF 6V 2 V to 6 V Submit Documentation Feedback 3 V Copyright © 1992–2007, Texas Instruments Incorporated Product Folder Link(s): SN54HC195 SN54HC195 4-BIT PARALLEL-ACCESS SHIFT REGISTERS www.ti.com SCLS124A – DECEMBER 1992 – REVISED NOVEMBER 2007 TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54HC195 MIN MAX MIN MAX 2V 0 6 0 4.2 4.5 V 0 31 0 21 6V 0 36 0 25 2V 80 120 4.5 V 16 24 6V 14 20 2V 80 120 4.5 V 16 24 6V 14 20 2V 100 150 4.5 V 20 30 6V 17 26 2V 0 0 4.5 V 0 0 6V 0 0 VCC fclock Clock frequency CLK high or low tw Pulse duration CLR low tsu th Setup time, before CLK↑ Hold time, after CLK↑ SH/LD, or serial and parallel data, or CLR inactive SH/LD, or serial and parallel data, or CLR inactive UNIT MHz ns ns ns SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted), CL = 50 pF (1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd tpd QA thru QD or QD CLK QA thru QD or QD CLR tt Cpd (1) Any VCC TA = 25°C MIN TYP SN54HC195 MAX MIN 2V 6 12 4.2 4.5 V 31 50 21 6V 36 60 MHz 25 2V 67 145 220 4.5 V 17 29 44 6V 14 25 37 2V 67 150 225 4.5 V 17 30 45 6V 13 26 38 2V 28 75 110 4.5 V 8 15 22 6V 6 13 19 Power dissipation capacitance UNIT MAX No load, TA = 25°C ns ns ns 65 pF typ Load circuit and voltage waveforms are shown in previous pages. Submit Documentation Feedback Copyright © 1992–2007, Texas Instruments Incorporated Product Folder Link(s): SN54HC195 5 PACKAGE OPTION ADDENDUM www.ti.com 5-Sep-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp ACTIVE LCCC FK 20 1 TBD Call TI Call TI 5962-8682701EA ACTIVE CDIP J 16 1 TBD Call TI Call TI SN54HC195J ACTIVE CDIP J 16 1 TBD ACTIVE LCCC FK 20 1 TBD SNJ54HC195J ACTIVE CDIP J 16 1 TBD A42 Samples (Requires Login) 5962-86827012A SNJ54HC195FK (3) N / A for Pkg Type POST-PLATE N / A for Pkg Type A42 N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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